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[examples] add k32w061 platform (#4930)

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This commit is contained in:
doru91
2020-05-14 14:19:25 -07:00
committed by GitHub
parent 09dd07d823
commit 3122132af8
252 changed files with 103572 additions and 50125 deletions
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configure.ac
+5 -3
View File
@@ -788,14 +788,14 @@ AC_MSG_CHECKING([whether to build examples])
AC_ARG_WITH(examples,
[AS_HELP_STRING([--with-examples=TARGET],
[Build example applications for one of: simulation, cc1352, cc2538, cc2650, cc2652, efr32mg12, efr32mg13, efr32mg21,
gp712, jn5189, kw41z, nrf52811, nrf52833, nrf52840, qpg6095, samr21 @<:@default=no@:>@.
gp712, jn5189, k32w061, kw41z, nrf52811, nrf52833, nrf52840, qpg6095, samr21 @<:@default=no@:>@.
Note that building example applications also builds the associated OpenThread platform libraries
and any third_party libraries needed to support the examples.])],
[
case "${with_examples}" in
no)
;;
simulation|cc1352|cc2538|cc2650|cc2652|efr32mg12|efr32mg13|efr32mg21|gp712|jn5189|kw41z|nrf52811|nrf52833|nrf52840|qpg6095|samr21)
simulation|cc1352|cc2538|cc2650|cc2652|efr32mg12|efr32mg13|efr32mg21|gp712|jn5189|k32w061|kw41z|nrf52811|nrf52833|nrf52840|qpg6095|samr21)
;;
*)
AC_MSG_RESULT(ERROR)
@@ -817,6 +817,7 @@ AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG13], [test "${with_examples}" = "efr3
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_EFR32MG21], [test "${with_examples}" = "efr32mg21"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_GP712], [test "${with_examples}" = "gp712"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_JN5189], [test "${with_examples}" = "jn5189"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_K32W061], [test "${with_examples}" = "k32w061"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_KW41Z], [test "${with_examples}" = "kw41z"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52811], [test "${with_examples}" = "nrf52811"])
AM_CONDITIONAL([OPENTHREAD_EXAMPLES_NRF52833], [test "${with_examples}" = "nrf52833"])
@@ -900,6 +901,7 @@ AM_CONDITIONAL([OPENTHREAD_PLATFORM_SAMR21], [test "${with_platform}" = "samr
AM_CONDITIONAL([OPENTHREAD_PLATFORM_SIMULATION],[test "${with_platform}" = "simulation"])
AM_CONDITIONAL([OPENTHREAD_PLATFORM_NRF528XX], [test OPENTHREAD_PLATFORM_NRF52811 || test OPENTHREAD_PLATFORM_NRF52833 || test OPENTHREAD_PLATFORM_NRF52840])
AM_CONDITIONAL([OPENTHREAD_PLATFORM_K32W], [test OPENTHREAD_PLATFORM_K32W061 || test OPENTHREAD_PLATFORM_JN5189])
AM_COND_IF([OPENTHREAD_PLATFORM_POSIX], CPPFLAGS="${CPPFLAGS} -DOPENTHREAD_PLATFORM_POSIX=1", CPPFLAGS="${CPPFLAGS} -DOPENTHREAD_PLATFORM_POSIX=0")
@@ -1056,7 +1058,7 @@ examples/platforms/efr32mg21/sleepy-demo/Makefile
examples/platforms/efr32mg21/sleepy-demo/sleepy-demo-ftd/Makefile
examples/platforms/efr32mg21/sleepy-demo/sleepy-demo-mtd/Makefile
examples/platforms/gp712/Makefile
examples/platforms/jn5189/Makefile
examples/platforms/k32w/Makefile
examples/platforms/kw41z/Makefile
examples/platforms/nrf528xx/Makefile
examples/platforms/qpg6095/Makefile
examples/Makefile-jn5189
+13 -11
View File
@@ -43,7 +43,6 @@ BuildJobs ?= 10
configure_OPTIONS = \
--enable-cli \
--enable-diag \
--enable-ftd \
--enable-mtd \
--enable-ncp \
@@ -61,14 +60,16 @@ JN5189_MBEDTLS_CPPFLAGS = -DMBEDTLS_CONFIG_FILE='\"mbedtls-config.h\"'
JN5189_MBEDTLS_CPPFLAGS += -DMBEDTLS_USER_CONFIG_FILE='\"jn5189-mbedtls-config.h\"'
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/include/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/crypto
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/aes/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/drivers/sha/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/rom_apis/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189/dk6_jn5180/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/CMSIS/Include/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189/drivers/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug-console/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/drivers/components/serial_manager/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/drivers/components/uart/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/JN5189DK6/CMSIS/Include/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/
JN5189_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/mbedtls/
@@ -77,8 +78,8 @@ TopSourceDir := $(dir $(shell readlink $(firstword $(MAKEFILE
AbsTopSourceDir := $(dir $(realpath $(firstword $(MAKEFILE_LIST))))..
CONFIG_FILE = OPENTHREAD_PROJECT_CORE_CONFIG_FILE='\"openthread-core-jn5189-config.h\"'
CONFIG_FILE_PATH = $(AbsTopSourceDir)/examples/platforms/jn5189/
SIGN_IMAGE_PATH = $(AbsTopSourceDir)/third_party/nxp/JN5189/ImageSigning/
CONFIG_FILE_PATH = $(AbsTopSourceDir)/examples/platforms/k32w/jn5189/
SIGN_IMAGE_PATH = $(AbsTopSourceDir)/third_party/nxp/JN5189DK6/tools/imagetool/
COMMONCFLAGS := \
-fdata-sections \
@@ -91,6 +92,7 @@ COMMONCFLAGS := \
-DJENNIC_CHIP_FAMILY_NAME=_JN518x \
-DSDK_DEBUGCONSOLE=0 \
-D$(CONFIG_FILE) \
-DUSE_RTOS=0 \
-I$(CONFIG_FILE_PATH) \
$(NULL)
examples/Makefile-k32w061
Executable
+298
View File
@@ -0,0 +1,298 @@
#
# Copyright (c) 2019, The OpenThread Authors.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of the copyright holder nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
.NOTPARALLEL:
AR = arm-none-eabi-ar
CCAS = arm-none-eabi-as
CPP = arm-none-eabi-cpp
CC = arm-none-eabi-gcc
CXX = arm-none-eabi-g++
LD = arm-none-eabi-ld
STRIP = arm-none-eabi-strip
NM = arm-none-eabi-nm
RANLIB = arm-none-eabi-ranlib
OBJCOPY = arm-none-eabi-objcopy
BuildJobs ?= 10
configure_OPTIONS = \
--enable-cli \
--enable-diag \
--enable-ftd \
--enable-mtd \
--enable-ncp \
--with-ncp-bus=uart \
--enable-radio-only \
--enable-linker-map \
--with-examples=k32w061 \
$(NULL)
ifneq ($(DISABLE_BUILTIN_MBEDTLS), 1)
configure_OPTIONS += MBEDTLS_CPPFLAGS="$(K32W061_MBEDTLS_CPPFLAGS)"
endif
K32W061_MBEDTLS_CPPFLAGS = -DMBEDTLS_CONFIG_FILE='\"mbedtls-config.h\"'
K32W061_MBEDTLS_CPPFLAGS += -DMBEDTLS_USER_CONFIG_FILE='\"k32w061-mbedtls-config.h\"'
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/include/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061/drivers/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug-console/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/drivers/components/serial_manager/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/drivers/components/uart/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/nxp/K32W061DK6/CMSIS/Include/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/
K32W061_MBEDTLS_CPPFLAGS += -I$(AbsTopSourceDir)/third_party/mbedtls/repo/include/mbedtls/
TopSourceDir := $(dir $(shell readlink $(firstword $(MAKEFILE_LIST))))..
AbsTopSourceDir := $(dir $(realpath $(firstword $(MAKEFILE_LIST))))..
CONFIG_FILE = OPENTHREAD_PROJECT_CORE_CONFIG_FILE='\"openthread-core-k32w061-config.h\"'
CONFIG_FILE_PATH = $(AbsTopSourceDir)/examples/platforms/k32w/k32w061/
SIGN_IMAGE_PATH = $(AbsTopSourceDir)/third_party/nxp/K32W061DK6/tools/imagetool/
COMMONCFLAGS := \
-fdata-sections \
-ffunction-sections \
-Os \
-g \
-DCPU_K32W061HN \
-DCPU_JN518X \
-DCPU_JN518X_REV=2 \
-DJENNIC_CHIP_FAMILY_JN518x \
-DJENNIC_CHIP_FAMILY_NAME=_JN518x \
-DSDK_DEBUGCONSOLE=0 \
-D$(CONFIG_FILE) \
-DUSE_RTOS=0 \
-I$(CONFIG_FILE_PATH) \
$(NULL)
include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/common-switches.mk
CPPFLAGS += \
$(COMMONCFLAGS) \
$(target_CPPFLAGS) \
$(NULL)
CFLAGS += \
$(COMMONCFLAGS) \
$(target_CFLAGS) \
$(NULL)
CXXFLAGS += \
$(COMMONCFLAGS) \
$(target_CXXFLAGS) \
-fno-exceptions \
-fno-rtti \
$(NULL)
LDFLAGS += \
$(COMMONCFLAGS) \
$(target_LDFLAGS) \
-specs=nano.specs \
-specs=nosys.specs \
-Wl,--gc-sections \
$(NULL)
ECHO := @echo
MAKE := make
MKDIR_P := mkdir -p
LN_S := ln -s
RM_F := rm -f
INSTALL := /usr/bin/install
INSTALLFLAGS := -p
BuildPath = build
TopBuildDir = $(BuildPath)
AbsTopBuildDir = $(PWD)/$(TopBuildDir)
ResultPath = output
TopResultDir = $(ResultPath)
AbsTopResultDir = $(PWD)/$(TopResultDir)
TargetTuple = k32w061
ARCHS = cortex-m4
TopTargetLibDir = $(TopResultDir)/$(TargetTuple)/lib
TopTargetBinDir = $(TopResultDir)/$(TargetTuple)/bin
ifndef BuildJobs
BuildJobs := $(shell getconf _NPROCESSORS_ONLN)
endif
JOBSFLAG := -j$(BuildJobs)
#
# configure-arch <arch>
#
# Configure OpenThread for the specified architecture.
#
# arch - The architecture to configure.
#
define configure-arch
$(ECHO) " CONFIG $(TargetTuple)..."
(cd $(BuildPath)/$(TargetTuple) && $(AbsTopSourceDir)/configure \
INSTALL="$(INSTALL) $(INSTALLFLAGS)" \
CPP="$(CPP)" CC="$(CC)" CXX="$(CXX)" OBJC="$(OBJC)" OBJCXX="$(OBJCXX)" AR="$(AR)" RANLIB="$(RANLIB)" NM="$(NM)" STRIP="$(STRIP)" CPPFLAGS="$(CPPFLAGS)" CFLAGS="$(CFLAGS)" CXXFLAGS="$(CXXFLAGS)" LDFLAGS="$(LDFLAGS)" \
--host=arm-none-eabi \
--prefix=/ \
--exec-prefix=/$(TargetTuple) \
$(configure_OPTIONS))
endef # configure-arch
#
# build-arch <arch>
#
# Build the OpenThread intermediate build products for the specified
# architecture.
#
# arch - The architecture to build.
#
define build-arch
$(ECHO) " BUILD $(TargetTuple)"
$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \
all
endef # build-arch
#
# stage-arch <arch>
#
# Stage (install) the OpenThread final build products for the specified
# architecture.
#
# arch - The architecture to stage.
#
define stage-arch
$(ECHO) " STAGE $(TargetTuple)"
$(MAKE) $(JOBSFLAG) -C $(BuildPath)/$(TargetTuple) --no-print-directory \
DESTDIR=$(AbsTopResultDir) \
install
endef # stage-arch
#
# ARCH_template <arch>
#
# Define macros, targets and rules to configure, build, and stage the
# OpenThread for a single architecture.
#
# arch - The architecture to instantiate the template for.
#
define ARCH_template
CONFIGURE_TARGETS += configure-$(1)
BUILD_TARGETS += do-build-$(1)
STAGE_TARGETS += stage-$(1)
BUILD_DIRS += $(BuildPath)/$(TargetTuple)
DIRECTORIES += $(BuildPath)/$(TargetTuple)
configure-$(1): target_CPPFLAGS=$($(1)_target_CPPFLAGS)
configure-$(1): target_CFLAGS=$($(1)_target_CFLAGS)
configure-$(1): target_CXXFLAGS=$($(1)_target_CXXFLAGS)
configure-$(1): target_LDFLAGS=$($(1)_target_LDFLAGS)
configure-$(1): $(BuildPath)/$(TargetTuple)/config.status
$(BuildPath)/$(TargetTuple)/config.status: | $(BuildPath)/$(TargetTuple)
$$(call configure-arch,$(1))
do-build-$(1): configure-$(1)
do-build-$(1):
+$$(call build-arch,$(1))
stage-$(1): do-build-$(1)
stage-$(1): | $(TopResultDir)
$$(call stage-arch,$(1))
$(1): stage-$(1)
endef # ARCH_template
.DEFAULT_GOAL := all
all: stage
#
# cortex-m4
#
cortex-m4_target_ABI = cortex-m4
cortex-m4_target_CPPFLAGS = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
cortex-m4_target_CFLAGS = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
cortex-m4_target_CXXFLAGS = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
cortex-m4_target_LDFLAGS = -mcpu=cortex-m4 -mfloat-abi=soft -mthumb
# Instantiate an architecture-specific build template for each target
# architecture.
$(foreach arch,$(ARCHS),$(eval $(call ARCH_template,$(arch))))
#
# Common / Finalization
#
configure: $(CONFIGURE_TARGETS)
build: $(BUILD_TARGETS)
stage: $(STAGE_TARGETS)
DIRECTORIES = $(TopResultDir) $(TopResultDir)/$(TargetTuple)/lib $(BUILD_DIRS)
CLEAN_DIRS = $(TopResultDir) $(BUILD_DIRS)
all: stage post-build-step
$(DIRECTORIES):
$(ECHO) " MKDIR $@"
@$(MKDIR_P) "$@"
post-build-step:
$(SIGN_IMAGE_PATH)/sign_images.sh $(TopTargetBinDir)
clean:
$(ECHO) " CLEAN"
@$(RM_F) -r $(CLEAN_DIRS)
help:
$(ECHO) "Simply type 'make -f $(firstword $(MAKEFILE_LIST))' to build OpenThread for the following "
$(ECHO) "architectures: "
$(ECHO) ""
$(ECHO) " $(ARCHS)"
$(ECHO) ""
$(ECHO) "To build only a particular architecture, specify: "
$(ECHO) ""
$(ECHO) " make -f $(firstword $(MAKEFILE_LIST)) <architecture>"
$(ECHO) ""
examples/platforms/Makefile.am
+3 -3
View File
@@ -39,7 +39,7 @@ DIST_SUBDIRS = \
efr32mg13 \
efr32mg21 \
gp712 \
jn5189 \
k32w \
kw41z \
nrf528xx \
simulation \
@@ -86,8 +86,8 @@ if OPENTHREAD_PLATFORM_GP712
SUBDIRS += gp712
endif
if OPENTHREAD_PLATFORM_JN5189
SUBDIRS += jn5189
if OPENTHREAD_PLATFORM_K32W
SUBDIRS += k32w
endif
if OPENTHREAD_PLATFORM_KW41Z
examples/platforms/Makefile.platform.am
+5 -1
View File
@@ -74,7 +74,11 @@ include $(top_srcdir)/examples/platforms/gp712/Makefile.platform.am
endif
if OPENTHREAD_EXAMPLES_JN5189
include $(top_srcdir)/examples/platforms/jn5189/Makefile.platform.am
include $(top_srcdir)/examples/platforms/k32w/jn5189/Makefile.platform.am
endif
if OPENTHREAD_EXAMPLES_K32W061
include $(top_srcdir)/examples/platforms/k32w/k32w061/Makefile.platform.am
endif
if OPENTHREAD_EXAMPLES_KW41Z
examples/platforms/jn5189/Makefile.am
-132
View File
@@ -1,132 +0,0 @@
#
# Copyright (c) 2019, The OpenThread Authors.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of the copyright holder nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
include $(abs_top_nlbuild_autotools_dir)/automake/pre.am
lib_LIBRARIES = \
libopenthread-jn5189_plat.a \
libopenthread-jn5189_sdk.a
$(NULL)
# Do not enable -pedantic-errors for jn5189 driver library
override CFLAGS := $(filter-out -pedantic-errors,$(CFLAGS))
override CXXFLAGS := $(filter-out -pedantic-errors,$(CXXFLAGS))
# Do not enable -Wundef for jn5189 driver library
override CFLAGS := $(filter-out -Wundef,$(CFLAGS))
override CXXFLAGS := $(filter-out -Wundef,$(CXXFLAGS))
# Do not enable -Wcast-align for this platform
override CFLAGS := $(filter-out -Wcast-align,$(CFLAGS))
override CXXFLAGS := $(filter-out -Wcast-align,$(CXXFLAGS))
LIB_FLAGS = \
-DCPU_JN518X \
-DCPU_JN518X_REV=2 \
-DJENNIC_CHIP_FAMILY_JN518x \
-DJENNIC_CHIP_FAMILY_NAME=_JN518x \
-I$(top_srcdir)/include \
-I$(top_srcdir)/examples/platforms \
-I$(top_srcdir)/src/core \
-I$(top_srcdir)/third_party/nxp \
-I$(top_srcdir)/third_party/nxp/JN5189 \
-I$(top_srcdir)/third_party/nxp/JN5189/crypto \
-I$(top_srcdir)/third_party/nxp/JN5189/drivers \
-I$(top_srcdir)/third_party/nxp/JN5189/rom_apis \
-I$(top_srcdir)/third_party/nxp/JN5189/dk6_jn5180 \
-I$(top_srcdir)/third_party/nxp/CMSIS/Include \
-I$(top_srcdir)/third_party/nxp/JN5189/uMac/Include \
-I$(top_srcdir)/third_party/nxp/JN5189/Radio_JN5189/Include \
-I$(top_srcdir)/third_party/nxp/JN5189/JennicCommon/Include \
-I$(top_srcdir)/third_party/nxp/JN5189/MicroSpecific/Include \
-Wno-unknown-pragmas \
-Wno-sign-compare \
-Wno-unused-function \
-Wno-unused-parameter \
-Wno-empty-body \
$(NULL)
libopenthread_jn5189_sdk_a_CPPFLAGS = \
$(LIB_FLAGS) \
$(NULL)
libopenthread_jn5189_plat_a_CPPFLAGS = \
$(LIB_FLAGS) \
$(NULL)
PLATFORM_SOURCES = \
alarm.c \
diag.c \
flash.c \
logging.c \
misc.c \
radio.c \
entropy.c \
system.c \
uart.c \
settings_jn5189.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_assert.c \
@top_builddir@/third_party/nxp/JN5189/crypto/aes_alt.c \
@top_builddir@/third_party/nxp/JN5189/crypto/ksdk_mbedtls.c \
$(NULL)
libopenthread_jn5189_sdk_a_SOURCES = \
@top_builddir@/third_party/nxp/JN5189/startup_JN5189.c \
@top_builddir@/third_party/nxp/JN5189/system_JN5189.c \
@top_builddir@/third_party/nxp/JN5189/dk6_jn5180/pin_mux.c \
@top_builddir@/third_party/nxp/JN5189/dk6_jn5180/clock_config.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_gpio.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_clock.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_ctimer.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_wtimer.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_flash.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_usart.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_rng.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_flexcomm.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_reset.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_power.c \
@top_builddir@/third_party/nxp/JN5189/drivers/fsl_debug_console.c \
@top_builddir@/third_party/nxp/JN5189/drivers/aes/fsl_aes.c \
@top_builddir@/third_party/nxp/JN5189/drivers/sha/fsl_sha.c \
$(NULL)
libopenthread_jn5189_plat_a_SOURCES = \
$(PLATFORM_SOURCES) \
$(NULL)
PRETTY_FILES = \
$(PLATFORM_SOURCES) \
$(NULL)
Dash = -
libopenthread_jn5189_sdk_a_LIBADD = \
$(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
libopenthread_jn5189_plat_a_LIBADD = \
$(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
include $(abs_top_nlbuild_autotools_dir)/automake/post.am
examples/platforms/k32w/Makefile.am
Executable
+40
View File
@@ -0,0 +1,40 @@
#
# Copyright (c) 2019, The OpenThread Authors.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of the copyright holder nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# Use automake includes since we cannot use SUBDIRS feature due to cleanup
# errors - few targets may use the same source file but dependency file is
# created only once which leads to errors when auto-generated Makefile tries
# to remove .Po files that were already removed
if OPENTHREAD_EXAMPLES_JN5189
include jn5189/Makefile.am
endif
if OPENTHREAD_EXAMPLES_K32W061
include k32w061/Makefile.am
endif
examples/platforms/k32w/README.md
Executable
+14
View File
@@ -0,0 +1,14 @@
# OpenThread on K32W Example
This directory contains example platform drivers for [NXP Semiconductors K32W061 SoC][k32w061] and [NXP Semiconductors JN5189 SoC][jn5189].
[k32w061]: https://www.nxp.com/products/wireless/thread/k32w061-41-high-performance-secure-and-ultra-low-power-mcu-for-zigbeethread-and-bluetooth-le-5-0-with-built-in-nfc-option:K32W061_41
[jn5189]: https://www.nxp.com/products/wireless/thread/jn5189-88-t-high-performance-and-ultra-low-power-mcus-for-zigbee-and-thread-with-built-in-nfc-option:JN5189_88_T
To learn more about building and running the examples please check:
- [OpenThread on K32W061 examples][k32w061-page]
- [OpenThread on JN5189 examples][jn5189-page]
[k32w061-page]: ./k32w061/README.md
[jn5189-page]: ./jn5189/README.md
examples/platforms/k32w/jn5189/Makefile.am
Executable
+140
View File
@@ -0,0 +1,140 @@
#
# Copyright (c) 2019, The OpenThread Authors.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of the copyright holder nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
include $(abs_top_nlbuild_autotools_dir)/automake/pre.am
lib_LIBRARIES = \
libopenthread-jn5189_plat.a \
libopenthread-jn5189_sdk.a
$(NULL)
# Do not enable -pedantic-errors for jn5189 driver library
override CFLAGS := $(filter-out -pedantic-errors,$(CFLAGS))
override CXXFLAGS := $(filter-out -pedantic-errors,$(CXXFLAGS))
# Do not enable -Wcast-align for jn5189 driver library
override CFLAGS := $(filter-out -Wcast-align,$(CFLAGS))
override CXXFLAGS := $(filter-out -Wcast-align,$(CXXFLAGS))
LIB_FLAGS = \
-DCPU_JN518X \
-DCPU_JN518X_REV=2 \
-DJENNIC_CHIP_FAMILY_JN518x \
-DJENNIC_CHIP_FAMILY_NAME=_JN518x \
-DUSE_RTOS=0 \
-DgPWR_LDOMEM_0_9V_PD=0 \
-DNO_SYSCORECLK_UPD=0 \
-I$(top_srcdir)/include \
-I$(top_srcdir)/examples/platforms \
-I$(top_srcdir)/src/core \
-I$(top_srcdir)/third_party/nxp \
-I$(top_srcdir)/third_party/nxp/JN5189DK6 \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/devices/JN5189 \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/components/serial_manager \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/components/uart \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/devices/JN5189/drivers \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/CMSIS/Include \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/uMac/Include \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/DK6/Build/Include \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/DK6 \
-I$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common \
-Wno-unknown-pragmas \
-Wno-sign-compare \
-Wno-unused-function \
-Wno-unused-parameter \
-Wno-empty-body \
$(NULL)
libopenthread_jn5189_sdk_a_CPPFLAGS = \
$(LIB_FLAGS) \
$(NULL)
libopenthread_jn5189_plat_a_CPPFLAGS = \
$(LIB_FLAGS) \
$(NULL)
PLATFORM_SOURCES = \
src/alarm.c \
src/diag.c \
src/flash.c \
src/logging.c \
src/misc.c \
src/radio.c \
src/entropy.c \
src/system.c \
src/uart.c \
src/settings_k32w.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/utilities/fsl_assert.c \
@top_builddir@/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/aes_alt.c \
@top_builddir@/third_party/nxp/JN5189DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c \
$(NULL)
libopenthread_jn5189_sdk_a_SOURCES = \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/mcuxpresso/startup_JN5189.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/system_JN5189.c \
@top_builddir@/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/pin_mux.c \
@top_builddir@/third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.c \
@top_builddir@/third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.c \
@top_builddir@/third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.c \
@top_builddir@/third_party/nxp/JN5189DK6/components/uart/usart_adapter.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_gpio.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_ctimer.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_wtimer.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flash.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_usart.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_rng.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flexcomm.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_reset.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_power.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_aes.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_sha.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/utilities/debug_console/fsl_debug_console.c \
@top_builddir@/third_party/nxp/JN5189DK6/devices/JN5189/utilities/str/fsl_str.c \
@top_builddir@/third_party/nxp/JN5189DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c \
$(NULL)
libopenthread_jn5189_plat_a_SOURCES = \
$(PLATFORM_SOURCES) \
$(NULL)
PRETTY_FILES = \
$(PLATFORM_SOURCES) \
$(NULL)
Dash = -
libopenthread_jn5189_sdk_a_LIBADD = \
$(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
libopenthread_jn5189_plat_a_LIBADD = \
$(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
include $(abs_top_nlbuild_autotools_dir)/automake/post.am
examples/platforms/jn5189/Makefile.platform.am → examples/platforms/k32w/jn5189/Makefile.platform.am
+7 -8
View File
@@ -30,14 +30,13 @@
# JN5189 platform-specific Makefile
#
LDADD_COMMON += \
$(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_plat.a \
$(top_builddir)/examples/platforms/jn5189/libopenthread-jn5189_sdk.a \
$(top_srcdir)/third_party/nxp/JN5189/libraries/libMiniMac.a \
$(top_srcdir)/third_party/nxp/JN5189/libraries/libRadio.a \
$(top_srcdir)/third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a \
LDADD_COMMON += \
$(top_builddir)/examples/platforms/k32w/libopenthread-jn5189_plat.a \
$(top_builddir)/examples/platforms/k32w/libopenthread-jn5189_sdk.a \
$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a \
$(top_srcdir)/third_party/nxp/JN5189DK6/middleware/wireless/framework/XCVR/lib/libRadio.a \
$(NULL)
LDFLAGS_COMMON += \
-T $(top_srcdir)/examples/platforms/jn5189/jn5189.ld \
LDFLAGS_COMMON += \
-T $(top_srcdir)/examples/platforms/k32w/jn5189/jn5189.ld \
$(NULL)
examples/platforms/jn5189/README.md → examples/platforms/k32w/jn5189/README.md
+5 -9
View File
@@ -1,6 +1,6 @@
# OpenThread on NXP JN5189 Example
This directory contains example platform drivers for the [NXP JN5189][https://www.nxp.com/products/wireless/thread/jn5189-88-t-high-performance-and-ultra-low-power-mcus-for-zigbee-and-thread-with-built-in-nfc-option:jn5189_88_t] based on [JN5189-DK006][https://www.nxp.com/products/wireless/zigbee/advanced-development-kit-for-jn5189-88:jn5189-dk006] hardware platform.
This directory contains example platform drivers for the [NXP JN5189][jn5189] based on [JN5189-DK006][jn5189-dk006] hardware platform.
The example platform drivers are intended to present the minimal code necessary to support OpenThread. As a result, the example platform drivers do not necessarily highlight the platform's full capabilities.
@@ -19,7 +19,7 @@ $ ./script/bootstrap
If a network connection timeout is encountered, re-run the script.
Python-pip is also required for the build. User can install it by running "sudo apt-get install Python-pip" in bash. After installing Python-pip, execute "pip install PyCryptodome" in bash. This is needed for signing the built binary in order to load it on the board. Also, pycrypto "pip install pycrypto" is required for PKCS1.
Python-pip is also required for the build. User can install it by running "sudo apt-get install Python-pip" in bash. After installing Python-pip, execute "pip install pycryptodome" in bash. This is needed for signing the built binary in order to load it on the board. Also, pycrypto "pip install pycrypto" is required for PKCS1.
Windows 10 offers the possibility of running bash by installing "Ubuntu on Windows" from Microsoft Store. This application allows the user to use Ubuntu Terminal and run Ubuntu command line utilities including bash, ssh, git, apt and many more. If this option is used, it is recommended to add instructions for the path mapping in MCUXpresso IDE. This can be done after adding the project to the workspace by going to Run->"Debug Configuration"->"C/C++(NXP Semiconductors) MCU Application"->Source->Add. Then the user should create a path mapping such that MCUXpresso IDE will find the mount point for the "Ubuntu in Windows" subsystem. For example, user can enter compilation path recognized by Ubuntu as /mnt/c/<path-to-openthread>, while equivalent "Local file system path" is C:/<path-to-openthread>. This example assumes that the openthread package is installed on the C drive.
@@ -39,13 +39,13 @@ Connect to the board by plugging a mini-USB cable to the connector marked with T
OpenThread example application compiled binaries can be found in `<path-to-openthread>/output/jn5189/bin` and include FTD (Full Thread Device) and MTD (Minimal Thread Device) variants of CLI and NCP applications. The compiled binaries can be flashed onto the JN5189 using MCUXpresso IDE. This requires the following steps:
1. Import the JN5189 SDK into MCUXpresso IDE. This can be done by dragging and dropping the SDK archive into MCUXpresso IDE's Installed SDKs tab. The archive for SDK_2.6.0_JN5189DK6 can be downloaded from https://mcuxpresso.nxp.com.
1. Import the JN5189 SDK into MCUXpresso IDE. This can be done by dragging and dropping the SDK archive into MCUXpresso IDE's Installed SDKs tab. The archive for SDK_2.6.0_JN5189DK6 is available for download at https://mcuxpresso.nxp.com/en/welcome
2. In MCUXpresso IDE, go to File->Import->C/C++->"Existing Code as Makefile Project" and click Next.
3. Select the OpenThread folder as the "Existing Code Location". In the "Toolchain for Indexer Settings" list, be sure to keep the setting to "none". Click Finish.
3. Select the OpenThread folder as the "Existing Code Location". In the "Toolchain for Indexer Settings" list, be sure to keep the setting to <none>. Click Finish.
4. Right click on the newly created openthread project in the Workspace and go to Properties->"C/C++ Build"->"MCU Settings". Select the JN518x from the SDK MCUs list.
5. Go to C/C++ Build->"Tool Chain Editor" and untick the "Display compatible toolchains only" checkbox. In the drop-down menu named "Current toolchain", select "NXP MCU Tools". Click "Apply and Close".
6. Right click on the openthread project and select "Debug As"->"MCUXpresso IDE LinkServer (inc. CMSIS-DAP) probes"
7. A window to select the binary will appear. Select "output/jn5189/bin/ot-<application>" and click Ok. Ignore the error message.
7. A window to select the binary will appear. Select "output/jn5189/bin/ot-<application>" and click Ok.
8. Under the menu bar, towards the center of the screen, there is a green bug icon with a drop-down arrow next to it. Click on the arrow and select "Debug Configurations".
9. In the right side of the Debug Configurations window, go to "C/C++ (NXP Semiconductors) MCU Application"->"openthread LinkServer Default".
10. Make sure that in the "C/C++ Application:" text box contains "output\jn5189\bin\ot-<application>" path.
@@ -123,7 +123,3 @@ fe80:0:0:0:5c91:c61:b67c:271c
For a list of all available commands, visit [OpenThread CLI Reference README.md][cli].
[cli]: https://github.com/openthread/openthread/blob/master/src/cli/README.md
## Known limitations
While running the build process in "Ubuntu on Windows" bash, user can encounter build errors from unknown reasons. The current workaround is to re-run the "make -f examples/Makefile-jn5189" command. NCP applications have not been tested.
examples/platforms/jn5189/jn5189-mbedtls-config.h → examples/platforms/k32w/jn5189/jn5189-mbedtls-config.h
View File
examples/platforms/jn5189/jn5189.ld → examples/platforms/k32w/jn5189/jn5189.ld
+1
View File
@@ -80,6 +80,7 @@ INT_STORAGE_SIZE = INT_STORAGE_END - INT_STORAGE_S
FREESCALE_PROD_DATA_BASE_ADDR = m_fsl_prodInfo_start;
INT_STORAGE_SECTOR_SIZE = m_sector_size;
m_app_size = 0x48000;
ENTRY(ResetISR)
examples/platforms/jn5189/openthread-core-jn5189-config-check.h → examples/platforms/k32w/jn5189/openthread-core-jn5189-config-check.h
View File
examples/platforms/jn5189/openthread-core-jn5189-config.h → examples/platforms/k32w/jn5189/openthread-core-jn5189-config.h
+31 -11
View File
@@ -115,9 +115,6 @@
* Define to 1 if you want to use JN589 Flash implementation.
*
*/
#ifdef OPENTHREAD_SETTINGS_RAM
#undef OPENTHREAD_SETTINGS_RAM
#endif
#define OPENTHREAD_SETTINGS_RAM 1
/**
@@ -128,6 +125,16 @@
*/
#define OPENTHREAD_CONFIG_NCP_TX_BUFFER_SIZE 1024
/**
* @def OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE
*
* The size of heap buffer when DTLS is enabled.
*
*/
#ifndef OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE
#define OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE (2048 * sizeof(void *))
#endif
/**
* @def OPENTHREAD_CONFIG_COAP_API_ENABLE
*
@@ -136,14 +143,6 @@
*/
#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE
*
* Define to 1 to enable the CoAP Secure API.
*
*/
#define OPENTHREAD_CONFIG_COAP_SECURE_API_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_JOINER_ENABLE
*
@@ -191,4 +190,25 @@
*
*/
#define OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
*
* Define as 1 to enable the time synchronization service feature.
*
*/
#ifndef OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
#define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0
#endif
/**
* @def OPENTHREAD_CONFIG_DIAG_ENABLE
*
* Define as 1 to enable the diag feature.
*
*/
#ifndef OPENTHREAD_CONFIG_DIAG_ENABLE
#define OPENTHREAD_CONFIG_DIAG_ENABLE 0
#endif
#endif // OPENTHREAD_CORE_JN5189_CONFIG_H_
examples/platforms/k32w/k32w061/Makefile.am
Executable
+142
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@@ -0,0 +1,142 @@
#
# Copyright (c) 2019, The OpenThread Authors.
# Copyright (c) 2019, NXP.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of the copyright holder nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
include $(abs_top_nlbuild_autotools_dir)/automake/pre.am
lib_LIBRARIES = \
libopenthread-k32w061_plat.a \
libopenthread-k32w061_sdk.a
$(NULL)
# Do not enable -pedantic-errors for k32w061 driver library
override CFLAGS := $(filter-out -pedantic-errors,$(CFLAGS))
override CXXFLAGS := $(filter-out -pedantic-errors,$(CXXFLAGS))
# Do not enable -Wcast-align for k32w061 driver library
override CFLAGS := $(filter-out -Wcast-align,$(CFLAGS))
override CXXFLAGS := $(filter-out -Wcast-align,$(CXXFLAGS))
LIB_FLAGS = \
-DCPU_K32W061HN \
-DCPU_JN518X \
-DCPU_JN518X_REV=2 \
-DJENNIC_CHIP_FAMILY_JN518x \
-DJENNIC_CHIP_FAMILY_NAME=_JN518x \
-DUSE_RTOS=0 \
-DgPWR_LDOMEM_0_9V_PD=0 \
-DNO_SYSCORECLK_UPD=0 \
-I$(top_srcdir)/include \
-I$(top_srcdir)/examples/platforms \
-I$(top_srcdir)/src/core \
-I$(top_srcdir)/third_party/nxp \
-I$(top_srcdir)/third_party/nxp/K32W061DK6 \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/devices/K32W061 \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/components/serial_manager \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/components/uart \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/devices/K32W061/drivers \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/CMSIS/Include \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/uMac/Include \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/DK6/Build/Include \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/DK6 \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/ \
-I$(top_srcdir)/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement \
-Wno-unknown-pragmas \
-Wno-sign-compare \
-Wno-unused-function \
-Wno-unused-parameter \
-Wno-empty-body \
$(NULL)
libopenthread_k32w061_sdk_a_CPPFLAGS = \
$(LIB_FLAGS) \
$(NULL)
libopenthread_k32w061_plat_a_CPPFLAGS = \
$(LIB_FLAGS) \
$(NULL)
PLATFORM_SOURCES = \
src/alarm.c \
src/diag.c \
src/flash.c \
src/logging.c \
src/misc.c \
src/radio.c \
src/entropy.c \
src/system.c \
src/uart.c \
src/settings_k32w.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/utilities/fsl_assert.c \
@top_builddir@/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/aes_alt.c \
@top_builddir@/third_party/nxp/K32W061DK6/middleware/mbedtls/port/ksdk/ksdk_mbedtls.c \
$(NULL)
libopenthread_k32w061_sdk_a_SOURCES = \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/mcuxpresso/startup_k32w061.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/system_K32W061.c \
@top_builddir@/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/pin_mux.c \
@top_builddir@/third_party/nxp/K32W061DK6/boards/k32w061dk6/wireless_examples/openthread/enablement/clock_config.c \
@top_builddir@/third_party/nxp/K32W061DK6/components/serial_manager/serial_manager.c \
@top_builddir@/third_party/nxp/K32W061DK6/components/serial_manager/serial_port_uart.c \
@top_builddir@/third_party/nxp/K32W061DK6/components/uart/usart_adapter.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_gpio.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_clock.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_ctimer.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_wtimer.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flash.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_usart.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_rng.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_flexcomm.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_reset.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_power.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_aes.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/drivers/fsl_sha.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/utilities/debug_console/fsl_debug_console.c \
@top_builddir@/third_party/nxp/K32W061DK6/devices/K32W061/utilities/str/fsl_str.c \
@top_builddir@/third_party/nxp/K32W061DK6/middleware/wireless/framework/Common/MicroInt_arm_sdk2.c \
$(NULL)
libopenthread_k32w061_plat_a_SOURCES = \
$(PLATFORM_SOURCES) \
$(NULL)
PRETTY_FILES = \
$(PLATFORM_SOURCES) \
$(NULL)
Dash = -
libopenthread_k32w061_sdk_a_LIBADD = \
$(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
libopenthread_k32w061_plat_a_LIBADD = \
$(shell find $(top_builddir)/examples/platforms/utils $(Dash)type f $(Dash)name "*.o")
include $(abs_top_nlbuild_autotools_dir)/automake/post.am
examples/platforms/k32w/k32w061/Makefile.platform.am
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#
# Copyright (c) 2019, The OpenThread Authors.
# Copyright (c) 2019, NXP.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of the copyright holder nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
#
# K32W061 platform-specific Makefile
#
LDADD_COMMON += \
$(top_builddir)/examples/platforms/k32w/libopenthread-k32w061_plat.a \
$(top_builddir)/examples/platforms/k32w/libopenthread-k32w061_sdk.a \
$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/ieee-802.15.4/lib/libMiniMac.a \
$(top_srcdir)/third_party/nxp/K32W061DK6/middleware/wireless/framework/XCVR/lib/libRadio.a \
$(NULL)
LDFLAGS_COMMON += \
-T $(top_srcdir)/examples/platforms/k32w/k32w061/k32w061.ld \
$(NULL)
examples/platforms/k32w/k32w061/README.md
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# OpenThread on NXP K32W061 Example
This directory contains example platform drivers for the [NXP K32W061][k32w061] based on [K32W061-DK006][k32w061-dk006] hardware platform.
The example platform drivers are intended to present the minimal code necessary to support OpenThread. As a result, the example platform drivers do not necessarily highlight the platform's full capabilities.
## Toolchain
OpenThread environment is suited to be run on a Linux-based OS. Recommended OS is Ubuntu 18.04.2 LTS. Download and install the [MCUXpresso IDE][mcuxpresso ide].
[mcuxpresso ide]: https://www.nxp.com/support/developer-resources/software-development-tools/mcuxpresso-software-and-tools/mcuxpresso-integrated-development-environment-ide:MCUXpresso-IDE
In a Bash terminal (found, for example, in Ubuntu OS), follow these instructions to install the GNU toolchain and other dependencies.
```bash
$ cd <path-to-openthread>
$ ./script/bootstrap
```
If a network connection timeout is encountered, re-run the script.
Python-pip is also required for the build. User can install it by running "sudo apt-get install python-pip" in bash. After installing Python-pip, execute "pip install pycryptodome" in bash. This is needed for signing the built binary in order to load it on the board. Also, pycrypto "pip install pycrypto" is required for PKCS1.
Windows 10 offers the possibility of running bash by installing "Ubuntu on Windows" from Microsoft Store. This application allows the user to use Ubuntu Terminal and run Ubuntu command line utilities including bash, ssh, git, apt and many more. If this option is used, it is recommended to add instructions for the path mapping in MCUXpresso IDE. This can be done after adding the project to the workspace by going to Run->"Debug Configuration"->"C/C++(NXP Semiconductors) MCU Application"->Source->Add. Then the user should create a path mapping such that MCUXpresso IDE will find the mount point for the "Ubuntu in Windows" subsystem. For example, user can enter compilation path recognized by Ubuntu as /mnt/c/<path-to-openthread>, while equivalent "Local file system path" is C:/<path-to-openthread>. This example assumes that the openthread package is installed on the C drive.
## Build Examples
```bash
$ cd <path-to-openthread>
$ ./bootstrap
$ make -f examples/Makefile-k32w061
```
After a successful build, the `elf` files are found in `<path-to-openthread>/output/k32w061/bin`.
## Flash Binaries
Connect to the board by plugging a mini-USB cable to the connector marked with TARGET on the DK6 board. This connector is situated on the same side with the power connector.
OpenThread example application compiled binaries can be found in `<path-to-openthread>/output/k32w061/bin` and include FTD (Full Thread Device) and MTD (Minimal Thread Device) variants of CLI and NCP applications. The compiled binaries can be flashed onto the K32W061 using MCUXpresso IDE. This requires the following steps:
1. Import the K32W061 SDK into MCUXpresso IDE. This can be done by dragging and dropping the SDK archive into MCUXpresso IDE's Installed SDKs tab. The archive for SDK_2.6.0_K32W061DK6 is available for download at https://mcuxpresso.nxp.com/en/welcome
2. In MCUXpresso IDE, go to File->Import->C/C++->"Existing Code as Makefile Project" and click Next.
3. Select the OpenThread folder as the "Existing Code Location". In the "Toolchain for Indexer Settings" list, be sure to keep the setting to <none>. Click Finish.
4. Right click on the newly created openthread project in the Workspace and go to Properties->"C/C++ Build"->"MCU Settings". Select the JN518x from the SDK MCUs list.
5. Go to C/C++ Build->"Tool Chain Editor" and untick the "Display compatible toolchains only" checkbox. In the drop-down menu named "Current toolchain", select "NXP MCU Tools". Click "Apply and Close".
6. Right click on the openthread project and select "Debug As"->"MCUXpresso IDE LinkServer (inc. CMSIS-DAP) probes"
7. A window to select the binary will appear. Select "output/k32w061/bin/ot-<application>" and click Ok.
8. Under the menu bar, towards the center of the screen, there is a green bug icon with a drop-down arrow next to it. Click on the arrow and select "Debug Configurations".
9. In the right side of the Debug Configurations window, go to "C/C++ (NXP Semiconductors) MCU Application"->"openthread LinkServer Default".
10. Make sure that in the "C/C++ Application:" text box contains "output\k32w061\bin\ot-<application>" path.
11. Go to "GUI Flash Tool" tab. In "Target Operations"->Program->Options, select "bin" as the "Format to use for programming". Make sure the "Base address" is 0x0.
12. Click Debug.
13. A pop-up window entitled "Errors in Workspace" will appear. Click Proceed.
14. The board is now flashed.
[cmsis-dap]: https://os.mbed.com/handbook/CMSIS-DAP
## Running the example
1. Prepare two boards with the flashed `CLI Example` (as shown above). Make sure that the JN4 jumper is set to RX and the JN7 jumper is set to TX, connecting the LPC and JN UART0 pins.
2. The CLI example uses UART connection. To view raw UART output, start a terminal emulator like PuTTY and connect to the used COM port with the following UART settings:
- Baud rate: 115200
- 8 data bits
- 1 stop bit
- No parity
- No flow control
3. Open a terminal connection on the first board and start a new Thread network.
```bash
> panid 0xabcd
Done
> ifconfig up
Done
> thread start
Done
```
4. After a couple of seconds the node will become a Leader of the network.
```bash
> state
Leader
```
5. Open a terminal connection on the second board and attach a node to the network.
```bash
> panid 0xabcd
Done
> ifconfig up
Done
> thread start
Done
```
6. After a couple of seconds the second node will attach and become a Child.
```bash
> state
Child
```
7. List all IPv6 addresses of the first board.
```bash
> ipaddr
fdde:ad00:beef:0:0:ff:fe00:fc00
fdde:ad00:beef:0:0:ff:fe00:9c00
fdde:ad00:beef:0:4bcb:73a5:7c28:318e
fe80:0:0:0:5c91:c61:b67c:271c
```
8. Choose one of them and send an ICMPv6 ping from the second board.
```bash
> ping fdde:ad00:beef:0:0:ff:fe00:fc00
16 bytes from fdde:ad00:beef:0:0:ff:fe00:fc00: icmp_seq=1 hlim=64 time=8ms
```
For a list of all available commands, visit [OpenThread CLI Reference README.md][cli].
[cli]: https://github.com/openthread/openthread/blob/master/src/cli/README.md
examples/platforms/k32w/k32w061/k32w061-mbedtls-config.h
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/*
* Copyright (c) 2019, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef K32W061_MBEDTLS_CONFIG_H
#define K32W061_MBEDTLS_CONFIG_H
#if defined(MBEDTLS_ECP_WINDOW_SIZE)
#undef MBEDTLS_ECP_WINDOW_SIZE
#define MBEDTLS_ECP_WINDOW_SIZE 4 /**< Maximum window size used */
#endif
#if defined(MBEDTLS_ECP_FIXED_POINT_OPTIM)
#undef MBEDTLS_ECP_FIXED_POINT_OPTIM
#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */
#endif
/**
* \def MBEDTLS_AES_ALT
*
* Enable hardware acceleration for the AES block cipher
*
* See MBEDTLS_AES_C for more information.
*/
#define MBEDTLS_AES_ALT
#if defined(MBEDTLS_AES_ALT)
/**************************** KSDK ********************************************/
#include "fsl_device_registers.h"
/* Enable LTC use in library if there is LTC on chip. */
#if defined(FSL_FEATURE_SOC_LTC_COUNT) && (FSL_FEATURE_SOC_LTC_COUNT > 0)
#include "fsl_ltc.h"
#define LTC_INSTANCE LTC0 /* LTC base register.*/
#if FSL_FEATURE_LTC_HAS_SHA
#define MBEDTLS_FREESCALE_LTC_SHA1 /* Enable use of LTC SHA.*/
#define MBEDTLS_FREESCALE_LTC_SHA256 /* Enable use of LTC SHA256.*/
#endif
#if defined(FSL_FEATURE_LTC_HAS_DES) && FSL_FEATURE_LTC_HAS_DES
#define MBEDTLS_FREESCALE_LTC_DES /* Enable use of LTC DES.*/
#endif
#define MBEDTLS_FREESCALE_LTC_AES /* Enable use of LTC AES.*/
#if defined(FSL_FEATURE_LTC_HAS_GCM) && FSL_FEATURE_LTC_HAS_GCM
#define MBEDTLS_FREESCALE_LTC_AES_GCM /* Enable use of LTC AES GCM.*/
#endif
#if defined(FSL_FEATURE_LTC_HAS_PKHA) && FSL_FEATURE_LTC_HAS_PKHA
#define MBEDTLS_FREESCALE_LTC_PKHA /* Enable use of LTC PKHA.*/
#define FREESCALE_PKHA_INT_MAX_BYTES 256
#endif
#endif
/* Enable MMCAU use in library if there is MMCAU on chip. */
#if defined(FSL_FEATURE_SOC_MMCAU_COUNT) && (FSL_FEATURE_SOC_MMCAU_COUNT > 0)
#include "fsl_mmcau.h"
#define MBEDTLS_FREESCALE_MMCAU_MD5 /* Enable use of MMCAU MD5.*/
#define MBEDTLS_FREESCALE_MMCAU_SHA1 /* Enable use of MMCAU SHA1.*/
#define MBEDTLS_FREESCALE_MMCAU_SHA256 /* Enable use of MMCAU SHA256.*/
#define MBEDTLS_FREESCALE_MMCAU_DES /* Enable use of MMCAU DES, when LTC is disabled.*/
#define MBEDTLS_FREESCALE_MMCAU_AES /* Enable use of MMCAU AES, when LTC is disabled.*/
#endif
/* Enable CAU3 use in library if there is CAU3 on chip. */
#if defined(FSL_FEATURE_SOC_CAU3_COUNT) && (FSL_FEATURE_SOC_CAU3_COUNT > 0)
#include "cau3_pkha.h"
#include "fsl_cau3.h"
#define MBEDTLS_CAU3_COMPLETION_SIGNAL CAU3_CC_CMD_EVT
#define MBEDTLS_SHA256_ALT_NO_224
#define MBEDTLS_FREESCALE_CAU3_AES /* Enable use of CAU3 AES.*/
#define MBEDTLS_FREESCALE_CAU3_SHA256 /* Enable use of CAU3 SHA256.*/
#define MBEDTLS_FREESCALE_CAU3_PKHA /* Enable use of CAU3 PKHA.*/
#define FREESCALE_PKHA_INT_MAX_BYTES 512
#endif
#if defined(MBEDTLS_FREESCALE_LTC_PKHA) || defined(MBEDTLS_FREESCALE_CAU3_PKHA)
/*
* This FREESCALE_PKHA_LONG_OPERANDS_ENABLE macro can be defined.
* In such a case both software and hardware algorithm for TFM is linked in.
* The decision for which algorithm is used is determined at runtime
* from size of inputs. If inputs and result can fit into LTC (see FREESCALE_PKHA_INT_MAX_BYTES)
* then we call hardware algorithm, otherwise we call software algorithm.
*
* Note that mbedTLS algorithms break modular operations unefficiently into two steps.
* First is normal operation, for example non-modular multiply, which can produce number
* with greater size than operands. Second is modular reduction.
* The implication of this is that if for example FREESCALE_PKHA_INT_MAX_BYTES is 256 (2048 bits),
* RSA-2048 still requires the FREESCALE_PKHA_LONG_OPERANDS_ENABLE macro to be defined,
* otherwise it fails at runtime.
*/
//#define FREESCALE_PKHA_LONG_OPERANDS_ENABLE
#endif
/* Enable AES use in library if there is AES on chip. */
#if defined(FSL_FEATURE_SOC_AES_COUNT) && (FSL_FEATURE_SOC_AES_COUNT > 0)
#include "fsl_aes.h"
#define AES_INSTANCE AES0 /* AES base register.*/
#define MBEDTLS_FREESCALE_LPC_AES /* Enable use of LPC AES.*/
#define MBEDTLS_FREESCALE_LPC_AES_GCM /* Enable use of LPC AES GCM.*/
#endif
/* Enable SHA use in library if there is SHA on chip. */
#if defined(FSL_FEATURE_SOC_SHA_COUNT) && (FSL_FEATURE_SOC_SHA_COUNT > 0)
#include "fsl_sha.h"
//#define SHA_INSTANCE SHA0 /* AES base register.*/
#define MBEDTLS_FREESCALE_LPC_SHA1 /* Enable use of LPC SHA.*/
//#define MBEDTLS_FREESCALE_LPC_SHA256 /* Enable use of LPC SHA256.*/
#endif
/* Define ALT MMCAU & LTC functions. Do not change it. */
#if defined(MBEDTLS_FREESCALE_MMCAU_DES) || defined(MBEDTLS_FREESCALE_LTC_DES)
#define MBEDTLS_DES_SETKEY_ENC_ALT
#define MBEDTLS_DES_SETKEY_DEC_ALT
#define MBEDTLS_DES_CRYPT_ECB_ALT
#define MBEDTLS_DES3_CRYPT_ECB_ALT
#endif
#if defined(MBEDTLS_FREESCALE_LTC_DES)
#define MBEDTLS_DES_CRYPT_CBC_ALT
#define MBEDTLS_DES3_CRYPT_CBC_ALT
#endif
#if defined(MBEDTLS_FREESCALE_LTC_AES) || defined(MBEDTLS_FREESCALE_MMCAU_AES) || \
defined(MBEDTLS_FREESCALE_LPC_AES) || defined(MBEDTLS_FREESCALE_CAU3_AES)
#define MBEDTLS_AES_SETKEY_ENC_ALT
#define MBEDTLS_AES_SETKEY_DEC_ALT
#define MBEDTLS_AES_ENCRYPT_ALT
#define MBEDTLS_AES_DECRYPT_ALT
#endif
#if defined(MBEDTLS_FREESCALE_LTC_AES)
#define MBEDTLS_AES_CRYPT_CBC_ALT
#define MBEDTLS_AES_CRYPT_CTR_ALT
#define MBEDTLS_CCM_CRYPT_ALT
#endif
#if defined(MBEDTLS_FREESCALE_LTC_AES_GCM) || defined(MBEDTLS_FREESCALE_LPC_AES_GCM)
#define MBEDTLS_GCM_CRYPT_ALT
#endif
#if defined(MBEDTLS_FREESCALE_LTC_PKHA) || defined(MBEDTLS_FREESCALE_CAU3_PKHA)
#define MBEDTLS_MPI_ADD_ABS_ALT
#define MBEDTLS_MPI_SUB_ABS_ALT
#define MBEDTLS_MPI_MUL_MPI_ALT
#define MBEDTLS_MPI_MOD_MPI_ALT
#define MBEDTLS_MPI_EXP_MOD_ALT
#define MBEDTLS_MPI_GCD_ALT
#define MBEDTLS_MPI_INV_MOD_ALT
#define MBEDTLS_MPI_IS_PRIME_ALT
#if defined(MBEDTLS_FREESCALE_LTC_PKHA)
#define MBEDTLS_ECP_MUL_COMB_ALT
#define MBEDTLS_ECP_ADD_ALT
#endif
#endif
#if defined(MBEDTLS_FREESCALE_LTC_SHA1) || defined(MBEDTLS_FREESCALE_LPC_SHA1)
#define MBEDTLS_SHA1_ALT
#endif
#if defined(MBEDTLS_FREESCALE_LTC_SHA256) || defined(MBEDTLS_FREESCALE_LPC_SHA256)
//#define MBEDTLS_SHA256_ALT
/*
* LPC SHA module does not support SHA-224.
*
* Since mbed TLS does not provide separate APIs for SHA-224 and SHA-256
* and SHA-224 is not widely used, this implementation provides HW accelerated SHA-256 only
* and SHA-224 is not available at all (calls will fail).
*
* To use SHA-224 on LPC, do not define MBEDTLS_SHA256_ALT and both SHA-224 and SHA-256 will use
* original mbed TLS software implementation.
*/
#if defined(MBEDTLS_FREESCALE_LPC_SHA256)
#define MBEDTLS_SHA256_ALT_NO_224
#endif
#endif
#if defined(MBEDTLS_FREESCALE_MMCAU_MD5)
#define MBEDTLS_MD5_PROCESS_ALT
#endif
#if defined(MBEDTLS_FREESCALE_MMCAU_SHA1)
#define MBEDTLS_SHA1_PROCESS_ALT
#endif
#if defined(MBEDTLS_FREESCALE_MMCAU_SHA256)
#define MBEDTLS_SHA256_PROCESS_ALT
#endif
#if defined(MBEDTLS_FREESCALE_CAU3_SHA256)
#define MBEDTLS_SHA256_PROCESS_ALT
#endif
#if defined(MBEDTLS_FREESCALE_CAU3_AES)
#define MBEDTLS_AES_ALT_NO_192
#endif
#if defined(MBEDTLS_FREESCALE_LTC_AES)
#if !defined(FSL_FEATURE_LTC_HAS_AES192) || !FSL_FEATURE_LTC_HAS_AES192
#define MBEDTLS_AES_ALT_NO_192
#endif
#if !defined(FSL_FEATURE_LTC_HAS_AES256) || !FSL_FEATURE_LTC_HAS_AES256
#define MBEDTLS_AES_ALT_NO_256
#endif
#endif
#if defined(MBEDTLS_FREESCALE_LPC_AES)
#define MBEDTLS_AES_CRYPT_CBC_ALT
#define MBEDTLS_AES_CRYPT_CFB_ALT
#define MBEDTLS_AES_CRYPT_CTR_ALT
#endif
#if defined(MBEDTLS_FREESCALE_LPC_SHA1)
#define MBEDTLS_SHA1_PROCESS_ALT
#endif
#if defined(MBEDTLS_FREESCALE_LPC_SHA256)
#define MBEDTLS_SHA256_PROCESS_ALT
#endif
#if USE_RTOS && defined(FSL_RTOS_FREE_RTOS)
#include "FreeRTOS.h"
void *pvPortCalloc(size_t num, size_t size); /*Calloc for HEAP3.*/
#define MBEDTLS_PLATFORM_MEMORY
#define MBEDTLS_PLATFORM_STD_CALLOC pvPortCalloc
#define MBEDTLS_PLATFORM_STD_FREE vPortFree
#endif /* USE_RTOS*/
/**************************** KSDK end ****************************************/
#endif /* MBEDTLS_AES_ALT || MBEDTLS_SHA256_ALT */
#endif // K32W061_MBEDTLS_CONFIG_H
examples/platforms/k32w/k32w061/k32w061.ld
Executable
+304
View File
@@ -0,0 +1,304 @@
/*
* Copyright (c) 2019, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file
* GCC linker script for K32W061.
*/
/*
* stack size for the boot rom during warm boot and application
* 256 is sufficient (pwrm_test) but keep it large to 1024
*/
BOOT_RESUME_STACK_SIZE = 1024;
/* Set Stack size to 4K minus 32Bytes reserved for ROM code at end of BANK7 so
the stack fits in BANK7. In practice the active stack size at the time of
going to sleep is more important than the total available stack size */
STACK_SIZE = (4096 - 32);
MEM_RAM0_BASE = 0x4000400;
MEM_RAM0_SIZE = 0x0015c00;
MEMORY
{
/* Define each memory region. RAM0 definition leaves the first 1kB for the
boot code */
Flash640 (rx) : ORIGIN = 0, LENGTH = 0x00a0000 /* 640K bytes (alias Flash) */
RAM0 (rwx) : ORIGIN = 0x4000400, LENGTH = 0x0015c00 /* 87K bytes (alias RAM) */
RAM1 (rwx) : ORIGIN = 0x4020000, LENGTH = 0x10000 /* 64K bytes (alias RAM2) */
}
/* Define a symbol for the top of each memory region */
__top_RAM0 = MEM_RAM0_BASE + MEM_RAM0_SIZE; /* 87K bytes */
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x2F4;
/*** flash memory characteristics definitions required for OTA ***/
m_flash_start = 0x00000000;
m_flash_end = 0x0009FFFF;
m_flash_size = 0x000A0000;
m_sector_size = 512;
m_fsl_prodInfo_size = m_sector_size;
m_fsl_prodInfo_end = m_flash_size - 17 * m_sector_size - 1;
m_fsl_prodInfo_start = m_fsl_prodInfo_end - m_fsl_prodInfo_size + 1;
NV_STORAGE_MAX_SECTORS = 64;
NV_STORAGE_SIZE = NV_STORAGE_MAX_SECTORS * m_sector_size;
NV_STORAGE_END_ADDRESS = m_fsl_prodInfo_start - 1;
NV_STORAGE_START_ADDRESS = NV_STORAGE_END_ADDRESS - NV_STORAGE_SIZE + 1;
INT_STORAGE_END = NV_STORAGE_START_ADDRESS - 1;
INT_STORAGE_START = 0x48000;
INT_STORAGE_SIZE = INT_STORAGE_END - INT_STORAGE_START;
FREESCALE_PROD_DATA_BASE_ADDR = m_fsl_prodInfo_start;
INT_STORAGE_SECTOR_SIZE = m_sector_size;
m_app_size = 0x48000;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.header : ALIGN(4)
{
_flash_start = ABSOLUTE(.);
_flash_beg = ABSOLUTE(.);
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
FILL(0xff)
. = ALIGN (0x10);
} >Flash640
.ro_nonce : ALIGN(0x10)
{
_FlsNonceStart = ABSOLUTE(.);
*(.ro_nonce) /* nonce value is 16 bytes.*/
FILL(0xff)
. = ALIGN (0x10);
} > Flash640
.ro_ota_header : ALIGN(0x10)
{
_enc_start = ABSOLUTE(.);
_enc_offset = (_enc_start & 0x0000000F);
_FlsOtaHeader = ABSOLUTE(.);
*(.ro_ota_header) /* Ota Header 69 bytes*/
FILL(0xff)
. = ALIGN (0x10);
} > Flash640
.ro_se_lnkKey (ALIGN((. - _enc_offset), 16) + _enc_offset):
{
_FlsLinkKey = ABSOLUTE(.);
*(.ro_se_lnkKey) /* Link Key 16 bytes*/
FILL(0xff)
. = ALIGN (0x10);
} > Flash640
.filler :
{
BYTE(0xff)
FILL(0xff);
. = ALIGN(0x40);
} > Flash640
.text : ALIGN(0x40)
{
FILL(0xff)
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
} > Flash640
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
FILL(0xff)
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > Flash640
__exidx_start = .;
.ARM.exidx : ALIGN(4)
{
FILL(0xff)
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > Flash640
__exidx_end = .;
_etext = .;
/* RAM1/RAM2 (different names for same thing) SECTION */
/* RAM1 contents are specified before RAM0 as they have specific input
sections and we do not want the RAM0 wildcards to catch them */
/* DATA section for RAM1 */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM2 = .) ;
*(.ramfunc.$RAM2)
*(.ramfunc.$RAM1)
*(.data.$RAM2*)
*(.data.$RAM1*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM2 = .) ;
} > RAM1 AT>Flash640
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(4)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > RAM0
/* Main DATA section (RAM0) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
} > RAM0 AT>Flash640
/* BSS section for RAM1 */
.bss_RAM2 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_bss_RAM2 = .) ;
*(.bss.$RAM2*)
*(.bss.$RAM1*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
} > RAM1
/* MAIN BSS SECTION */
.bss (NOLOAD) : ALIGN(4)
{
_bss = .;
*(.bss*)
*(COMMON)
*(g_u32NwkFrameCounter)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
} > RAM0
/* BSS section for MAC buffers */
.bss_MAC (NOLOAD) : ALIGN(4)
{
/* MAC buffer section: must be within 128kB block. __mac_buffer_base is
defined further down to be on 128kB alignment */
__mac_buffer_start = .;
*(.mac_buffer)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
} > RAM0
/* HEAP */
.heap (NOLOAD): ALIGN(4)
{
_heap = .;
. += HEAP_SIZE;
. = ALIGN(4) ;
_end_heap = .;
} > RAM0
/* NOINIT section for RAM1 */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
*(.noinit.$RAM2*)
*(.noinit.$RAM1*)
. = ALIGN(4) ;
} > RAM1
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > RAM0
/* stack for rom boot during warm resume */
.boot_resume_stack (NOLOAD): ALIGN(4)
{
_boot_resume_stack = .;
*(.boot_resume_stack*)
. += BOOT_RESUME_STACK_SIZE;
. = ALIGN(4) ;
_end_boot_resume_stack = .;
} > RAM0
__nv_storage_end_address = NV_STORAGE_END_ADDRESS;
__nv_storage_start_address = NV_STORAGE_START_ADDRESS;
PROVIDE(_vStackTop = __top_RAM0 - 32);
PROVIDE(__mac_buffer_base = (__mac_buffer_start & 0xfffe0000));
PROVIDE(BOOT_GetStartPowerMode = 0x03000e9d);
PROVIDE(ROM_GetFlash = 0x03000e0d);
PROVIDE(pmc_reset_get_cause = 0x030046e9);
PROVIDE(psector_ReadIeee802_15_4_MacId1 = 0x030053b1);
PROVIDE(Chip_LOWPOWER_ChipSoftwareReset = 0x03003fa1);
__StackLimit = _vStackTop - STACK_SIZE;
ASSERT(__StackLimit >= _end_boot_resume_stack, "Possible stack corruption with data/bss/boot_stack")
}
examples/platforms/k32w/k32w061/openthread-core-k32w061-config-check.h
Executable
+42
View File
@@ -0,0 +1,42 @@
/*
* Copyright (c) 2019, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef OPENTHREAD_CORE_K32W061_CONFIG_CHECK_H_
#define OPENTHREAD_CORE_K32W061_CONFIG_CHECK_H_
#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
#error "Platform k32w061 doesn't support configuration option: OPENTHREAD_CONFIG_TIME_SYNC_ENABLE"
#endif
#ifndef RADIO_CONFIG_915MHZ_OQPSK_SUPPORT
#if OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT
#error "Platform k32w061 not configured to support configuration option: OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT"
#endif
#endif
#endif /* OPENTHREAD_CORE_K32W061_CONFIG_CHECK_H_ */
examples/platforms/k32w/k32w061/openthread-core-k32w061-config.h
Executable
+214
View File
@@ -0,0 +1,214 @@
/*
* Copyright (c) 2019, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file
* This file includes k32w061 compile-time configuration constants
* for OpenThread.
*/
#ifndef OPENTHREAD_CORE_K32W061_CONFIG_H_
#define OPENTHREAD_CORE_K32W061_CONFIG_H_
/**
* @def OPENTHREAD_CONFIG_LOG_OUTPUT
*
* The emsk platform provides an otPlatLog() function.
*/
#ifndef OPENTHREAD_CONFIG_LOG_OUTPUT /* allow command line override */
#define OPENTHREAD_CONFIG_LOG_OUTPUT OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED
#endif
/**
* @def OPENTHREAD_CONFIG_PLATFORM_INFO
*
* The platform-specific string to insert into the OpenThread version string.
*
*/
#define OPENTHREAD_CONFIG_PLATFORM_INFO "K32W061"
/**
* @def SETTINGS_CONFIG_BASE_ADDRESS
*
* The base address of settings.
*
*/
#define SETTINGS_CONFIG_BASE_ADDRESS 0
/**
* @def SETTINGS_CONFIG_PAGE_SIZE
*
* The page size of settings.
*
*/
#define SETTINGS_CONFIG_PAGE_SIZE 0x200
/**
* @def SETTINGS_CONFIG_PAGE_NUM
*
* The page number of settings.
*
*/
#define SETTINGS_CONFIG_PAGE_NUM 64
/**
* @def RADIO_CONFIG_SRC_MATCH_ENTRY_NUM
*
* The number of source address table entries.
*
*/
#define RADIO_CONFIG_SRC_MATCH_ENTRY_NUM 128
/**
* @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_RETRANSMIT
*
* Define to 1 if you want to enable software retransmission logic.
*
*/
/* TODO */
/**
* @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_CSMA_BACKOFF
*
* Define to 1 if you want to enable software CSMA-CA backoff logic.
*
*/
/* TODO */
/**
* @def OPENTHREAD_CONFIG_NCP_UART_ENABLE
*
* Define to 1 to enable NCP UART support.
*
*/
#define OPENTHREAD_CONFIG_NCP_UART_ENABLE 1
/**
* @def OPENTHREAD_SETTINGS_RAM
*
* Define to 1 if you want to use K32W061 Flash implementation.
*
*/
#define OPENTHREAD_SETTINGS_RAM 1
/**
* @def OPENTHREAD_CONFIG_NCP_TX_BUFFER_SIZE
*
* The size of NCP message buffer in bytes.
*
*/
#define OPENTHREAD_CONFIG_NCP_TX_BUFFER_SIZE 1024
/**
* @def OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE
*
* The size of heap buffer when DTLS is enabled.
*
*/
#ifndef OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE
#define OPENTHREAD_CONFIG_HEAP_INTERNAL_SIZE (2048 * sizeof(void *))
#endif
/**
* @def OPENTHREAD_CONFIG_COAP_API_ENABLE
*
* Define to 1 to enable the CoAP API.
*
*/
#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_JOINER_ENABLE
*
* Define to 1 to enable Joiner support.
*
*/
#define OPENTHREAD_CONFIG_JOINER_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_COMMISSIONER_ENABLE
*
* Define to 1 to enable Commissioner support.
*
*/
#define OPENTHREAD_CONFIG_COMMISSIONER_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE
*
* Define to 1 to enable UDP forward support.
*
*/
#define OPENTHREAD_CONFIG_UDP_FORWARD_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE
*
* Define to 1 to enable the Border Router service.
*
*/
#define OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE
*
* Define to 1 to enable the DHCP CLIENT service.
*
*/
#define OPENTHREAD_CONFIG_DHCP6_CLIENT_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE
*
* Define to 1 to enable the DHCP SERVER service.
*
*/
#define OPENTHREAD_CONFIG_DHCP6_SERVER_ENABLE 1
/**
* @def OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
*
* Define as 1 to enable the time synchronization service feature.
*
*/
#ifndef OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
#define OPENTHREAD_CONFIG_TIME_SYNC_ENABLE 0
#endif
/**
* @def OPENTHREAD_CONFIG_DIAG_ENABLE
*
* Define as 1 to enable the diag feature.
*
*/
#ifndef OPENTHREAD_CONFIG_DIAG_ENABLE
#define OPENTHREAD_CONFIG_DIAG_ENABLE 0
#endif
#endif // OPENTHREAD_CORE_K32W061_CONFIG_H_
examples/platforms/jn5189/alarm.c → examples/platforms/k32w/src/alarm.c
+7 -4
View File
@@ -32,6 +32,9 @@
*
*/
/* Openthread configuration */
#include OPENTHREAD_PROJECT_CORE_CONFIG_FILE
#include "fsl_clock.h"
#include "fsl_ctimer.h"
#include "fsl_device_registers.h"
@@ -63,7 +66,7 @@ static ctimer_match_config_t sMatchConfig = {.enableCounterReset = false,
static uint32_t sRemainingTicks;
#endif
void JN5189AlarmInit(void)
void K32WAlarmInit(void)
{
#if ALARM_USE_CTIMER
ctimer_config_t config;
@@ -99,7 +102,7 @@ void JN5189AlarmInit(void)
#endif
}
void JN5189AlarmClean(void)
void K32WAlarmClean(void)
{
#if ALARM_USE_CTIMER
CTIMER_StopTimer(CTIMER0);
@@ -118,11 +121,11 @@ void JN5189AlarmClean(void)
#endif
}
void JN5189AlarmProcess(otInstance *aInstance)
void K32WAlarmProcess(otInstance *aInstance)
{
if (sEventFired)
{
#if OPENTHREAD_ENABLE_DIAG
#if OPENTHREAD_CONFIG_DIAG_ENABLE
if (otPlatDiagModeGet())
{
examples/platforms/jn5189/diag.c → examples/platforms/k32w/src/diag.c
+7 -4
View File
@@ -32,12 +32,15 @@
*
*/
/* Openthread configuration */
#include OPENTHREAD_PROJECT_CORE_CONFIG_FILE
#include <stdio.h>
#include <openthread/config.h>
#include <openthread/platform/alarm-milli.h>
#include <openthread/platform/radio.h>
#if OPENTHREAD_ENABLE_DIAG
#if OPENTHREAD_CONFIG_DIAG_ENABLE
/**
* Diagnostics mode variables.
@@ -45,13 +48,13 @@
*/
static bool sDiagMode = false;
void otPlatDiagProcess(otInstance *aInstance, uint8_t aArgsLength, char *aArgs[], char *aOutput, size_t aOutputMaxLen)
void otPlatDiagProcess(otInstance *aInstance, int argc, char *argv[], char *aOutput, size_t aOutputMaxLen)
{
OT_UNUSED_VARIABLE(aInstance);
OT_UNUSED_VARIABLE(aArgsLength);
OT_UNUSED_VARIABLE(argc);
// Add more platform specific diagnostics features here.
snprintf(aOutput, aOutputMaxLen, "diag feature '%s' is not supported\r\n", aArgs[0]);
snprintf(aOutput, aOutputMaxLen, "diag feature '%s' is not supported\r\n", argv[0]);
}
void otPlatDiagModeSet(bool aMode)
examples/platforms/jn5189/entropy.c → examples/platforms/k32w/src/entropy.c
+1 -1
View File
@@ -39,7 +39,7 @@
#include <stdlib.h>
#include <utils/code_utils.h>
void JN5189RandomInit(void)
void K32WRandomInit(void)
{
trng_config_t config;
uint32_t seed;
examples/platforms/jn5189/flash.c → examples/platforms/k32w/src/flash.c
+22 -36
View File
@@ -26,11 +26,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "openthread/platform/flash.h"
#include "fsl_device_registers.h"
#include "fsl_flash.h"
#include "openthread-core-jn5189-config.h"
#include "openthread-core-config.h"
#include <utils/code_utils.h>
#include <utils/flash.h>
#include "openthread/platform/alarm-milli.h"
#define USE_MEM_COPY_FOR_READ 0
@@ -50,8 +50,10 @@ static bool mapToNvFlashAddress(uint32_t *aAddress);
static void copyFromFlash(uint8_t *pDst, uint8_t *pSrc, uint32_t cBytes);
static uint32_t blankCheckAndErase(uint8_t *pageAddr);
otError utilsFlashInit(void)
void otPlatFlashInit(otInstance *aInstance)
{
OT_UNUSED_VARIABLE(aInstance);
extern uint32_t __nv_storage_start_address;
extern uint32_t __nv_storage_end_address;
@@ -59,13 +61,6 @@ otError utilsFlashInit(void)
sNvFlashStartAddr = (uint32_t)&__nv_storage_start_address;
sNvFlashEndAddr = (uint32_t)&__nv_storage_end_address;
return OT_ERROR_NONE;
}
uint32_t utilsFlashGetSize(void)
{
return sNvFlashEndAddr - sNvFlashStartAddr;
}
otError utilsFlashErasePage(uint32_t aAddress)
@@ -91,31 +86,17 @@ exit:
return error;
}
otError utilsFlashStatusWait(uint32_t aTimeout)
{
otError error = OT_ERROR_BUSY;
uint32_t start = otPlatAlarmMilliGetNow();
do
{
if (FLASH->INT_STATUS & FLASH_DONE)
{
error = OT_ERROR_NONE;
break;
}
} while (aTimeout && ((otPlatAlarmMilliGetNow() - start) < aTimeout));
return error;
}
uint32_t utilsFlashWrite(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
void otPlatFlashWrite(otInstance *aInstance, uint8_t aSwapIndex, uint32_t aOffset, const void *aData, uint32_t aSize)
{
uint32_t result = 0;
status_t status;
uint32_t address = aAddress;
uint32_t address = aOffset;
uint32_t alignAddr;
uint32_t bytes;
OT_UNUSED_VARIABLE(aInstance);
OT_UNUSED_VARIABLE(aSwapIndex);
/* Map address to NV Flash space and check boundaries */
if (mapToNvFlashAddress(&address))
{
@@ -182,13 +163,21 @@ uint32_t utilsFlashWrite(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
}
exit:
return result;
/* There are times when the result != 0.
* Use this workaround until we replace the flash code with the Packet Data Manager.
*/
if (result)
{
result = 0;
}
}
uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
void otPlatFlashRead(otInstance *aInstance, uint8_t aSwapIndex, uint32_t aOffset, void *aData, uint32_t aSize)
{
uint32_t address = aAddress;
uint32_t result = 0;
uint32_t address = aOffset;
OT_UNUSED_VARIABLE(aInstance);
OT_UNUSED_VARIABLE(aSwapIndex);
/* Map address to NV Flash space and check boundaries */
if (mapToNvFlashAddress(&address))
@@ -197,11 +186,8 @@ uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
if ((address + aSize) <= sNvFlashEndAddr)
{
copyFromFlash(aData, (uint8_t *)address, aSize);
result = aSize;
}
}
return result;
}
static bool mapToNvFlashAddress(uint32_t *aAddress)
examples/platforms/jn5189/logging.c → examples/platforms/k32w/src/logging.c
+5 -5
View File
@@ -32,7 +32,7 @@
*
*/
#include "platform-jn5189.h"
#include "platform-k32w.h"
#include <openthread-core-config.h>
#include <utils/code_utils.h>
#include <openthread/config.h>
@@ -52,7 +52,7 @@
#define EOL_CHARS_LEN 2 /* Length of EOL */
/* static functions */
static void JN5189LogOutput(const char *aFormat, va_list ap);
static void K32WLogOutput(const char *aFormat, va_list ap);
/* static variables */
static char sTxBuffer[TX_BUFFER_SIZE + 1]; /* Transmit Buffer */
@@ -64,7 +64,7 @@ OT_TOOL_WEAK void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const
va_list ap;
va_start(ap, aFormat);
JN5189LogOutput(aFormat, ap);
K32WLogOutput(aFormat, ap);
va_end(ap);
}
@@ -75,7 +75,7 @@ OT_TOOL_WEAK void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const
* @param[in] ap Variable List Argument
*
*/
static void JN5189LogOutput(const char *aFormat, va_list ap)
static void K32WLogOutput(const char *aFormat, va_list ap)
{
int len = 0;
@@ -83,7 +83,7 @@ static void JN5189LogOutput(const char *aFormat, va_list ap)
otEXPECT(len >= 0);
memcpy(sTxBuffer + len, EOL_CHARS, EOL_CHARS_LEN);
len += EOL_CHARS_LEN;
JN5189WriteBlocking((const uint8_t *)sTxBuffer, len);
K32WWriteBlocking((const uint8_t *)sTxBuffer, len);
exit:
return;
examples/platforms/jn5189/misc.c → examples/platforms/k32w/src/misc.c
View File
examples/platforms/jn5189/platform-jn5189.h → examples/platforms/k32w/src/platform-k32w.h
+10 -10
View File
@@ -32,8 +32,8 @@
*
*/
#ifndef PLATFORM_KWJN5189_H_
#define PLATFORM_KWJN5189_H_
#ifndef PLATFORM_K32W_H_
#define PLATFORM_K32W_H_
#include <openthread-core-config.h>
#include <openthread/config.h>
@@ -46,7 +46,7 @@
* This function initializes the alarm service used by OpenThread.
*
*/
void JN5189AlarmInit(void);
void K32WAlarmInit(void);
/**
* This function performs alarm driver processing.
@@ -54,13 +54,13 @@ void JN5189AlarmInit(void);
* @param[in] aInstance The OpenThread instance structure.
*
*/
void JN5189AlarmProcess(otInstance *aInstance);
void K32WAlarmProcess(otInstance *aInstance);
/**
* This function initializes the radio service used by OpenThread.
*
*/
void JN5189RadioInit(void);
void K32WRadioInit(void);
/**
* This function performs radio driver processing.
@@ -68,19 +68,19 @@ void JN5189RadioInit(void);
* @param[in] aInstance The OpenThread instance structure.
*
*/
void JN5189RadioProcess(otInstance *aInstance);
void K32WRadioProcess(otInstance *aInstance);
/**
* This function initializes the random number service used by OpenThread.
*
*/
void JN5189RandomInit(void);
void K32WRandomInit(void);
/**
* This function performs UART driver processing.
*
*/
void JN5189UartProcess(void);
void K32WUartProcess(void);
/**
* This function performs UART Blocking Send
@@ -89,5 +89,5 @@ void JN5189UartProcess(void);
* @param[in] len Length of the above buffer
*
*/
void JN5189WriteBlocking(const uint8_t *aBuf, uint32_t len);
#endif // PLATFORM_JN5189_H_
void K32WWriteBlocking(const uint8_t *aBuf, uint32_t len);
#endif // PLATFORM_K32W_H_
examples/platforms/jn5189/radio.c → examples/platforms/k32w/src/radio.c
+109 -110
View File
@@ -33,16 +33,15 @@
*/
/* Openthread configuration */
#include "openthread-core-jn5189-config.h"
#include OPENTHREAD_PROJECT_CORE_CONFIG_FILE
/* memcpy */
#include "string.h"
/* uMac, MMAC, Radio */
#include "BbcAndPhyRegs.h"
#include "MMAC.h"
#include "MicroSpecific_arm_sdk2.h"
#include "radio_jn518x.h"
#include "radio.h"
/* Openthread general */
#include <utils/code_utils.h>
@@ -59,17 +58,17 @@ extern void BOARD_LedDongleToggle(void);
#define ALL_FFs_BYTE (0xFF)
#define JN5189_RADIO_MIN_TX_POWER_DBM (-30)
#define JN5189_RADIO_MAX_TX_POWER_DBM (15)
#define JN5189_RADIO_RX_SENSITIVITY_DBM (-100)
#define JN5189_RADIO_DEFAULT_CHANNEL (11)
#define K32W_RADIO_MIN_TX_POWER_DBM (-30)
#define K32W_RADIO_MAX_TX_POWER_DBM (15)
#define K32W_RADIO_RX_SENSITIVITY_DBM (-100)
#define K32W_RADIO_DEFAULT_CHANNEL (11)
#define US_PER_SYMBOL (16) /* Duration of a single symbol in [us] */
#define SYMBOLS_TO_US(symbols) ((symbols)*US_PER_SYMBOL)
#define US_TO_MILI_DIVIDER (1000)
#define MAX_FP_ADDRS (10) /* max number of frame pending children */
#define JN5189_RX_BUFFERS (8) /* max number of RX buffers */
#define MAX_FP_ADDRS (10) /* max number of frame pending children */
#define K32W_RX_BUFFERS (8) /* max number of RX buffers */
/* check IEEE Std. 802.15.4 - 2015: Table 8-81 - MAC sublayer constants */
#define MAC_TX_ATTEMPTS (4)
@@ -98,7 +97,7 @@ typedef struct
typedef struct
{
tsRxFrameFormat *buffer[JN5189_RX_BUFFERS];
tsRxFrameFormat *buffer[K32W_RX_BUFFERS];
uint8_t head;
uint8_t tail;
bool isFull;
@@ -155,23 +154,23 @@ typedef enum
} frameConversionType;
/* Private functions declaration */
static void JN5189ISR(uint32_t u32IntBitmap);
static void JN5189ProcessMacHeader(tsRxFrameFormat *aRxFrame);
static void JN5189ProcessRxFrames(otInstance *aInstance);
static void JN5189ProcessTxFrame(otInstance *aInstance);
static bool JN5189CheckIfFpRequired(tsRxFrameFormat *aRxFrame);
static bool_t JN5189IsDataReq(tsRxFrameFormat *aRxFrame);
static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
otRadioFrame * aOtFrame,
frameConversionType convType);
static void JN5189Copy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize, frameConversionType convType);
static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing);
static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFrame);
static tsRxFrameFormat *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing);
static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
static tsRxFrameFormat *JN5189GetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFrameIndex);
static void JN5189EnableReceive(bool_t isNewFrameNeeded);
static void JN5189RestartRx();
static void K32WISR(uint32_t u32IntBitmap);
static void K32WProcessMacHeader(tsRxFrameFormat *aRxFrame);
static void K32WProcessRxFrames(otInstance *aInstance);
static void K32WProcessTxFrame(otInstance *aInstance);
static bool K32WCheckIfFpRequired(tsRxFrameFormat *aRxFrame);
static bool_t K32WIsDataReq(tsRxFrameFormat *aRxFrame);
static otError K32WFrameConversion(tsRxFrameFormat * aMacFormatFrame,
otRadioFrame * aOtFrame,
frameConversionType convType);
static void K32WCopy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize, frameConversionType convType);
static void K32WResetRxRingBuffer(rxRingBuffer *aRxRing);
static void K32WPushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFrame);
static tsRxFrameFormat *K32WPopRxRingBuffer(rxRingBuffer *aRxRing);
static bool K32WIsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
static tsRxFrameFormat *K32WGetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFrameIndex);
static void K32WEnableReceive(bool_t isNewFrameNeeded);
static void K32WRestartRx(void);
/* Private variables declaration */
static otRadioState sState = OT_RADIO_STATE_DISABLED;
@@ -192,7 +191,7 @@ static fpNeighExtAddr sFpExtAddr[MAX_FP_ADDRS]; /* Frame Pending extended addres
static uint16_t sFpExtAddrMask; /* Mask - sFpExtAddr is valid */
static rxRingBuffer sRxRing; /* Receive Ring Buffer */
static tsRxFrameFormat sRxFrame[JN5189_RX_BUFFERS]; /* RX Buffers */
static tsRxFrameFormat sRxFrame[K32W_RX_BUFFERS]; /* RX Buffers */
static tsRxFrameFormat *sRxFrameInProcess; /* RX Frame currently in processing */
static bool_t sIsRxDisabled; /* TRUE if RX was disabled due to no RX bufs */
static uint8_t sRxFrameIndex; /* Index tracking the sRxFrame array */
@@ -247,10 +246,10 @@ void App_SetCustomEui64(uint8_t *aIeeeEui64)
memcpy((uint8_t *)&sCustomExtAddr, aIeeeEui64, sizeof(sCustomExtAddr));
}
void JN5189RadioInit(void)
void K32WRadioInit(void)
{
/* RX initialization */
memset(sRxFrame, 0, sizeof(tsRxFrameFormat) * JN5189_RX_BUFFERS);
memset(sRxFrame, 0, sizeof(tsRxFrameFormat) * K32W_RX_BUFFERS);
sRxFrameIndex = 0;
/* TX initialization */
@@ -258,10 +257,10 @@ void JN5189RadioInit(void)
sRxOtFrame.mPsdu = sRxData;
}
void JN5189RadioProcess(otInstance *aInstance)
void K32WRadioProcess(otInstance *aInstance)
{
JN5189ProcessRxFrames(aInstance);
JN5189ProcessTxFrame(aInstance);
K32WProcessRxFrames(aInstance);
K32WProcessTxFrame(aInstance);
}
otRadioState otPlatRadioGetState(otInstance *aInstance)
@@ -321,10 +320,10 @@ otError otPlatRadioEnable(otInstance *aInstance)
{
OT_UNUSED_VARIABLE(aInstance);
JN5189ResetRxRingBuffer(&sRxRing);
K32WResetRxRingBuffer(&sRxRing);
sRxFrameIndex = 0;
vMMAC_Enable();
vMMAC_EnableInterrupts(JN5189ISR);
vMMAC_EnableInterrupts(K32WISR);
vMMAC_ConfigureInterruptSources(E_MMAC_INT_TX_COMPLETE | E_MMAC_INT_RX_HEADER | E_MMAC_INT_RX_COMPLETE);
vMMAC_ConfigureRadio();
vMMAC_SetTxParameters(MAC_TX_ATTEMPTS, MAC_TX_CSMA_MIN_BE, MAC_TX_CSMA_MAX_BE, MAC_TX_CSMA_MAX_BACKOFFS);
@@ -353,7 +352,7 @@ otError otPlatRadioDisable(otInstance *aInstance)
otEXPECT(otPlatRadioIsEnabled(aInstance));
JN5189ResetRxRingBuffer(&sRxRing);
K32WResetRxRingBuffer(&sRxRing);
sRxFrameIndex = 0;
vMMAC_Disable();
sState = OT_RADIO_STATE_DISABLED;
@@ -425,7 +424,7 @@ otError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel)
* in the middle of a receive operation */
isNewFrameNeeded = FALSE;
}
JN5189EnableReceive(isNewFrameNeeded);
K32WEnableReceive(isNewFrameNeeded);
exit:
return error;
@@ -438,7 +437,7 @@ void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable)
sIsFpEnabled = aEnable;
}
otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, uint16_t aShortAddress)
otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
OT_UNUSED_VARIABLE(aInstance);
@@ -483,7 +482,7 @@ otError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const otExtAddress
return error;
}
otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, uint16_t aShortAddress)
otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
OT_UNUSED_VARIABLE(aInstance);
@@ -567,13 +566,13 @@ otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame)
eOptions |= E_MMAC_TX_USE_CCA;
}
JN5189FrameConversion(&sTxMacFrame, aFrame, otToMacFrame);
K32WFrameConversion(&sTxMacFrame, aFrame, otToMacFrame);
/* stop rx is handled by uMac tx function */
vMMAC_StartMacTransmit(&sTxMacFrame.sFrameBody, eOptions);
/* Set RX buffer pointer for ACK */
vREG_BbcWrite(REG_BBC_RXBUFAD, (uint32)&sRxAckFrame.sFrameBody);
vMMAC_SetRxFrame(&sRxAckFrame);
otPlatRadioTxStarted(aInstance, aFrame);
@@ -592,7 +591,7 @@ int8_t otPlatRadioGetRssi(otInstance *aInstance)
/* in RCP designs, the RSSI function is called while the radio is in
* OT_RADIO_STATE_RECEIVE. Turn off the radio before reading RSSI,
* otherwise we may end up waiting until a packet is received
* (in i16Radio_JN518x_GetRSSI, while loop)
* (in i16Radio_GetRSSI, while loop)
*/
if (sState == OT_RADIO_STATE_RECEIVE)
@@ -602,15 +601,15 @@ int8_t otPlatRadioGetRssi(otInstance *aInstance)
stateChanged = TRUE;
}
rssiValSigned = i16Radio_Jn518x_GetRSSI(0, FALSE, NULL);
rssiValSigned = i16Radio_GetRSSI(0, FALSE, NULL);
if (stateChanged)
{
sState = OT_RADIO_STATE_RECEIVE;
JN5189EnableReceive(TRUE);
K32WEnableReceive(TRUE);
}
rssiValSigned = i16Radio_Jn518x_BoundRssiValue(rssiValSigned);
rssiValSigned = i16Radio_BoundRssiValue(rssiValSigned);
/* RSSI reported by radio is in 1/4 dBm step,
* meaning values are 4 times larger than real dBm value.
@@ -681,13 +680,13 @@ otError otPlatRadioSetTransmitPower(otInstance *aInstance, int8_t aPower)
sState = OT_RADIO_STATE_SLEEP;
/* trim the values to the radio capabilities */
if (aPower < JN5189_RADIO_MIN_TX_POWER_DBM)
if (aPower < K32W_RADIO_MIN_TX_POWER_DBM)
{
aPower = JN5189_RADIO_MIN_TX_POWER_DBM;
aPower = K32W_RADIO_MIN_TX_POWER_DBM;
}
else if (aPower > JN5189_RADIO_MAX_TX_POWER_DBM)
else if (aPower > K32W_RADIO_MAX_TX_POWER_DBM)
{
aPower = JN5189_RADIO_MAX_TX_POWER_DBM;
aPower = K32W_RADIO_MAX_TX_POWER_DBM;
}
/* save for later use */
@@ -701,8 +700,8 @@ otError otPlatRadioSetTransmitPower(otInstance *aInstance, int8_t aPower)
}
else
{
/* if the channel has not yet been initialized use JN5189_RADIO_DEFAULT_CHANNEL as default */
vMMAC_SetChannelAndPower(JN5189_RADIO_DEFAULT_CHANNEL, aPower);
/* if the channel has not yet been initialized use K32W_RADIO_DEFAULT_CHANNEL as default */
vMMAC_SetChannelAndPower(K32W_RADIO_DEFAULT_CHANNEL, aPower);
}
sState = tempState;
@@ -729,7 +728,7 @@ int8_t otPlatRadioGetReceiveSensitivity(otInstance *aInstance)
{
OT_UNUSED_VARIABLE(aInstance);
return JN5189_RADIO_RX_SENSITIVITY_DBM;
return K32W_RADIO_RX_SENSITIVITY_DBM;
}
/**
@@ -738,7 +737,7 @@ int8_t otPlatRadioGetReceiveSensitivity(otInstance *aInstance)
* @param[in] u32IntBitmap Bitmap telling which interrupt fired
*
*/
static void JN5189ISR(uint32_t u32IntBitmap)
static void K32WISR(uint32_t u32IntBitmap)
{
tsRxFrameFormat *pRxFrame = NULL;
@@ -752,28 +751,28 @@ static void JN5189ISR(uint32_t u32IntBitmap)
if (u32IntBitmap & E_MMAC_INT_RX_HEADER)
{
/* go back one index from current frame index */
pRxFrame = &sRxFrame[(sRxFrameIndex + JN5189_RX_BUFFERS - 1) % JN5189_RX_BUFFERS];
pRxFrame = &sRxFrame[(sRxFrameIndex + K32W_RX_BUFFERS - 1) % K32W_RX_BUFFERS];
/* FP processing first */
JN5189ProcessMacHeader(pRxFrame);
K32WProcessMacHeader(pRxFrame);
/* RX interrupt fired so it's safe to consume the frame */
JN5189PushRxRingBuffer(&sRxRing, pRxFrame);
K32WPushRxRingBuffer(&sRxRing, pRxFrame);
if (0 == (pRxFrame->sFrameBody.u16FCF & kFcfAckRequest))
{
JN5189EnableReceive(TRUE);
K32WEnableReceive(TRUE);
}
}
else if (u32IntBitmap & E_MMAC_INT_RX_COMPLETE)
{
JN5189EnableReceive(TRUE);
K32WEnableReceive(TRUE);
}
}
else
{
/* restart RX and keep same buffer as data received contains errors */
JN5189EnableReceive(FALSE);
K32WEnableReceive(FALSE);
}
BOARD_LedDongleToggle();
@@ -785,21 +784,21 @@ static void JN5189ISR(uint32_t u32IntBitmap)
uint32_t txErrors = u32MMAC_GetTxErrors();
sTxDone = TRUE;
if (txErrors & REG_BBC_TXSTAT_CCAE_MASK)
if (txErrors & E_MMAC_TXSTAT_CCA_BUSY)
{
sTxStatus = OT_ERROR_CHANNEL_ACCESS_FAILURE;
}
else if (txErrors & REG_BBC_TXSTAT_ACKE_MASK)
else if (txErrors & E_MMAC_TXSTAT_NO_ACK)
{
sTxStatus = OT_ERROR_NO_ACK;
}
else if (txErrors & REG_BBC_TXSTAT_OOTE_MASK)
else if (txErrors & E_MMAC_TXSTAT_ABORTED)
{
sTxStatus = OT_ERROR_ABORT;
}
else if ((txErrors & REG_BBC_TXSTAT_TXPCTO_MASK) || (txErrors & REG_BBC_TXSTAT_TXTO_MASK))
else if ((txErrors & E_MMAC_TXSTAT_TXPCTO) || (txErrors & E_MMAC_TXSTAT_TXTO))
{
/* The JN518x has a TXTO timeout that we are using to catch and cope with the curious
/* The JN518x/K32W0x1 has a TXTO timeout that we are using to catch and cope with the curious
hang-up issue */
vMMAC_AbortRadio();
@@ -815,7 +814,7 @@ static void JN5189ISR(uint32_t u32IntBitmap)
BOARD_LedDongleToggle();
sState = OT_RADIO_STATE_RECEIVE;
JN5189EnableReceive(TRUE);
K32WEnableReceive(TRUE);
}
break;
@@ -831,7 +830,7 @@ static void JN5189ISR(uint32_t u32IntBitmap)
* @param[in] aRxFrame Pointer to the latest received MAC packet
*
*/
static void JN5189ProcessMacHeader(tsRxFrameFormat *aRxFrame)
static void K32WProcessMacHeader(tsRxFrameFormat *aRxFrame)
{
/* check if frame pending processing is required */
if (aRxFrame && sIsFpEnabled)
@@ -844,9 +843,9 @@ static void JN5189ProcessMacHeader(tsRxFrameFormat *aRxFrame)
aRxFrame->sFrameBody.u16SrcPAN = aRxFrame->sFrameBody.u16DestPAN;
}
if (JN5189IsDataReq(aRxFrame))
if (K32WIsDataReq(aRxFrame))
{
vREG_BbcWrite(REG_BBC_TXPEND, JN5189CheckIfFpRequired(aRxFrame));
vMMAC_SetTxPend(K32WCheckIfFpRequired(aRxFrame));
}
else
{
@@ -864,7 +863,7 @@ static void JN5189ProcessMacHeader(tsRxFrameFormat *aRxFrame)
* @return TRUE aRxFrame is a MAC Data Request Frame
* @return FALSE aRxFrame is not a MAC Data Request Frame
*/
static bool_t JN5189IsDataReq(tsRxFrameFormat *aRxFrame)
static bool_t K32WIsDataReq(tsRxFrameFormat *aRxFrame)
{
bool_t isDataReq = FALSE;
uint8_t offset = 0;
@@ -921,7 +920,7 @@ static bool_t JN5189IsDataReq(tsRxFrameFormat *aRxFrame)
* @return FALSE Frame Pending bit shouldn't be set in the reply
*
*/
static bool JN5189CheckIfFpRequired(tsRxFrameFormat *aRxFrame)
static bool K32WCheckIfFpRequired(tsRxFrameFormat *aRxFrame)
{
bool isFpRequired = FALSE;
uint16_t panId = aRxFrame->sFrameBody.u16SrcPAN;
@@ -966,14 +965,14 @@ static bool JN5189CheckIfFpRequired(tsRxFrameFormat *aRxFrame)
*
* @param[in] aInstance Pointer to OT instance
*/
static void JN5189ProcessRxFrames(otInstance *aInstance)
static void K32WProcessRxFrames(otInstance *aInstance)
{
tsRxFrameFormat *pRxMacFormatFrame = NULL;
uint32_t savedInterrupts;
while ((pRxMacFormatFrame = JN5189PopRxRingBuffer(&sRxRing)) != NULL)
while ((pRxMacFormatFrame = K32WPopRxRingBuffer(&sRxRing)) != NULL)
{
if (OT_ERROR_NONE == JN5189FrameConversion(pRxMacFormatFrame, &sRxOtFrame, macToOtFrame))
if (OT_ERROR_NONE == K32WFrameConversion(pRxMacFormatFrame, &sRxOtFrame, macToOtFrame))
{
otPlatRadioReceiveDone(aInstance, &sRxOtFrame, OT_ERROR_NONE);
}
@@ -987,7 +986,7 @@ static void JN5189ProcessRxFrames(otInstance *aInstance)
sRxFrameInProcess = NULL;
if (sIsRxDisabled)
{
JN5189EnableReceive(TRUE);
K32WEnableReceive(TRUE);
}
MICRO_RESTORE_INTERRUPTS(savedInterrupts);
}
@@ -998,14 +997,14 @@ static void JN5189ProcessRxFrames(otInstance *aInstance)
*
* @param[in] aInstance Pointer to OT instance
*/
static void JN5189ProcessTxFrame(otInstance *aInstance)
static void K32WProcessTxFrame(otInstance *aInstance)
{
if (sTxDone)
{
sTxDone = FALSE;
if ((sTxOtFrame.mPsdu[kMacFcfLowOffset] & kFcfAckRequest) && (OT_ERROR_NONE == sTxStatus))
{
JN5189FrameConversion(&sRxAckFrame, &sRxOtFrame, macToOtFrame);
K32WFrameConversion(&sRxAckFrame, &sRxOtFrame, macToOtFrame);
otPlatRadioTxDone(aInstance, &sTxOtFrame, &sRxOtFrame, sTxStatus);
}
else
@@ -1025,9 +1024,9 @@ static void JN5189ProcessTxFrame(otInstance *aInstance)
* @return OT_ERROR_NONE No conversion error
* @return OT_ERROR_PARSE Conversion failed due to parsing error
*/
static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
otRadioFrame * aOtFrame,
frameConversionType convType)
static otError K32WFrameConversion(tsRxFrameFormat * aMacFormatFrame,
otRadioFrame * aOtFrame,
frameConversionType convType)
{
tsMacFrame *pMacFrame = &aMacFormatFrame->sFrameBody;
uint8_t * pSavedStartRxPSDU = aOtFrame->mPsdu;
@@ -1036,13 +1035,13 @@ static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
otError error = OT_ERROR_NONE;
/* frame control field */
JN5189Copy((uint8_t *)&pMacFrame->u16FCF, &pPsdu, kFcfSize, convType);
K32WCopy((uint8_t *)&pMacFrame->u16FCF, &pPsdu, kFcfSize, convType);
aFcf = pMacFrame->u16FCF;
/* sequence number */
if (0 == (aFcf & kFcfSeqNbSuppresssion))
{
JN5189Copy(&pMacFrame->u8SequenceNum, &pPsdu, kDsnSize, convType);
K32WCopy(&pMacFrame->u8SequenceNum, &pPsdu, kDsnSize, convType);
}
/* destination Pan Id + address */
@@ -1052,14 +1051,14 @@ static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
break;
case kFcfDstAddrShort:
JN5189Copy((uint8_t *)&pMacFrame->u16DestPAN, &pPsdu, sizeof(otPanId), convType);
JN5189Copy((uint8_t *)&pMacFrame->uDestAddr.u16Short, &pPsdu, sizeof(otShortAddress), convType);
K32WCopy((uint8_t *)&pMacFrame->u16DestPAN, &pPsdu, sizeof(otPanId), convType);
K32WCopy((uint8_t *)&pMacFrame->uDestAddr.u16Short, &pPsdu, sizeof(otShortAddress), convType);
break;
case kFcfDstAddrExt:
JN5189Copy((uint8_t *)&pMacFrame->u16DestPAN, &pPsdu, sizeof(otPanId), convType);
JN5189Copy((uint8_t *)&pMacFrame->uDestAddr.sExt.u32L, &pPsdu, sizeof(uint32_t), convType);
JN5189Copy((uint8_t *)&pMacFrame->uDestAddr.sExt.u32H, &pPsdu, sizeof(uint32_t), convType);
K32WCopy((uint8_t *)&pMacFrame->u16DestPAN, &pPsdu, sizeof(otPanId), convType);
K32WCopy((uint8_t *)&pMacFrame->uDestAddr.sExt.u32L, &pPsdu, sizeof(uint32_t), convType);
K32WCopy((uint8_t *)&pMacFrame->uDestAddr.sExt.u32H, &pPsdu, sizeof(uint32_t), convType);
break;
default:
@@ -1070,7 +1069,7 @@ static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
/* Source Pan Id */
if ((aFcf & kFcfSrcAddrMask) != kFcfSrcAddrNone && (aFcf & kFcfPanidCompression) == 0)
{
JN5189Copy((uint8_t *)&pMacFrame->u16SrcPAN, &pPsdu, sizeof(otPanId), convType);
K32WCopy((uint8_t *)&pMacFrame->u16SrcPAN, &pPsdu, sizeof(otPanId), convType);
}
/* Source Address */
@@ -1080,12 +1079,12 @@ static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
break;
case kFcfSrcAddrShort:
JN5189Copy((uint8_t *)&pMacFrame->uSrcAddr.u16Short, &pPsdu, sizeof(otShortAddress), convType);
K32WCopy((uint8_t *)&pMacFrame->uSrcAddr.u16Short, &pPsdu, sizeof(otShortAddress), convType);
break;
case kFcfSrcAddrExt:
JN5189Copy((uint8_t *)&pMacFrame->uSrcAddr.sExt.u32L, &pPsdu, sizeof(uint32_t), convType);
JN5189Copy((uint8_t *)&pMacFrame->uSrcAddr.sExt.u32H, &pPsdu, sizeof(uint32_t), convType);
K32WCopy((uint8_t *)&pMacFrame->uSrcAddr.sExt.u32L, &pPsdu, sizeof(uint32_t), convType);
K32WCopy((uint8_t *)&pMacFrame->uSrcAddr.sExt.u32H, &pPsdu, sizeof(uint32_t), convType);
break;
default:
@@ -1101,7 +1100,7 @@ static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
{
aOtFrame->mInfo.mRxInfo.mAckedWithFramePending = (bool)aMacFormatFrame->sFrameBody.u16Unused;
aOtFrame->mInfo.mRxInfo.mLqi = aMacFormatFrame->u8LinkQuality;
aOtFrame->mInfo.mRxInfo.mRssi = i8Radio_Jn518x_GetLastPacketRSSI();
aOtFrame->mInfo.mRxInfo.mRssi = i8Radio_GetLastPacketRSSI();
aOtFrame->mChannel = sChannel;
#if OPENTHREAD_CONFIG_TIME_SYNC_ENABLE
#error Time sync requires the timestamp of SFD rather than that of rx done!
@@ -1114,7 +1113,7 @@ static otError JN5189FrameConversion(tsRxFrameFormat * aMacFormatFrame,
aOtFrame->mLength = pPsdu + (pMacFrame->u8PayloadLength) - pSavedStartRxPSDU + sizeof(pMacFrame->u16FCS);
}
JN5189Copy((uint8_t *)&pMacFrame->uPayload, &pPsdu, pMacFrame->u8PayloadLength, convType);
K32WCopy((uint8_t *)&pMacFrame->uPayload, &pPsdu, pMacFrame->u8PayloadLength, convType);
exit:
return error;
@@ -1132,7 +1131,7 @@ exit:
* @return OT_ERROR_NONE No conversion error
* @return OT_ERROR_PARSE Conversion failed due to parsing error
*/
static void JN5189Copy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize, frameConversionType convType)
static void K32WCopy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize, frameConversionType convType)
{
if (convType == macToOtFrame)
{
@@ -1151,7 +1150,7 @@ static void JN5189Copy(uint8_t *aFieldValue, uint8_t **aPsdu, uint8_t copySize,
*
* @param[in] aRxRing Pointer to an RX Ring Buffer
*/
static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing)
static void K32WResetRxRingBuffer(rxRingBuffer *aRxRing)
{
aRxRing->head = 0;
aRxRing->tail = 0;
@@ -1165,15 +1164,15 @@ static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing)
* @param[in] aRxRing Pointer to the RX Ring Buffer
* @param[in] rxFrame The address for a received frame
*/
static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFrame)
static void K32WPushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFrame)
{
aRxRing->buffer[aRxRing->head] = aRxFrame;
if (aRxRing->isFull)
{
aRxRing->tail = (aRxRing->tail + 1) % JN5189_RX_BUFFERS;
aRxRing->tail = (aRxRing->tail + 1) % K32W_RX_BUFFERS;
}
aRxRing->head = (aRxRing->head + 1) % JN5189_RX_BUFFERS;
aRxRing->head = (aRxRing->head + 1) % K32W_RX_BUFFERS;
aRxRing->isFull = (aRxRing->head == aRxRing->tail);
}
@@ -1188,17 +1187,17 @@ static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, tsRxFrameFormat *aRxFr
* @return tsRxFrameFormat Pointer to a received frame
* @return NULL In case the RX Ring buffer is empty
*/
static tsRxFrameFormat *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing)
static tsRxFrameFormat *K32WPopRxRingBuffer(rxRingBuffer *aRxRing)
{
tsRxFrameFormat *rxFrame = NULL;
uint32_t savedInterrupts;
MICRO_DISABLE_AND_SAVE_INTERRUPTS(savedInterrupts);
if (!JN5189IsEmptyRxRingBuffer(aRxRing))
if (!K32WIsEmptyRxRingBuffer(aRxRing))
{
rxFrame = aRxRing->buffer[aRxRing->tail];
aRxRing->isFull = FALSE;
aRxRing->tail = (aRxRing->tail + 1) % JN5189_RX_BUFFERS;
aRxRing->tail = (aRxRing->tail + 1) % K32W_RX_BUFFERS;
}
MICRO_RESTORE_INTERRUPTS(savedInterrupts);
@@ -1213,7 +1212,7 @@ static tsRxFrameFormat *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing)
* @return TRUE RX Ring Buffer is not empty
* @return FALSE RX Ring Buffer is empty
*/
static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
static bool K32WIsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
{
return (!aRxRing->isFull && (aRxRing->head == aRxRing->tail));
}
@@ -1230,14 +1229,14 @@ static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
*
* @return tsRxFrameFormat Pointer to a tsRxFrameFormat
*/
static tsRxFrameFormat *JN5189GetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFrameIndex)
static tsRxFrameFormat *K32WGetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFrameIndex)
{
tsRxFrameFormat *frame = NULL;
frame = &aRxFrame[*aRxFrameIndex];
if (frame != sRxFrameInProcess)
{
*aRxFrameIndex = (*aRxFrameIndex + 1) % JN5189_RX_BUFFERS;
*aRxFrameIndex = (*aRxFrameIndex + 1) % K32W_RX_BUFFERS;
}
else
{
@@ -1262,21 +1261,21 @@ static tsRxFrameFormat *JN5189GetFrame(tsRxFrameFormat *aRxFrame, uint8_t *aRxFr
* used for a new RX operation.
*
*/
static void JN5189EnableReceive(bool_t isNewFrameNeeded)
static void K32WEnableReceive(bool_t isNewFrameNeeded)
{
tsRxFrameFormat *pRxFrame = NULL;
if (isNewFrameNeeded)
{
if ((pRxFrame = JN5189GetFrame(sRxFrame, &sRxFrameIndex)) != NULL)
if ((pRxFrame = K32WGetFrame(sRxFrame, &sRxFrameIndex)) != NULL)
{
vREG_BbcWrite(REG_BBC_RXBUFAD, (uint32)(&pRxFrame->sFrameBody));
JN5189RestartRx();
vMMAC_SetRxFrame(pRxFrame);
K32WRestartRx();
}
}
else
{
JN5189RestartRx();
K32WRestartRx();
}
}
@@ -1284,8 +1283,8 @@ static void JN5189EnableReceive(bool_t isNewFrameNeeded)
* Function used for MMAC-RX Restart
*
*/
static void JN5189RestartRx()
static void K32WRestartRx(void)
{
vREG_BbcWrite(REG_BBC_RXPROM, ((uint32)sRxOpt >> 8) & ALL_FFs_BYTE);
vMMAC_SetRxProm(((uint32)sRxOpt >> 8) & ALL_FFs_BYTE);
vMMAC_RxCtlUpdate(((uint32)sRxOpt) & ALL_FFs_BYTE);
}
examples/platforms/jn5189/random.c → examples/platforms/k32w/src/random.c
View File
examples/platforms/jn5189/settings_jn5189.c → examples/platforms/k32w/src/settings_k32w.c
+21 -19
View File
@@ -29,8 +29,8 @@
/**
* @file
* This file implements the OpenThread platform abstraction for non-volatile storage of
* settings on JN5189 platform. It has been modified and optimized from the original
* Open Thread settings implementation to work with JN5189's flash particularities.
* settings on K32W platform. It has been modified and optimized from the original
* Open Thread settings implementation to work with K32W's flash particularities.
*
*/
@@ -46,7 +46,7 @@
#include "utils/code_utils.h"
#include "utils/wrap_string.h"
#include "utils/flash.h"
#include "openthread/platform/flash.h"
#define OT_FLASH_BLOCK_ADD_BEGIN_FLAG (1 << 0)
#define OT_FLASH_BLOCK_ADD_COMPLETE_FLAG (1 << 1)
@@ -60,7 +60,7 @@
#define OT_SETTINGS_FLAG_SIZE 16
#define OT_SETTINGS_BLOCK_DATA_SIZE 256
/* JN5189 erases the flash to value 0x00 */
/* K32W erases the flash to value 0x00 */
#define FLASH_ERASE_VALUE 0x00
#define FLASH_ALIGN_SIZE 16
#define FLASH_BLOCK_PAD1_SIZE 10
@@ -68,6 +68,8 @@
#define OT_SETTINGS_IN_USE 0xbe5cc5ee
extern otError utilsFlashErasePage(uint32_t aAddress);
/* Added padding to make settings block structure align to minimum flash write size of 16 bytes.
* The delFlag field has an offset of 16 bytes from the beginning of the structure to allow a new
* write on the field. */
@@ -179,7 +181,7 @@ static uint16_t getAlignLength(uint16_t currentPos, uint8_t blockFlag, uint16_t
static void setSettingsFlag(uint32_t aBase, uint32_t aFlag)
{
utilsFlashWrite(aBase, (uint8_t *)&aFlag, sizeof(aFlag));
otPlatFlashWrite(0, 0, aBase, (uint8_t *)&aFlag, sizeof(aFlag));
}
static void eraseSettings(uint32_t aBase)
@@ -235,7 +237,7 @@ static uint32_t swapSettingsBlock(otInstance *aInstance)
} OT_TOOL_PACKED_END addBlock;
bool valid = true;
utilsFlashRead(swapAddress, (uint8_t *)(&addBlock.block), sizeof(struct settingsBlock));
otPlatFlashRead(aInstance, 0, swapAddress, (uint8_t *)(&addBlock.block), sizeof(struct settingsBlock));
swapAddress += sizeof(struct settingsBlock);
tempFlag = addBlock.block.flag;
@@ -250,7 +252,7 @@ static uint32_t swapSettingsBlock(otInstance *aInstance)
{
struct settingsBlock block;
utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
otPlatFlashRead(aInstance, 0, address, (uint8_t *)(&block), sizeof(block));
if ((FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG)) &&
(0 == FLASH_BLOCK_FLAG_IS_SET(block.delFlag, OT_FLASH_BLOCK_DELETE_FLAG)) &&
@@ -281,7 +283,7 @@ static uint32_t swapSettingsBlock(otInstance *aInstance)
/* current pos parameter doesn't count in this case */
writeSize += getAlignLength(0, OT_FLASH_BLOCK_COMPACT_FLAG, addBlock.block.length);
utilsFlashRead(swapAddress, addBlock.data, addBlock.block.length);
otPlatFlashRead(aInstance, 0, swapAddress, addBlock.data, addBlock.block.length);
/* contents fits in current page - we can copy it to page buffer until there is
* enough data to program a page */
if ((sSettingsUsedSize % SETTINGS_CONFIG_PAGE_SIZE) + writeSize <= SETTINGS_CONFIG_PAGE_SIZE)
@@ -302,7 +304,7 @@ static uint32_t swapSettingsBlock(otInstance *aInstance)
/* calculate page address that we are going to write */
uint32_t alignAddress = sSettingsBaseAddress + sSettingsUsedSize;
alignAddress = alignAddress - (alignAddress % SETTINGS_CONFIG_PAGE_SIZE);
utilsFlashWrite(alignAddress, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
otPlatFlashWrite(aInstance, 0, alignAddress, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
/* After the page buffer is erased copy what dind't fit the previous page */
memset(pageBuffer, FLASH_ERASE_VALUE, SETTINGS_CONFIG_PAGE_SIZE);
@@ -324,7 +326,7 @@ static uint32_t swapSettingsBlock(otInstance *aInstance)
/* If the page buffer has been used and it's not full write to flash at the end */
uint32_t alignAddr = sSettingsBaseAddress + sSettingsUsedSize;
alignAddr = alignAddr - (alignAddr % SETTINGS_CONFIG_PAGE_SIZE);
utilsFlashWrite(alignAddr, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
otPlatFlashWrite(aInstance, 0, alignAddr, pageBuffer, SETTINGS_CONFIG_PAGE_SIZE);
}
/* Clear the old settings zone */
eraseSettings(oldBase);
@@ -375,8 +377,8 @@ static otError addSetting(otInstance * aInstance,
memcpy(addBlock.data, aValue, addBlock.block.length);
SET_FLASH_BLOCK_FLAG(addBlock.block.flag, OT_FLASH_BLOCK_ADD_COMPLETE_FLAG);
utilsFlashWrite(sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&addBlock.block),
sizeof(struct settingsBlock) + addBlock.block.length);
otPlatFlashWrite(aInstance, 0, sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&addBlock.block),
sizeof(struct settingsBlock) + addBlock.block.length);
/* The next settings block will be written to the next flash page to optimize the number of
* writes made to a page */
sSettingsUsedSize +=
@@ -400,14 +402,14 @@ void otPlatSettingsInit(otInstance *aInstance)
sSettingsBaseAddress = SETTINGS_CONFIG_BASE_ADDRESS;
utilsFlashInit();
otPlatFlashInit(aInstance);
for (index = 0; index < 2; index++)
{
uint32_t blockFlag;
sSettingsBaseAddress += settingsSize * index;
utilsFlashRead(sSettingsBaseAddress, (uint8_t *)(&blockFlag), sizeof(blockFlag));
otPlatFlashRead(aInstance, 0, sSettingsBaseAddress, (uint8_t *)(&blockFlag), sizeof(blockFlag));
if (blockFlag == OT_SETTINGS_IN_USE)
{
@@ -424,7 +426,7 @@ void otPlatSettingsInit(otInstance *aInstance)
while (sSettingsUsedSize < settingsSize)
{
utilsFlashRead(sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&block), sizeof(block));
otPlatFlashRead(aInstance, 0, sSettingsBaseAddress + sSettingsUsedSize, (uint8_t *)(&block), sizeof(block));
if (FLASH_BLOCK_FLAG_IS_SET(block.flag, OT_FLASH_BLOCK_ADD_BEGIN_FLAG))
{
@@ -477,7 +479,7 @@ otError otPlatSettingsGet(otInstance *aInstance, uint16_t aKey, int aIndex, uint
{
struct settingsBlock block;
utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
otPlatFlashRead(aInstance, 0, address, (uint8_t *)(&block), sizeof(block));
if (block.key == aKey)
{
@@ -502,7 +504,7 @@ otError otPlatSettingsGet(otInstance *aInstance, uint16_t aKey, int aIndex, uint
readLength = *aValueLength;
}
utilsFlashRead(address + sizeof(struct settingsBlock), aValue, readLength);
otPlatFlashRead(aInstance, 0, address + sizeof(struct settingsBlock), aValue, readLength);
}
valueLength = block.length;
@@ -550,7 +552,7 @@ otError otPlatSettingsDelete(otInstance *aInstance, uint16_t aKey, int aIndex)
{
struct settingsBlock block;
utilsFlashRead(address, (uint8_t *)(&block), sizeof(block));
otPlatFlashRead(aInstance, 0, address, (uint8_t *)(&block), sizeof(block));
if (block.key == aKey)
{
@@ -579,7 +581,7 @@ otError otPlatSettingsDelete(otInstance *aInstance, uint16_t aKey, int aIndex)
if (flashWrite)
{
utilsFlashWrite(address, (uint8_t *)(&block), sizeof(block));
otPlatFlashWrite(aInstance, 0, address, (uint8_t *)(&block), sizeof(block));
}
index++;
examples/platforms/jn5189/system.c → examples/platforms/k32w/src/system.c
+7 -7
View File
@@ -33,7 +33,7 @@
*/
#include "board.h"
#include "pin_mux.h"
#include "platform-jn5189.h"
#include "platform-k32w.h"
#include "openthread/platform/uart.h"
#include <stdbool.h>
@@ -59,9 +59,9 @@ void otSysInit(int argc, char *argv[])
BOARD_InitPins();
}
JN5189AlarmInit();
JN5189RandomInit();
JN5189RadioInit();
K32WAlarmInit();
K32WRandomInit();
K32WRadioInit();
}
bool otSysPseudoResetWasRequested(void)
@@ -77,9 +77,9 @@ void otSysDeinit(void)
void otSysProcessDrivers(otInstance *aInstance)
{
JN5189RadioProcess(aInstance);
JN5189UartProcess();
JN5189AlarmProcess(aInstance);
K32WRadioProcess(aInstance);
K32WUartProcess();
K32WAlarmProcess(aInstance);
}
void otSysEventSignalPending(void)
examples/platforms/jn5189/uart.c → examples/platforms/k32w/src/uart.c
+43 -29
View File
@@ -43,13 +43,13 @@
#include "openthread/platform/uart.h"
/* Defines */
#define JN5189_UART_RX_BUFFERS 256
#define JN5189_UART_BAUD_RATE 115200
#define K32W_UART_RX_BUFFERS 256
#define K32W_UART_BAUD_RATE 115200
/* Structures */
typedef struct
{
uint8_t buffer[JN5189_UART_RX_BUFFERS];
uint8_t buffer[K32W_UART_RX_BUFFERS];
uint8_t head;
uint8_t tail;
bool isFull;
@@ -60,15 +60,15 @@ typedef enum
{
UART_IDLE, /* TX idle. */
UART_BUSY, /* TX busy. */
} jn5189UartStates;
} K32WUartStates;
/* Private functions declaration */
static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing);
static uint8_t *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing);
static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter);
static void JN5189ProcessReceive();
static void JN5189ProcessTransmit();
static void K32WResetRxRingBuffer(rxRingBuffer *aRxRing);
static uint8_t *K32WPopRxRingBuffer(rxRingBuffer *aRxRing);
static bool K32WIsEmptyRxRingBuffer(rxRingBuffer *aRxRing);
static void K32WPushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter);
static void K32WProcessReceive(void);
static void K32WProcessTransmit(void);
static void USART0_IRQHandler(USART_Type *base, usart_handle_t *handle);
/* Private variables declaration */
@@ -77,12 +77,12 @@ static bool sIsTransmitDone; /* Transmit done for the latest user-d
static usart_handle_t sUartHandle; /* Handle to the UART module */
static rxRingBuffer sUartRxRing; /* Receive Ring Buffer */
void JN5189UartProcess(void)
void K32WUartProcess(void)
{
if (sIsUartInitialized)
{
JN5189ProcessTransmit();
JN5189ProcessReceive();
K32WProcessTransmit();
K32WProcessReceive();
}
}
@@ -104,7 +104,7 @@ otError otPlatUartEnable(void)
sUartHandle.txState = UART_IDLE;
USART_GetDefaultConfig(&config);
config.baudRate_Bps = JN5189_UART_BAUD_RATE;
config.baudRate_Bps = K32W_UART_BAUD_RATE;
config.enableTx = true;
config.enableRx = true;
config.rxWatermark = kUSART_RxFifo1;
@@ -112,7 +112,7 @@ otError otPlatUartEnable(void)
uartStatus = USART_Init(USART0, &config, kPlatformClock);
otEXPECT_ACTION(uartStatus == kStatus_Success, error = OT_ERROR_INVALID_ARGS);
JN5189ResetRxRingBuffer(&sUartRxRing);
K32WResetRxRingBuffer(&sUartRxRing);
FLEXCOMM_SetIRQHandler(USART0, (flexcomm_irq_handler_t)USART0_IRQHandler, &sUartHandle);
@@ -163,7 +163,7 @@ otError otPlatUartFlush(void)
* @param[in] aBuf Pointer to the character buffer
* @param[in] len Length of the character buffer
*/
void JN5189WriteBlocking(const uint8_t *aBuf, uint32_t len)
void K32WWriteBlocking(const uint8_t *aBuf, uint32_t len)
{
otEXPECT(sIsUartInitialized && sUartHandle.txState != UART_BUSY);
@@ -178,7 +178,7 @@ exit:
/**
* Process TX characters in process context and call the upper layer call-backs.
*/
static void JN5189ProcessTransmit(void)
static void K32WProcessTransmit(void)
{
if (sIsTransmitDone)
{
@@ -190,13 +190,13 @@ static void JN5189ProcessTransmit(void)
/**
* Process RX characters in process context and call the upper layer call-backs.
*/
static void JN5189ProcessReceive(void)
static void K32WProcessReceive(void)
{
uint8_t rx[JN5189_UART_RX_BUFFERS];
uint8_t rx[K32W_UART_RX_BUFFERS];
uint16_t rxIndex = 0;
uint8_t *pCharacter;
while ((pCharacter = JN5189PopRxRingBuffer(&sUartRxRing)) != NULL)
while ((pCharacter = K32WPopRxRingBuffer(&sUartRxRing)) != NULL)
{
rx[rxIndex] = *pCharacter;
rxIndex++;
@@ -229,7 +229,7 @@ static void USART0_IRQHandler(USART_Type *base, usart_handle_t *handle)
volatile uint8_t rx_data = USART_ReadByte(USART0);
{
JN5189PushRxRingBuffer(&sUartRxRing, rx_data);
K32WPushRxRingBuffer(&sUartRxRing, rx_data);
}
}
@@ -267,16 +267,16 @@ static void USART0_IRQHandler(USART_Type *base, usart_handle_t *handle)
* @param[in] aRxRing Pointer to the RX Ring Buffer
* @param[in] aCharacter The received character
*/
static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter)
static void K32WPushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter)
{
aRxRing->buffer[aRxRing->head] = aCharacter;
if (aRxRing->isFull)
{
aRxRing->tail = (aRxRing->tail + 1) % JN5189_UART_RX_BUFFERS;
aRxRing->tail = (aRxRing->tail + 1) % K32W_UART_RX_BUFFERS;
}
aRxRing->head = (aRxRing->head + 1) % JN5189_UART_RX_BUFFERS;
aRxRing->head = (aRxRing->head + 1) % K32W_UART_RX_BUFFERS;
aRxRing->isFull = (aRxRing->head == aRxRing->tail);
}
@@ -291,16 +291,16 @@ static void JN5189PushRxRingBuffer(rxRingBuffer *aRxRing, uint8_t aCharacter)
* @return tsRxFrameFormat Pointer to a received character
* @return NULL In case the RX Ring buffer is empty
*/
static uint8_t *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing)
static uint8_t *K32WPopRxRingBuffer(rxRingBuffer *aRxRing)
{
uint8_t *pCharacter = NULL;
DisableIRQ(USART0_IRQn);
if (!JN5189IsEmptyRxRingBuffer(aRxRing))
if (!K32WIsEmptyRxRingBuffer(aRxRing))
{
pCharacter = &(aRxRing->buffer[aRxRing->tail]);
aRxRing->isFull = false;
aRxRing->tail = (aRxRing->tail + 1) % JN5189_UART_RX_BUFFERS;
aRxRing->tail = (aRxRing->tail + 1) % K32W_UART_RX_BUFFERS;
}
EnableIRQ(USART0_IRQn);
@@ -315,7 +315,7 @@ static uint8_t *JN5189PopRxRingBuffer(rxRingBuffer *aRxRing)
* @return TRUE RX Ring Buffer is not empty
* @return FALSE RX Ring Buffer is empty
*/
static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
static bool K32WIsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
{
return (!aRxRing->isFull && (aRxRing->head == aRxRing->tail));
}
@@ -325,9 +325,23 @@ static bool JN5189IsEmptyRxRingBuffer(rxRingBuffer *aRxRing)
*
* @param[in] aRxRing Pointer to an RX Ring Buffer
*/
static void JN5189ResetRxRingBuffer(rxRingBuffer *aRxRing)
static void K32WResetRxRingBuffer(rxRingBuffer *aRxRing)
{
aRxRing->head = 0;
aRxRing->tail = 0;
aRxRing->isFull = false;
}
/**
* The UART driver weak functions definition.
*
*/
OT_TOOL_WEAK void otPlatUartSendDone(void)
{
}
OT_TOOL_WEAK void otPlatUartReceived(const uint8_t *aBuf, uint16_t aBufLength)
{
OT_UNUSED_VARIABLE(aBuf);
OT_UNUSED_VARIABLE(aBufLength);
}
src/core/common/tlvs.cpp
+1 -1
View File
@@ -59,7 +59,7 @@ otError Tlv::AppendTo(Message &aMessage) const
{
uint32_t size = GetSize();
OT_ASSERT(size <= UINT16_MAX);
// OT_ASSERT(size <= UINT16_MAX);
return aMessage.Append(this, static_cast<uint16_t>(size));
}
third_party/nxp/JN5189/MicroSpecific/Include/MicroInt.h
Vendored
-80
View File
@@ -1,80 +0,0 @@
/*****************************************************************************
*
* MODULE: Nested interrupt enabler
*
* COMPONENT: $RCSfile: MicroInt.h,v $
*
* VERSION: $Name: $
*
* REVISION: $Revision: 1.3 $
*
* DATED: $Date: 2009/07/15 10:44:32 $
*
* STATUS: $State: Exp $
*
* AUTHOR: CJG
*
* DESCRIPTION:
* Nested interrupt functions and macros
*
****************************************************************************
*
* (c) Copyright JENNIC Ltd 2008
*
****************************************************************************
*
* This software is owned by Jennic and/or its supplier and is protected
* under applicable copyright laws. All rights are reserved. We grant You,
* and any third parties, a license to use this software solely and
* exclusively on Jennic products. You, and any third parties must reproduce
* the copyright and warranty notice and any other legend of ownership on each
* copy or partial copy of the software.
*
* THIS SOFTWARE IS PROVIDED "AS IS". JENNIC MAKES NO WARRANTIES, WHETHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE,
* ACCURACY OR LACK OF NEGLIGENCE. JENNIC SHALL NOT, IN ANY CIRCUMSTANCES,
* BE LIABLE FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO, SPECIAL,
* INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON WHATSOEVER.
*
* Copyright Jennic Ltd 2008. All rights reserved
*
****************************************************************************/
#ifndef MICRO_INT_INCLUDED
#define MICRO_INT_INCLUDED
#if defined __cplusplus
extern "C" {
#endif
/****************************************************************************/
/*** Include Files ***/
/****************************************************************************/
#include "MicroSpecific.h"
/****************************************************************************/
/*** Macro Definitions ***/
/****************************************************************************/
/****************************************************************************/
/*** Type Definitions ***/
/****************************************************************************/
/****************************************************************************/
/*** Exported Functions ***/
/****************************************************************************/
/****************************************************************************/
/*** Exported Variables ***/
/****************************************************************************/
#if defined __cplusplus
}
#endif
#endif /* MICRO_INT_INCLUDED */
/****************************************************************************/
/*** END OF FILE ***/
/****************************************************************************/
third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific.h
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/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/****************************************************************************/
/*** Include files ***/
/****************************************************************************/
#define EXPAND1(x) x
#define EXPAND2(x, y) EXPAND1(x)y
#define EXPAND3(x, y, z) EXPAND2(x, y)z
/* Convoluted way to #include <MicroSpecific_JN51xx.h> */
#undef INCLUDE_NAME
#define INCLUDE_NAME <EXPAND3(MicroSpecific,JENNIC_CHIP_FAMILY_NAME,.h)>
#include INCLUDE_NAME
/****************************************************************************/
/*** END OF FILE ***/
/****************************************************************************/
third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_JN518x.h
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/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/****************************************************************************/
/*** Include files ***/
/****************************************************************************/
#include "MicroSpecific_arm_sdk2.h"
/****************************************************************************/
/*** END OF FILE ***/
/****************************************************************************/
third_party/nxp/JN5189/MicroSpecific/Include/MicroSpecific_arm_sdk2.h
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/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MICRO_SPECIFIC_INCLUDED
#define MICRO_SPECIFIC_INCLUDED
#if defined __cplusplus
extern "C" {
#endif
/****************************************************************************/
/*** Include Files ***/
/****************************************************************************/
#include <jendefs.h>
#include "JN5189.h"
extern void (*isr_handlers[])(void);
/****************************************************************************/
/*** Macro Definitions ***/
/****************************************************************************/
/** @{ Defined system call numbers */
#define SYSCALL_SEMIHOSTING 0xAB
#define SEMIHOSTING_WRITE0 0x04
#define SEMIHOSTING_READC 0x07
/** @} */
#define MICRO_INTERRUPT_EXCEPTION_OFFSET 16
// number of bits are defined by the hardware
#define MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS __NVIC_PRIO_BITS
// this macro depends on the setting of the priority group in the NVIC, setting G=3 in this case
#define MICRO_INTERRUPT_MAX_PRIORITY ((1 << MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS) - 1)
// half way
#define MICRO_INTERRUPT_MID_PRIORITY (MICRO_INTERRUPT_MAX_PRIORITY/2)
// Priority levels in the arm are higher for lower values - B-Semi chips were the other way around
#define MICRO_INTERRUPT_ELEVATED_PRIORITY (11)
#define MICRO_INTERRUPT_MEDIUM_PRIORITY (12)
// priority/sub priority register 8-bits wide
// read/write priority
#define MICRO_INTERRUPT_WRITE_PRIORITY_VALUE(W) ((W) << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
#define MICRO_INTERRUPT_READ_PRIORITY_VALUE(R) ((R) >> (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS))
// read/write sub-priority
#define MICRO_INTERRUPT_SUBPRIORITY_MASK ((1 << (8 - MICRO_INTERRUPT_NUMBER_OF_PRIORITY_BITS)) -1)
#define MICRO_INTERRUPT_SUBPRIORITY_VALUE(S) ((S) & (MICRO_INTERRUPT_SUBPRIORITY_MASK))
#define asm __asm__
#if 0 /* CJGTODO */
// JN5172 interrupt mappings
#define MICRO_ISR_NUM_TMR2 0
#define MICRO_ISR_NUM_TMR3 1
#define MICRO_ISR_NUM_TMR4 2
#define MICRO_ISR_NUM_TMR5 3
#define MICRO_ISR_NUM_TMR6 4
#define MICRO_ISR_NUM_TMR7 5
#define MICRO_ISR_NUM_SYSCTRL 6
#define MICRO_ISR_NUM_BBC 7 // MAC
#define MICRO_ISR_NUM_AES 8
#define MICRO_ISR_NUM_PHY 9
#define MICRO_ISR_NUM_UART0 10
#define MICRO_ISR_NUM_UART1 11
#define MICRO_ISR_NUM_SPIS 12
#define MICRO_ISR_NUM_SPIM 13
#define MICRO_ISR_NUM_I2C 14
#define MICRO_ISR_NUM_TMR0 15
#define MICRO_ISR_NUM_TMR1 16
#define MICRO_ISR_NUM_TMR8 17 // TIMER_ADC
#define MICRO_ISR_NUM_ANPER 18
#define MICRO_ISR_NUM_WDOG 19
// number of interrupts
#define MICRO_ISR_NUM 20
// mask
#define MICRO_ISR_EN_MASK ((1 << MICRO_ISR_NUM) - 1)
/* NOTE: Following are based on values above. Not all are defined for all
chips. So if an error is raised by the MICRO_ISR_MASK_* macros below, look
to see if the corresponding MICRO_ISR_NUM_* macro is defined above. If it
isn't, that peripheral is not present on the defined chip */
#define MICRO_ISR_MASK_SYSCTRL (1 << MICRO_ISR_NUM_SYSCTRL)
#define MICRO_ISR_MASK_BBC (1 << MICRO_ISR_NUM_BBC)
#define MICRO_ISR_MASK_AES (1 << MICRO_ISR_NUM_AES)
#define MICRO_ISR_MASK_PHY (1 << MICRO_ISR_NUM_PHY)
#define MICRO_ISR_MASK_UART0 (1 << MICRO_ISR_NUM_UART0)
#define MICRO_ISR_MASK_UART1 (1 << MICRO_ISR_NUM_UART1)
#define MICRO_ISR_MASK_TMR0 (1 << MICRO_ISR_NUM_TMR0)
#define MICRO_ISR_MASK_TMR1 (1 << MICRO_ISR_NUM_TMR1)
#define MICRO_ISR_MASK_TMR2 (1 << MICRO_ISR_NUM_TMR2)
#define MICRO_ISR_MASK_TMR3 (1 << MICRO_ISR_NUM_TMR3)
#define MICRO_ISR_MASK_TMR4 (1 << MICRO_ISR_NUM_TMR4)
#define MICRO_ISR_MASK_I2C (1 << MICRO_ISR_NUM_I2C)
#define MICRO_ISR_MASK_SPIM (1 << MICRO_ISR_NUM_SPIM)
#define MICRO_ISR_MASK_SPIS (1 << MICRO_ISR_NUM_SPIS)
#define MICRO_ISR_MASK_INTPER (1 << MICRO_ISR_NUM_INTPER)
#define MICRO_ISR_MASK_ANPER (1 << MICRO_ISR_NUM_ANPER)
#define MICRO_ISR_MASK_WDOG (1 << MICRO_ISR_NUM_WDOG)
#endif
/* Handy macros for controlling interrupts, PIC, interrupt levels */
#define MICRO_ENABLE_INTERRUPTS() \
asm volatile ("CPSIE I;" : : );
#define MICRO_DISABLE_INTERRUPTS() \
asm volatile ("CPSID I;" : : );
extern void vAHI_InterruptSetPriority(uint32 u32Mask, uint8 u8Level);
extern uint8 u8AHI_InterruptGetPriority(uint32 u32InterruptNumber);
extern void vAHI_InterruptDisable(uint32 u32EnableMask);
extern void vAHI_TickTimerIntEnable(bool_t bIntEnable);
extern void vAHI_InterruptSetActivePriorityLevel(uint8 u8Level);
extern uint8 u8AHI_InterruptReadActivePriorityLevel(void);
#define MICRO_ENABLE_TICK_TIMER_INTERRUPT(); \
vAHI_TickTimerIntEnable(TRUE);
// use same value as Jennic/BA devices
#define MICRO_SET_PIC_ENABLE(A) \
vAHI_InterruptSetPriority(A, 8);
#define MICRO_CLEAR_PIC_ENABLE(A) \
vAHI_InterruptDisable(A)
#define MICRO_SET_PIC_PRIORITY_LEVEL(A,B) \
vAHI_InterruptSetPriority(A, B);
#define MICRO_GET_PIC_PRIORITY_LEVEL(A) \
u8AHI_InterruptGetPriority(A);
/* MRS Move to register from status */
/* MSR Move to status register */
#define MICRO_SET_ACTIVE_INT_LEVEL(A) \
({ \
register uint32 __u32interruptLevelStore = A; \
asm volatile ("MSR BASEPRI, %[intlevelstore];" \
: \
:[intlevelstore] "r"(__u32interruptLevelStore) \
); \
})
#define MICRO_SET_ACTIVE_INT_LEVEL_MAX(A) \
({ \
register uint32 __u32interruptLevelStore = A; \
asm volatile ("MSR BASEPRI_MAX, %[intlevelstore];" \
: \
:[intlevelstore] "r"(__u32interruptLevelStore) \
); \
})
#define MICRO_GET_ACTIVE_INT_LEVEL() \
({ \
register uint32 __u32interruptActiveLevel; \
asm volatile ("MRS %[activelevelstore], BASEPRI;" \
:[activelevelstore] "=r"(__u32interruptActiveLevel) \
: ); \
__u32interruptActiveLevel; \
})
#define MICRO_SET_PRIMASK_LEVEL(A) \
({ \
register uint32 __u32primaskLevelStore = A; \
asm volatile ("MSR PRIMASK, %[primasklevelstore];" \
: \
:[primasklevelstore] "r"(__u32primaskLevelStore) \
); \
})
#define MICRO_GET_PRIMASK_LEVEL() \
({ \
register uint32 __u32primaskLevelStore; \
asm volatile ("MRS %[primasklevelstore], PRIMASK;" \
:[primasklevelstore] "=r"(__u32primaskLevelStore) \
: \
); \
__u32primaskLevelStore; \
})
// read back PRIMASK status into u32Store variable then disable the interrupts
#define MICRO_DISABLE_AND_SAVE_INTERRUPTS(u32Store) \
({ \
asm volatile ("MRS %[primasklevelstore], PRIMASK;" \
:[primasklevelstore] "=r"(u32Store) \
: \
); \
asm volatile ("CPSID I;" : : ); \
})
#define MICRO_RESTORE_INTERRUPTS(u32Store) \
({ \
asm volatile ("MSR PRIMASK, %[primasklevelstore];" \
: \
:[primasklevelstore] "r"(u32Store) \
); \
})
// using AAPCS the parameter (the stack frame) will map to r0
#define MICRO_GET_EXCEPTION_STACK_FRAME() \
{ \
asm volatile("MRS R0, MSP"); \
}
// macro using privilege/non�privilege model
#define MICRO_GET_EXCEPTION_STACK_FRAME_PNPM() \
({ \
asm volatile("TST LR, #4"); \
asm volatile("ITE EQ"); \
asm volatile("MRSEQ R0, MSP"); \
asm volatile("MRSNE R0, PSP"); \
})
#define FF1(__input) \
({ register uint32 __reverse, __result, __return; \
asm volatile ("RBIT %[reverse], %[input];" \
: [reverse] "=r" (__reverse) \
: [input] "r" (__input) \
); \
asm volatile ("CLZ %[result], %[reverse];" \
: [result] "=r" (__result) \
: [reverse] "r" (__reverse) \
); \
__return = ((__result == 32) ? 0 : __result+1); \
__return; })
#if 0 /* In chip_jn518x\inc/core_cmInstr.h */
/* Reverse byte order */
#define __REV(A) \
({ \
register uint32 __reverse, __input = A; \
asm volatile ("REV %[reverse], %[input];" \
: [reverse] "=r" (__reverse) \
: [input] "r" (__input) \
); \
__reverse; \
})
#endif
#define MICRO_GET_LX() \
({ \
register uint32 __u32lxRegister; \
asm volatile ("MOV %[lxRegister], R14;" \
:[lxRegister] "=r"(__u32lxRegister) \
: \
); \
__u32lxRegister; \
})
#define MICRO_GET_STACK_LEVEL() \
({ \
register uint32 __u32stackRegister; \
asm volatile ("MOV %[stackRegister], SP;" \
:[stackRegister] "=r"(__u32stackRegister) \
: \
); \
__u32stackRegister; \
})
/* Interrupt Handler registration - only useful if you're putting the handlers
* in RAM */
/* Location of isr_handlers is no longer at a known location, but we can link
to it directly instead */
#define MICRO_SET_INT_HANDLER(INT, FUNC); \
isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)] = (void *)(FUNC);
#define MICRO_GET_INT_HANDLER(INT) \
(isr_handlers[(MICRO_INTERRUPT_EXCEPTION_OFFSET + INT)])
/* Nested interrupt control */
#define MICRO_INT_STORAGE tsMicroIntStorage sIntStorage
#define MICRO_INT_ENABLE_ONLY(A) vMicroIntEnableOnly(&sIntStorage, A)
#define MICRO_INT_RESTORE_STATE() vMicroIntRestoreState(&sIntStorage)
/* Exception Handlers */
#define MICRO_ESR_NUM_RESETISR 1
#define MICRO_ESR_NUM_NMI 2
#define MICRO_ESR_NUM_HARDFAULT 3
#define MICRO_ESR_NUM_MEMMANAGE 4
#define MICRO_ESR_NUM_BUSFAULT 5
#define MICRO_ESR_NUM_USGFAULT 6
// 4 reserved handlers here
#define MICRO_ESR_NUM_SVCALL 11
#define MICRO_ESR_NUM_DEBUGMON 12
// 1 reserved handler here
#define MICRO_ESR_NUM_PENDSV 14
#define MICRO_ESR_NUM_SYSTICK 15
/* Location of exception_handlers is no longer at a known location, but we can link
to it directly instead - only useful if you're putting the handlers
* in RAM */
#define MICRO_SET_EXCEPTION_HANDLER(EXCEPTION, FUNC) \
isr_handlers[EXCEPTION] = (void *)(FUNC);
#define MICRO_GET_EXCEPTION_HANDLER(INT) \
(isr_handlers[EXCEPTION])
/* NOP instruction */
#define MICRO_NOP() \
{ \
asm volatile ("nop;"); \
}
/* TRAP instruction */
#define MICRO_TRAP() \
{ \
asm volatile("BKPT 0;"); \
}
#define MICRO_JUMP_TO_ADDRESS(ADDRESS) \
({ \
register uint32 __u32programAddressStore = ADDRESS | 0x1; \
asm volatile ("BLX %[programAddressStore];" \
: \
:[programAddressStore] "r"(__u32programAddressStore)); \
})
/****************************************************************************/
/*** Type Definitions ***/
/****************************************************************************/
/* Nested interrupt control */
typedef struct
{
uint8 u8Level;
} tsMicroIntStorage;
/****************************************************************************/
/*** Exported Functions ***/
/****************************************************************************/
PUBLIC void vAHI_InitialiseInterruptController(uint32 *pu32InterruptVectorTable);
/* Nested interrupt control */
PUBLIC void vMicroIntSetGlobalEnable(uint32 u32EnableMask);
PUBLIC void vMicroIntEnableOnly(tsMicroIntStorage *, uint32 u32EnableMask);
PUBLIC void vMicroIntRestoreState(tsMicroIntStorage *);
/* Default Exception Handler */
PUBLIC void vIntDefaultHandler(void);
PUBLIC void __attribute__((noinline)) vMicroSyscall(volatile uint32 u32SysCallNumber, ...);
PUBLIC void __attribute__((noinline)) vMicroSemihost(volatile uint32 u32SemihostNumber, ...);
/****************************************************************************/
/*** Exported Variables ***/
/****************************************************************************/
#if defined __cplusplus
}
#endif
#endif /* MICRO_SPECIFIC_INCLUDED */
/****************************************************************************/
/*** END OF FILE ***/
/****************************************************************************/
third_party/nxp/JN5189/Radio_JN5189/.cproject
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@@ -1,389 +0,0 @@
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<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
&lt;TargetConfig&gt;&#13;
&lt;Properties property_2="JN518x.cfx" property_3="NXP" property_4="JN5189" property_count="5" version="100200"/&gt;&#13;
&lt;infoList vendor="NXP"&gt;&lt;info chip="JN5189" flash_driver="JN518x.cfx" match_id="0x0" name="JN5189" stub="crt_emu_cm3_gen"&gt;&lt;chip&gt;&lt;name&gt;JN5189&lt;/name&gt;&#13;
&lt;family&gt;JN518x&lt;/family&gt;&#13;
&lt;vendor&gt;NXP Semiconductor&lt;/vendor&gt;&#13;
&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
&lt;memory id="RAM" type="RAM"/&gt;&#13;
&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
&lt;memoryInstance derived_from="Flash" id="Flash640" location="0x0" size="0xA0000"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RAM0" location="0x4000400" size="0x15C00"/&gt;&#13;
&lt;memoryInstance derived_from="RAM" id="RAM1" location="0x4020000" size="0x10000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
&lt;peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
&lt;/chip&gt;&#13;
&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
&lt;/processor&gt;&#13;
&lt;link href="JN518x_peripheral.xml" show="embed" type="simple"/&gt;&#13;
&lt;/info&gt;&#13;
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</storageModule>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Radio_Lib Release"/>
<configuration configurationName="Radio_Test_Lib_Debug"/>
<configuration configurationName="Radio Test Lib Debug">
<resource resourceType="PROJECT" workspacePath="/Radio"/>
</configuration>
<configuration configurationName="Debug Untrimmed and no MAC"/>
<configuration configurationName="Radio_Lib Debug"/>
<configuration configurationName="Radio Lib Debug Untrimmed and no MAC">
<resource resourceType="PROJECT" workspacePath="/Radio"/>
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<configuration configurationName="Radio_Test_Lib_Release"/>
<configuration configurationName="Radio_Test_Lib_Release_ES1"/>
<configuration configurationName="Radio Lib Release">
<resource resourceType="PROJECT" workspacePath="/Radio"/>
</configuration>
<configuration configurationName="Rdaio_Lib_Debug_ES2"/>
<configuration configurationName="Radio_Lib_Debug"/>
<configuration configurationName="Radio_Lib Debug Untrimmed and no MAC"/>
<configuration configurationName="Radio_Lib_Debug_ES2">
<resource resourceType="PROJECT" workspacePath="/Radio"/>
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<configuration configurationName="Radio_Lib_Debug_ES1"/>
<configuration configurationName="Radio_Test_Lib_Debug_ES1"/>
<configuration configurationName="Radio_Test_Lib Debug"/>
<configuration configurationName="Radio Test Lib Release">
<resource resourceType="PROJECT" workspacePath="/Radio"/>
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<configuration configurationName="Radio_Test_Lib Release"/>
<configuration configurationName="Radio_Lib_Release"/>
<configuration configurationName="Radio_Lib_Release_ES1"/>
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/Radio"/>
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<configuration configurationName="Release"/>
<configuration configurationName="Radio Lib Debug">
<resource resourceType="PROJECT" workspacePath="/Radio"/>
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third_party/nxp/JN5189/Radio_JN5189/.project
Vendored
-32
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@@ -1,32 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>Radio</name>
<comment></comment>
<projects>
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<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
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<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
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<variableList>
<variable>
<name>SDK_BASE_DIR</name>
<value>$%7BPARENT-1-WORKSPACE_LOC%7D</value>
</variable>
</variableList>
</projectDescription>
third_party/nxp/JN5189/Radio_JN5189/Include/BbcAndPhyRegs.h
Vendored
-365
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@@ -1,365 +0,0 @@
/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BBC_AND_PHY_REGS_H
#define BBC_AND_PHY_REGS_H
#if defined __cplusplus
extern "C" {
#endif
/****************************************************************************/
/*** Include Files ***/
/****************************************************************************/
#include "jn518x.h"
#include "jn518x_zb_mac.h"
#include "jn518x_zb_modem.h"
#include "jn518x_rfp_modem.h"
/****************************************************************************/
/*** Macro/Type Definitions ***/
/****************************************************************************/
#define vREG_BbcWrite(REG, VAL) JN518X_ZBMAC->REG = (VAL)
#define u32REG_BbcRead(REG) (JN518X_ZBMAC->REG)
#define vREG_PhyWrite(REG, VAL) JN518X_ZBMODEM->REG = (VAL)
#define u32REG_PhyRead(REG) (JN518X_ZBMODEM->REG)
#define vREG_XcvrPhyWrite(REG, VAL) JN518X_ZBMODEM->REG = (VAL)
#define u32REG_XcvrPhyRead(REG) (JN518X_ZBMODEM->REG)
#define vREG_PhyReadModWrite32(eOffset, u32Mask, u32Data) \
vREG_PhyWrite(eOffset, (((u32Mask) & (u32Data)) \
| (~(u32Mask) & (u32REG_PhyRead(eOffset)))))
#define vREG_BbcReadModWrite32(eOffset, u32Mask, u32Data) \
vREG_BbcWrite(eOffset, (((u32Mask) & (u32Data)) \
| (~(u32Mask) & (u32REG_BbcRead(eOffset)))))
#ifndef BIT_W_1
#define BIT_W_1 0x00000001UL
#define BIT_W_2 0x00000003UL
#define BIT_W_3 0x00000007UL
#define BIT_W_4 0x0000000FUL
#define BIT_W_5 0x0000001FUL
#define BIT_W_6 0x0000003FUL
#define BIT_W_7 0x0000007FUL
#define BIT_W_8 0x000000FFUL
#define BIT_W_10 0x000003FFUL
#define BIT_W_12 0x00000FFFUL
#define BIT_W_15 0x00007FFFUL
#define BIT_W_16 0x0000FFFFUL
#define BIT_W_17 0x0001FFFFUL
#define BIT_W_18 0x0003FFFFUL
#define BIT_W_19 0x0007FFFFUL
#define BIT_W_20 0x000FFFFFUL
#define BIT_W_21 0x001FFFFFUL
#define BIT_W_25 0x01FFFFFFUL
#endif
/**** BBC IER/ISR ****/
#define REG_BBC_INT_TX_BIT 0
#define REG_BBC_INT_TX_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_TX_BIT))
#define REG_BBC_INT_RX_H_BIT 1
#define REG_BBC_INT_RX_H_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_RX_H_BIT))
#define REG_BBC_INT_RX_BIT 2
#define REG_BBC_INT_RX_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_RX_BIT))
#define REG_BBC_INT_M0_BIT 4
#define REG_BBC_INT_M0_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_M0_BIT))
#define REG_BBC_INT_M1_BIT 5
#define REG_BBC_INT_M1_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_M1_BIT))
#define REG_BBC_INT_M2_BIT 6
#define REG_BBC_INT_M2_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_M2_BIT))
#define REG_BBC_INT_M3_BIT 7
#define REG_BBC_INT_M3_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_M3_BIT))
#define REG_BBC_INT_T0_BIT 8
#define REG_BBC_INT_T0_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_T0_BIT))
#define REG_BBC_INT_T1_BIT 9
#define REG_BBC_INT_T1_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_T1_BIT))
#define REG_BBC_INT_T2_BIT 10
#define REG_BBC_INT_T2_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_T2_BIT))
#define REG_BBC_INT_T3_BIT 11
#define REG_BBC_INT_T3_MASK ((uint32)(BIT_W_1 << REG_BBC_INT_T3_BIT))
#define REG_BBC_INT_TIMER_MASK ((uint32)(BIT_W_6 << REG_BBC_INT_M0_BIT))
/**** REG_BBC_TXMBEBT ****/
#define REG_BBC_TXMBEBT_MINBE_BIT (0)
#define REG_BBC_TXMBEBT_MINBE_MASK ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_MINBE_BIT))
#define REG_BBC_TXMBEBT_MAXBO_BIT (4)
#define REG_BBC_TXMBEBT_MAXBO_MASK ((uint32)(BIT_W_3 << REG_BBC_TXMBEBT_MAXBO_BIT))
#define REG_BBC_TXMBEBT_BLE_BIT (7)
#define REG_BBC_TXMBEBT_MAXBE_BIT (8)
#define REG_BBC_TXMBEBT_MAXBE_MASK ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_MAXBE_BIT))
#define REG_BBC_TXMBEBT_CSMA_DLY_BIT (12)
#define REG_BBC_TXMBEBT_CSMA_DLY_MASK ((uint32)(BIT_W_1 << REG_BBC_TXMBEBT_CSMA_DLY_BIT))
#define REG_BBC_TXMBEBT_DIR_DLY_BIT (13)
#define REG_BBC_TXMBEBT_DIR_DLY_MASK ((uint32)(BIT_W_4 << REG_BBC_TXMBEBT_DIR_DLY_BIT))
#define REG_BBC_TXMBEBT_FORMAT(dir_dly, min_be, ble, max_boffs, max_be) \
(((min_be) & BIT_W_4) | \
(((ble) & BIT_W_1) << REG_BBC_TXMBEBT_BLE_BIT) | \
(((max_be) & BIT_W_4) << REG_BBC_TXMBEBT_MAXBE_BIT) | \
(((max_boffs) & BIT_W_3) << REG_BBC_TXMBEBT_MAXBO_BIT) | \
(((dir_dly) & BIT_W_4) << REG_BBC_TXMBEBT_DIR_DLY_BIT) \
)
/**** REG_TXSTAT ****/
#define REG_BBC_TXSTAT_CCAE_BIT 0
#define REG_BBC_TXSTAT_CCAE_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_CCAE_BIT))
#define REG_BBC_TXSTAT_ACKE_BIT 1
#define REG_BBC_TXSTAT_ACKE_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_ACKE_BIT))
#define REG_BBC_TXSTAT_OOTE_BIT 2
#define REG_BBC_TXSTAT_OOTE_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_OOTE_BIT))
#define REG_BBC_TXSTAT_RXABT_BIT 3
#define REG_BBC_TXSTAT_RXABT_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_RXABT_BIT))
#define REG_BBC_TXSTAT_RXFP_BIT 4
#define REG_BBC_TXSTAT_RXFP_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_RXFP_BIT))
#define REG_BBC_TXSTAT_TXTO_BIT 5
#define REG_BBC_TXSTAT_TXTO_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_TXTO_BIT))
#define REG_BBC_TXSTAT_TXPCTO_BIT 6
#define REG_BBC_TXSTAT_TXPCTO_MASK ((uint32)(BIT_W_1 << REG_BBC_TXSTAT_TXPCTO_BIT))
/**** TXCTL ****/
#define REG_BBC_TXCTL_SCH_BIT 0
#define REG_BBC_TXCTL_SCH_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SCH_BIT))
#define REG_BBC_TXCTL_SS_BIT 1
#define REG_BBC_TXCTL_SS_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SS_BIT))
#define REG_BBC_TXCTL_SOVR_BIT 2
#define REG_BBC_TXCTL_SOVR_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_SOVR_BIT))
#define REG_BBC_TXCTL_AA_BIT 3
#define REG_BBC_TXCTL_AA_MASK ((uint32)(BIT_W_1 << REG_BBC_TXCTL_AA_BIT))
#define REG_BBC_TXCTL_MODE_BIT 4
#define REG_BBC_TXCTL_MODE_MASK ((uint32)(BIT_W_2 << REG_BBC_TXCTL_MODE_BIT))
#define REG_BBC_TXCTL_VALUE(sched_basis, sched_ss, slot_override, auto_ack, mode) \
(((sched_basis) & BIT_W_1) | \
(((sched_ss) & BIT_W_1) << REG_BBC_TXCTL_SS_BIT) | \
(((slot_override) & BIT_W_1) << REG_BBC_TXCTL_SOVR_BIT) | \
(((auto_ack) & BIT_W_1) << REG_BBC_TXCTL_AA_BIT) | \
(((mode) & BIT_W_2) << REG_BBC_TXCTL_MODE_BIT))
#define REG_BBC_TXCTL_SEND_AT(mode) REG_BBC_TXCTL_VALUE(1, 1, 0, 1, (mode))
#define REG_BBC_TXCTL_SEND_NOW(mode) REG_BBC_TXCTL_VALUE(0, 1, 0, 1, (mode))
/**** RXMPID ****/
#define REG_BBC_RXMPID_PAN_ID_BIT 0
#define REG_BBC_RXMPID_PAN_ID_MASK ((uint32)(BIT_W_16 << REG_BBC_RXMPID_PAN_ID_BIT))
#define REG_BBC_RXMPID_COORD_BIT 16
#define REG_BBC_RXMPID_COORD_MASK ((uint32)(BIT_W_1 << REG_BBC_RXMPID_COORD_BIT))
/**** RXPROM ****/
#define REG_BBC_RXPROM_AM_BIT 0
#define REG_BBC_RXPROM_AM_MASK ((uint32)(BIT_W_1 << REG_BBC_RXPROM_AM_BIT))
#define REG_BBC_RXPROM_FCSE_BIT 1
#define REG_BBC_RXPROM_FCSE_MASK ((uint32)(BIT_W_1 << REG_BBC_RXPROM_FCSE_BIT))
#define REG_BBC_RXPROM_AMAL_BIT 2
#define REG_BBC_RXPROM_AMAL_MASK ((uint32)(BIT_W_1 << REG_BBC_RXPROM_AMAL_BIT))
/**** REG_RXSTAT ****/
#define REG_BBC_RXSTAT_FCSE_BIT 0
#define REG_BBC_RXSTAT_FCSE_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_FCSE_BIT))
#define REG_BBC_RXSTAT_ABORT_BIT 1
#define REG_BBC_RXSTAT_ABORT_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_ABORT_BIT))
#define REG_BBC_RXSTAT_INPKT_BIT 4
#define REG_BBC_RXSTAT_INPKT_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_INPKT_BIT))
#define REG_BBC_RXSTAT_MAL_BIT 5
#define REG_BBC_RXSTAT_MAL_MASK ((uint32)(BIT_W_1 << REG_BBC_RXSTAT_MAL_BIT))
/**** RXCTL ****/
#define REG_BBC_RXCTL_SCH_BIT 0
#define REG_BBC_RXCTL_SCH_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_SCH_BIT))
#define REG_BBC_RXCTL_SS_BIT 1
#define REG_BBC_RXCTL_SS_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_SS_BIT))
#define REG_BBC_RXCTL_ICAP_BIT 2
#define REG_BBC_RXCTL_ICAP_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_ICAP_BIT))
#define REG_BBC_RXCTL_AA_BIT 3
#define REG_BBC_RXCTL_AA_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_AA_BIT))
#define REG_BBC_RXCTL_PRSP_BIT 4
#define REG_BBC_RXCTL_PRSP_MASK ((uint32)(BIT_W_1 << REG_BBC_RXCTL_PRSP_BIT))
#define REG_BBC_RXCTL_FORMAT(sched_basis, sched_ss, in_cap, auto_ack) \
(((sched_basis) & BIT_W_1) | \
(((sched_ss) & BIT_W_1) << REG_BBC_RXCTL_SS_BIT) | \
(((in_cap) & BIT_W_1) << REG_BBC_RXCTL_ICAP_BIT) | \
(((auto_ack) & BIT_W_1) << REG_BBC_RXCTL_AA_BIT))
/**** SM_STATE ****/
#define REG_BBC_SM_STATE_SUP_BIT 0
#define REG_BBC_SM_STATE_SUP_MASK ((uint32)(BIT_W_4 << REG_BBC_SM_STATE_SUP_BIT))
#define REG_BBC_SM_STATE_CSMA_BIT 4
#define REG_BBC_SM_STATE_CSMA_MASK ((uint32)(BIT_W_3 << REG_BBC_SM_STATE_CSMA_BIT))
#define REG_BBC_SM_STATE_ISA_BIT 8
#define REG_BBC_SM_STATE_ISA_MASK ((uint32)(BIT_W_5 << REG_BBC_SM_STATE_ISA_BIT))
/**** SCTCR ****/
#define REG_BBC_SCTCR_E0_BIT 0
#define REG_BBC_SCTCR_E0_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTCR_E0_BIT))
#define REG_BBC_SCTCR_E1_BIT 1
#define REG_BBC_SCTCR_E1_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTCR_E1_BIT))
/**** SCTL ****/
#define REG_BBC_SCTL_USE_BIT 0
#define REG_BBC_SCTL_USE_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_USE_BIT))
#define REG_BBC_SCTL_SNAP_BIT 1
#define REG_BBC_SCTL_SNAP_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_SNAP_BIT))
#define REG_BBC_SCTL_CO_BIT 2
#define REG_BBC_SCTL_CO_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_CO_BIT))
// bit name changed
#define REG_BBC_SCTL_CE_BIT 2
#define REG_BBC_SCTL_CE_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_CE_BIT))
#define REG_BBC_SCTL_PHYON_BIT 3
#define REG_BBC_SCTL_PHYON_MASK ((uint32)(BIT_W_1 << REG_BBC_SCTL_PHYON_BIT))
/**** RXFCTL/TXFCTL ****/
/* Operations on Frame header */
#define REG_BBC_FCTL_TYPE_BIT 0
#define REG_BBC_FCTL_TYPE_MASK ((uint32)(BIT_W_3/* << REG_BBC_FCTL_TYPE_BIT*/)) /* Optimised bit 0 */
#define REG_BBC_FCTL_SEC_BIT 3
#define REG_BBC_FCTL_SEC_MASK ((uint32)(BIT_W_1 << REG_BBC_FCTL_SEC_BIT))
#define REG_BBC_FCTL_FP_BIT 4
#define REG_BBC_FCTL_FP_MASK ((uint32)(BIT_W_1 << REG_BBC_FCTL_FP_BIT))
#define REG_BBC_FCTL_ACK_BIT 5
#define REG_BBC_FCTL_ACK_MASK ((uint32)(BIT_W_1 << REG_BBC_FCTL_ACK_BIT))
#define REG_BBC_FCTL_IP_BIT 6
#define REG_BBC_FCTL_IP_MASK ((uint32)(BIT_W_1 << REG_BBC_FCTL_IP_BIT))
#define REG_BBC_FCTL_DAM_BIT 10
#define REG_BBC_FCTL_DAM_MASK ((uint32)(BIT_W_2 << REG_BBC_FCTL_DAM_BIT))
#define REG_BBC_FCTL_DAM(x) (((x) & REG_BBC_FCTL_DAM_MASK) >> REG_BBC_FCTL_DAM_BIT)
#define REG_BBC_FCTL_SAM_BIT 14
#define REG_BBC_FCTL_SAM_MASK ((uint32)(BIT_W_2 << REG_BBC_FCTL_SAM_BIT))
#define REG_BBC_FCTL_SAM(x) (((x) & REG_BBC_FCTL_SAM_MASK) >> REG_BBC_FCTL_SAM_BIT)
/* Frame types */
#define REG_BBC_FCTL_TYPE_BEACON 0
#define REG_BBC_FCTL_TYPE_DATA 1
#define REG_BBC_FCTL_TYPE_ACK 2
#define REG_BBC_FCTL_TYPE_CMD 3
/* Addr modes */
#define REG_BBC_FCTL_AM_NONE 0
#define REG_BBC_FCTL_AM_RSVD 1
#define REG_BBC_FCTL_AM_SHORT 2
#define REG_BBC_FCTL_AM_EXT 3
#define REG_BBC_FCTL_FORMAT(type, sec, fp, ack, ip, dam, sam) \
(((type) & BIT_W_3) | \
(((sec) & BIT_W_1) << REG_BBC_FCTL_SEC_BIT) | \
(((fp) & BIT_W_1) << REG_BBC_FCTL_FP_BIT) | \
(((ack) & BIT_W_1) << REG_BBC_FCTL_ACK_BIT) | \
(((ip) & BIT_W_1) << REG_BBC_FCTL_IP_BIT) | \
(((dam) & BIT_W_2) << REG_BBC_FCTL_DAM_BIT) | \
(((sam) & BIT_W_2) << REG_BBC_FCTL_SAM_BIT))
/**** MCCA_CTRL ****/
#define REG_PHY_MCCA_CCAM_BIT 0
#define REG_PHY_MCCA_CCAM_MASK ((uint32)(BIT_W_2 << REG_PHY_MCCA_CCAM_BIT))
#define REG_PHY_MCCA_CCA_ED_THR_BIT 2
#define REG_PHY_MCCA_CCA_ED_THR_MASK ((uint32)(BIT_W_10 << REG_PHY_MCCA_CCA_ED_THR_BIT))
/**** MSTAT ****/
#define REG_PHY_MSTAT_ED_BIT 6
#define REG_PHY_MSTAT_ED_MASK ((uint32)(BIT_W_10 << REG_PHY_MSTAT_ED_BIT))
#define REG_PHY_MSTAT_SQI_BIT 16
#define REG_PHY_MSTAT_SQI_MASK ((uint32)(BIT_W_8 << REG_PHY_MSTAT_SQI_BIT))
#define REG_PHY_MSTAT_MCCAS_BIT 24
#define REG_PHY_MSTAT_MCCAS_MASK ((uint32)(BIT_W_1 << REG_PHY_MSTAT_MCCAS_BIT))
/**** PHY_MCTRL ****/
#define REG_PHY_MCTRL_MIOM_BIT 1
#define REG_PHY_MCTRL_MIOM_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MIOM_BIT))
#define REG_PHY_MCTRL_MPHYON_BIT 2
#define REG_PHY_MCTRL_MPHYON_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MPHYON_BIT))
#define REG_PHY_MCTRL_MPHYTX_BIT 3
#define REG_PHY_MCTRL_MPHYTX_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MPHYTX_BIT))
#define REG_PHY_MCTRL_MCCAT_BIT 4
#define REG_PHY_MCTRL_MCCAT_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MCCAT_BIT))
#define REG_PHY_MCTRL_MEDT_BIT 5
#define REG_PHY_MCTRL_MEDT_MASK ((uint32)(BIT_W_1 << REG_PHY_MCTRL_MEDT_BIT))
/**** PHY_PWR ****/
#define REG_PHY_PWR_BIT 0
#define REG_PHY_PWR_MASK ((uint32)(BIT_W_1 << REG_PHY_PWR_BIT))
/**** PHY IER/ISR ****/
#define REG_PHY_INT_ED_BIT 3
#define REG_PHY_INT_ED_MASK ((uint32)(BIT_W_1 << REG_PHY_INT_ED_BIT))
#define REG_PHY_INT_CCA_BIT 4
#define REG_PHY_INT_CCA_MASK ((uint32)(BIT_W_1 << REG_PHY_INT_CCA_BIT))
/* Register equivalents, mapping from old names to new ones */
#define REG_BBC_ISR ISR
#define REG_BBC_IER IER
#define REG_BBC_RXCTL RXCTL
#define REG_BBC_SM_STATE SM_STATE
#define REG_BBC_MISR MISR
#define REG_BBC_SCFRC SCFRC
#define REG_BBC_SCESL SCESL
#define REG_BBC_RXMPID RXMPID
#define REG_BBC_RXMSAD RXMSAD
#define REG_BBC_RXMEADL RXMEADL
#define REG_BBC_RXMEADH RXMEADH
#define REG_BBC_RXETST RXETST
#define REG_BBC_TXCTL TXCTL
#define REG_BBC_SCTL SCTL
#define REG_BBC_RXBUFAD RXBUFAD
#define REG_BBC_RXPROM RXPROM
#define REG_BBC_RXSTAT RXSTAT
#define REG_BBC_RXTSTP RXTSTP
#define REG_BBC_TXRETRY TXTRIES
#define REG_BBC_TXMBEBT TXMBEBT
#define REG_BBC_TXTSTP TXTSTP
#define REG_BBC_TXCSMAC TXCSMAC
#define REG_BBC_TXBUFAD TXBUFAD
#define REG_BBC_TXSTAT TXSTAT
#define REG_BBC_TXASC TXASC
#define REG_BBC_PRBSS PRBS_SEED
#define REG_BBC_SCMR0 SCMR0
#define REG_BBC_SCTR1 SCTR1
#define REG_BBC_SCTCR SCTCR
#define REG_BBC_TXPEND TXPEND
#define REG_BBC_PRTT PHYRXTUNETIME
#define REG_BBC_TAT TURNAROUNDTIME
#define REG_BBC_LIFS_TURNAROUND LIFSTURNAROUNDTIME
#define REG_BBC_SCTR0 SCTR0
#define REG_PHY_CHAN PHY_CHAN
#define REG_PHY_MCTRL PHY_MCTRL
#define REG_PHY_MSTAT0 MSTAT
#define REG_PHY_MCCA MCCA_CTRL
/****************************************************************************/
/*** Exported Functions ***/
/****************************************************************************/
/****************************************************************************/
/*** Exported Variables ***/
/****************************************************************************/
#if defined __cplusplus
}
#endif
#endif /* #ifndef BBC_AND_PHY_REGS_H */
/****************************************************************************/
/*** END OF FILE ***/
/****************************************************************************/
third_party/nxp/JN5189/Radio_JN5189/Include/jn518x.h
Vendored
-6
View File
@@ -1,6 +0,0 @@
#include "JN5189.h"
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
#include "jn518xHW_ES1.h"
#else
#include "jn518xHW.h"
#endif
third_party/nxp/JN5189/Radio_JN5189/Include/jn518xHW.h
Vendored
-22585
View File
File diff suppressed because it is too large Load Diff
third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_ble_link.h
Vendored
-870
View File
@@ -1,870 +0,0 @@
/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __BLE_LINK_IF_H__
#define __BLE_LINK_IF_H__
typedef struct {
/* Address 0x000 */
union {
__IO uint32_t RW_BLE_RWBLECNTL;
struct {
__IO uint32_t rw_ble_rwblecntl : 32;
} RW_BLE_RWBLECNTL_b;
};
/* Address 0x004 */
union {
__IO uint32_t RW_BLE_VERSION;
struct {
__IO uint32_t rw_ble_version : 32;
} RW_BLE_VERSION_b;
};
/* Address 0x008 */
union {
__IO uint32_t RW_BLE_RWBLECONF;
struct {
__IO uint32_t rw_ble_rwbleconf : 32;
} RW_BLE_RWBLECONF_b;
};
/* Address 0x00C */
union {
__IO uint32_t RW_BLE_INTCNTL;
struct {
__IO uint32_t rw_ble_intcntl : 32;
} RW_BLE_INTCNTL_b;
};
/* Address 0x010 */
union {
__IO uint32_t RW_BLE_INTSTAT;
struct {
__IO uint32_t rw_ble_intstat : 32;
} RW_BLE_INTSTAT_b;
};
/* Address 0x014 */
union {
__IO uint32_t RW_BLE_INTRAWSTAT;
struct {
__IO uint32_t rw_ble_intrawstat : 32;
} RW_BLE_INTRAWSTAT_b;
};
/* Address 0x018 */
union {
__IO uint32_t RW_BLE_INTACK;
struct {
__IO uint32_t rw_ble_intack : 32;
} RW_BLE_INTACK_b;
};
/* Address 0x01C */
union {
__IO uint32_t RW_BLE_BASETIMECNT;
struct {
__IO uint32_t rw_ble_basetimecnt : 32;
} RW_BLE_BASETIMECNT_b;
};
/* Address 0x020 */
union {
__IO uint32_t RW_BLE_FINETIMECNT;
struct {
__IO uint32_t rw_ble_finetimecnt : 32;
} RW_BLE_FINETIMECNT_b;
};
/* Address 0x024 */
union {
__IO uint32_t RW_BLE_BDADDRL;
struct {
__IO uint32_t rw_ble_bdaddrl : 32;
} RW_BLE_BDADDRL_b;
};
/* Address 0x028 */
union {
__IO uint32_t RW_BLE_BDADDRU;
struct {
__IO uint32_t rw_ble_bdaddru : 32;
} RW_BLE_BDADDRU_b;
};
/* Address 0x02C */
union {
__IO uint32_t RW_BLE_ET_CURRENTRXDESCPTR;
struct {
__IO uint32_t rw_ble_et_currentrxdescptr : 32;
} RW_BLE_ET_CURRENTRXDESCPTR_b;
};
/* Address 0x030 */
union {
__IO uint32_t RW_BLE_DEEPSLCNTL;
struct {
__IO uint32_t rw_ble_deepslcntl : 32;
} RW_BLE_DEEPSLCNTL_b;
};
/* Address 0x034 */
union {
__IO uint32_t RW_BLE_DEEPSLWKUP;
struct {
__IO uint32_t rw_ble_deepslwkup : 32;
} RW_BLE_DEEPSLWKUP_b;
};
/* Address 0x038 */
union {
__IO uint32_t RW_BLE_DEEPSLSTAT;
struct {
__IO uint32_t rw_ble_deepslstat : 32;
} RW_BLE_DEEPSLSTAT_b;
};
/* Address 0x03C */
union {
__IO uint32_t RW_BLE_ENBPRESET;
struct {
__IO uint32_t rw_ble_enbpreset : 32;
} RW_BLE_ENBPRESET_b;
};
/* Address 0x040 */
union {
__IO uint32_t RW_BLE_FINECNTCORR;
struct {
__IO uint32_t rw_ble_finecntcorr : 32;
} RW_BLE_FINECNTCORR_b;
};
/* Address 0x044 */
union {
__IO uint32_t RW_BLE_BASETIMECNTCORR;
struct {
__IO uint32_t rw_ble_basetimecntcorr : 32;
} RW_BLE_BASETIMECNTCORR_b;
};
/* Addresses 0x048 - 0x04C */
__O uint32_t RESERVED048[2];
/* Address 0x050 */
union {
__IO uint32_t RW_BLE_DIAGCNTL;
struct {
__IO uint32_t rw_ble_diagcntl : 32;
} RW_BLE_DIAGCNTL_b;
};
/* Address 0x054 */
union {
__IO uint32_t RW_BLE_DIAGSTAT;
struct {
__IO uint32_t rw_ble_diagstat : 32;
} RW_BLE_DIAGSTAT_b;
};
/* Address 0x058 */
union {
__IO uint32_t RW_BLE_DEBUGADDMAX;
struct {
__IO uint32_t rw_ble_debugaddmax : 32;
} RW_BLE_DEBUGADDMAX_b;
};
/* Address 0x05C */
union {
__IO uint32_t RW_BLE_DEBUGADDMIN;
struct {
__IO uint32_t rw_ble_debugaddmin : 32;
} RW_BLE_DEBUGADDMIN_b;
};
/* Address 0x060 */
union {
__IO uint32_t RW_BLE_ERRORTYPESTAT;
struct {
__IO uint32_t rw_ble_errortypestat : 32;
} RW_BLE_ERRORTYPESTAT_b;
};
/* Address 0x064 */
union {
__IO uint32_t RW_BLE_SWPROFILING;
struct {
__IO uint32_t rw_ble_swprofiling : 32;
} RW_BLE_SWPROFILING_b;
};
/* Addresses 0x068 - 0x06C */
__O uint32_t RESERVED068[2];
/* Address 0x070 */
union {
__IO uint32_t RW_BLE_RADIOCNTL0;
struct {
__IO uint32_t rw_ble_radiocntl0 : 32;
} RW_BLE_RADIOCNTL0_b;
};
/* Address 0x074 */
union {
__IO uint32_t RW_BLE_RADIOCNTL1;
struct {
__IO uint32_t rw_ble_radiocntl1 : 32;
} RW_BLE_RADIOCNTL1_b;
};
/* Address 0x078 */
union {
__IO uint32_t RW_BLE_RADIOCNTL2;
struct {
__IO uint32_t rw_ble_radiocntl2 : 32;
} RW_BLE_RADIOCNTL2_b;
};
/* Address 0x07C */
union {
__IO uint32_t RW_BLE_RADIOCNTL3;
struct {
__IO uint32_t rw_ble_radiocntl3 : 32;
} RW_BLE_RADIOCNTL3_b;
};
/* Address 0x080 */
union {
__IO uint32_t RW_BLE_RADIOPWRUPDN;
struct {
__IO uint32_t rw_ble_radiopwrupdn : 32;
} RW_BLE_RADIOPWRUPDN_b;
};
/* Address 0x084 */
union {
__IO uint32_t RW_BLE_SPIPTRCNTL0;
struct {
__IO uint32_t rw_ble_spiptrcntl0 : 32;
} RW_BLE_SPIPTRCNTL0_b;
};
/* Address 0x088 */
union {
__IO uint32_t RW_BLE_SPIPTRCNTL1;
struct {
__IO uint32_t rw_ble_spiptrcntl1 : 32;
} RW_BLE_SPIPTRCNTL1_b;
};
/* Address 0x08C */
union {
__IO uint32_t RW_BLE_SPIPTRCNTL2;
struct {
__IO uint32_t rw_ble_spiptrcntl2 : 32;
} RW_BLE_SPIPTRCNTL2_b;
};
/* Address 0x090 */
union {
__IO uint32_t RW_BLE_ADVCHMAP;
struct {
__IO uint32_t rw_ble_advchmap : 32;
} RW_BLE_ADVCHMAP_b;
};
/* Addresses 0x094 - 0x09C */
__O uint32_t RESERVED094[3];
/* Address 0x0A0 */
union {
__IO uint32_t RW_BLE_ADVTIM;
struct {
__IO uint32_t rw_ble_advtim : 32;
} RW_BLE_ADVTIM_b;
};
/* Address 0x0A4 */
union {
__IO uint32_t RW_BLE_ACTSCANSTAT;
struct {
__IO uint32_t rw_ble_actscanstat : 32;
} RW_BLE_ACTSCANSTAT_b;
};
/* Addresses 0x0A8 - 0x0AC */
__O uint32_t RESERVED0A8[2];
/* Address 0x0B0 */
union {
__IO uint32_t RW_BLE_WLPUBADDPTR;
struct {
__IO uint32_t rw_ble_wlpubaddptr : 32;
} RW_BLE_WLPUBADDPTR_b;
};
/* Address 0x0B4 */
union {
__IO uint32_t RW_BLE_WLPRIVADDPTR;
struct {
__IO uint32_t rw_ble_wlprivaddptr : 32;
} RW_BLE_WLPRIVADDPTR_b;
};
/* Address 0x0B8 */
union {
__IO uint32_t RW_BLE_WLNBDEV;
struct {
__IO uint32_t rw_ble_wlnbdev : 32;
} RW_BLE_WLNBDEV_b;
};
/* Address 0x0BC */
__O uint32_t RESERVED0BC[1];
/* Address 0x0C0 */
union {
__IO uint32_t RW_BLE_AESCNTL;
struct {
__IO uint32_t rw_ble_aescntl : 32;
} RW_BLE_AESCNTL_b;
};
/* Address 0x0C4 */
union {
__IO uint32_t RW_BLE_AESKEY31_0;
struct {
__IO uint32_t rw_ble_aeskey31_0 : 32;
} RW_BLE_AESKEY31_0_b;
};
/* Address 0x0C8 */
union {
__IO uint32_t RW_BLE_AESKEY63_32;
struct {
__IO uint32_t rw_ble_aeskey63_32 : 32;
} RW_BLE_AESKEY63_32_b;
};
/* Address 0x0CC */
union {
__IO uint32_t RW_BLE_AESKEY95_64;
struct {
__IO uint32_t rw_ble_aeskey95_64 : 32;
} RW_BLE_AESKEY95_64_b;
};
/* Address 0x0D0 */
union {
__IO uint32_t RW_BLE_AESKEY127_96;
struct {
__IO uint32_t rw_ble_aeskey127_96 : 32;
} RW_BLE_AESKEY127_96_b;
};
/* Address 0x0D4 */
union {
__IO uint32_t RW_BLE_AESPTR;
struct {
__IO uint32_t rw_ble_aesptr : 32;
} RW_BLE_AESPTR_b;
};
/* Address 0x0D8 */
union {
__IO uint32_t RW_BLE_TXMICVAL;
struct {
__IO uint32_t rw_ble_txmicval : 32;
} RW_BLE_TXMICVAL_b;
};
/* Address 0x0DC */
union {
__IO uint32_t RW_BLE_RXMICVAL;
struct {
__IO uint32_t rw_ble_rxmicval : 32;
} RW_BLE_RXMICVAL_b;
};
/* Address 0x0E0 */
union {
__IO uint32_t RW_BLE_RFTESTCNTL;
struct {
__IO uint32_t rw_ble_rftestcntl : 32;
} RW_BLE_RFTESTCNTL_b;
};
/* Address 0x0E4 */
union {
__IO uint32_t RW_BLE_RFTESTTXSTAT;
struct {
__IO uint32_t rw_ble_rftesttxstat : 32;
} RW_BLE_RFTESTTXSTAT_b;
};
/* Address 0x0E8 */
union {
__IO uint32_t RW_BLE_RFTESTRXSTAT;
struct {
__IO uint32_t rw_ble_rftestrxstat : 32;
} RW_BLE_RFTESTRXSTAT_b;
};
/* Address 0x0EC */
__O uint32_t RESERVED0EC[1];
/* Address 0x0F0 */
union {
__IO uint32_t RW_BLE_TIMGENCNTL;
struct {
__IO uint32_t rw_ble_timgencntl : 32;
} RW_BLE_TIMGENCNTL_b;
};
/* Address 0x0F4 */
union {
__IO uint32_t RW_BLE_GROSSTIMTGT;
struct {
__IO uint32_t rw_ble_grosstimtgt : 32;
} RW_BLE_GROSSTIMTGT_b;
};
/* Address 0x0F8 */
union {
__IO uint32_t RW_BLE_FINETIMTGT;
struct {
__IO uint32_t rw_ble_finetimtgt : 32;
} RW_BLE_FINETIMTGT_b;
};
/* Address 0x0FC */
__O uint32_t RESERVED0FC[1];
/* Address 0x100 */
union {
__IO uint32_t RW_BLE_COEXIFCNTL0;
struct {
__IO uint32_t rw_ble_coexifcntl0 : 32;
} RW_BLE_COEXIFCNTL0_b;
};
/* Address 0x104 */
union {
__IO uint32_t RW_BLE_COEXIFCNTL1;
struct {
__IO uint32_t rw_ble_coexifcntl1 : 32;
} RW_BLE_COEXIFCNTL1_b;
};
/* Address 0x108 */
union {
__IO uint32_t RW_BLE_COEXIFCNTL2;
struct {
__IO uint32_t rw_ble_coexifcntl2 : 32;
} RW_BLE_COEXIFCNTL2_b;
};
/* Address 0x10C */
union {
__IO uint32_t RW_BLE_BLEMPRIO0;
struct {
__IO uint32_t rw_ble_blemprio0 : 32;
} RW_BLE_BLEMPRIO0_b;
};
/* Address 0x110 */
union {
__IO uint32_t RW_BLE_BLEMPRIO1;
struct {
__IO uint32_t rw_ble_blemprio1 : 32;
} RW_BLE_BLEMPRIO1_b;
};
/* Addresses 0x114 - 0x11C */
__O uint32_t RESERVED114[3];
/* Address 0x120 */
union {
__IO uint32_t RW_BLE_RALPTR;
struct {
__IO uint32_t rw_ble_ralptr : 32;
} RW_BLE_RALPTR_b;
};
/* Address 0x124 */
union {
__IO uint32_t RW_BLE_RALNBDEV;
struct {
__IO uint32_t rw_ble_ralnbdev : 32;
} RW_BLE_RALNBDEV_b;
};
/* Address 0x128 */
union {
__IO uint32_t RW_BLE_RAL_LOCAL_RND;
struct {
__IO uint32_t rw_ble_ral_local_rnd : 32;
} RW_BLE_RAL_LOCAL_RND_b;
};
/* Address 0x12C */
union {
__IO uint32_t RW_BLE_RAL_PEER_RND;
struct {
__IO uint32_t rw_ble_ral_peer_rnd : 32;
} RW_BLE_RAL_PEER_RND_b;
};
/* Address 0x130 */
union {
__IO uint32_t RW_BLE_ISOCHANCNTL0;
struct {
__IO uint32_t rw_ble_isochancntl0 : 32;
} RW_BLE_ISOCHANCNTL0_b;
};
/* Address 0x134 */
union {
__IO uint32_t RW_BLE_ISOMUTECNTL0;
struct {
__IO uint32_t rw_ble_isomutecntl0 : 32;
} RW_BLE_ISOMUTECNTL0_b;
};
/* Address 0x138 */
union {
__IO uint32_t RW_BLE_ISOCURRENTTXPTR0;
struct {
__IO uint32_t rw_ble_isocurrenttxptr0 : 32;
} RW_BLE_ISOCURRENTTXPTR0_b;
};
/* Address 0x13C */
union {
__IO uint32_t RW_BLE_ISOCURRENTRXPTR0;
struct {
__IO uint32_t rw_ble_isocurrentrxptr0 : 32;
} RW_BLE_ISOCURRENTRXPTR0_b;
};
/* Address 0x140 */
union {
__IO uint32_t RW_BLE_ISOTRCNL0;
struct {
__IO uint32_t rw_ble_isotrcnl0 : 32;
} RW_BLE_ISOTRCNL0_b;
};
/* Address 0x144 */
union {
__IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL0;
struct {
__IO uint32_t rw_ble_isoevtcntloffsetl0 : 32;
} RW_BLE_ISOEVTCNTLOFFSETL0_b;
};
/* Address 0x148 */
union {
__IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU0;
struct {
__IO uint32_t rw_ble_isoevtcntloffsetu0 : 32;
} RW_BLE_ISOEVTCNTLOFFSETU0_b;
};
/* Address 0x14C */
__O uint32_t RESERVED14C[1];
/* Address 0x150 */
union {
__IO uint32_t RW_BLE_ISOCHANCNTL1;
struct {
__IO uint32_t rw_ble_isochancntl1 : 32;
} RW_BLE_ISOCHANCNTL1_b;
};
/* Address 0x154 */
union {
__IO uint32_t RW_BLE_ISOMUTECNTL1;
struct {
__IO uint32_t rw_ble_isomutecntl1 : 32;
} RW_BLE_ISOMUTECNTL1_b;
};
/* Address 0x158 */
union {
__IO uint32_t RW_BLE_ISOCURRENTTXPTR1;
struct {
__IO uint32_t rw_ble_isocurrenttxptr1 : 32;
} RW_BLE_ISOCURRENTTXPTR1_b;
};
/* Address 0x15C */
union {
__IO uint32_t RW_BLE_ISOCURRENTRXPTR1;
struct {
__IO uint32_t rw_ble_isocurrentrxptr1 : 32;
} RW_BLE_ISOCURRENTRXPTR1_b;
};
/* Address 0x160 */
union {
__IO uint32_t RW_BLE_ISOTRCNL1;
struct {
__IO uint32_t rw_ble_isotrcnl1 : 32;
} RW_BLE_ISOTRCNL1_b;
};
/* Address 0x164 */
union {
__IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL1;
struct {
__IO uint32_t rw_ble_isoevtcntloffsetl1 : 32;
} RW_BLE_ISOEVTCNTLOFFSETL1_b;
};
/* Address 0x168 */
union {
__IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU1;
struct {
__IO uint32_t rw_ble_isoevtcntloffsetu1 : 32;
} RW_BLE_ISOEVTCNTLOFFSETU1_b;
};
/* Address 0x16C */
__O uint32_t RESERVED16C[1];
/* Address 0x170 */
union {
__IO uint32_t RW_BLE_ISOCHANCNTL2;
struct {
__IO uint32_t rw_ble_isochancntl2 : 32;
} RW_BLE_ISOCHANCNTL2_b;
};
/* Address 0x174 */
union {
__IO uint32_t RW_BLE_ISOMUTECNTL2;
struct {
__IO uint32_t rw_ble_isomutecntl2 : 32;
} RW_BLE_ISOMUTECNTL2_b;
};
/* Address 0x178 */
union {
__IO uint32_t RW_BLE_ISOCURRENTTXPTR2;
struct {
__IO uint32_t rw_ble_isocurrenttxptr2 : 32;
} RW_BLE_ISOCURRENTTXPTR2_b;
};
/* Address 0x17C */
union {
__IO uint32_t RW_BLE_ISOCURRENTRXPTR2;
struct {
__IO uint32_t rw_ble_isocurrentrxptr2 : 32;
} RW_BLE_ISOCURRENTRXPTR2_b;
};
/* Address 0x180 */
union {
__IO uint32_t RW_BLE_ISOTRCNL2;
struct {
__IO uint32_t rw_ble_isotrcnl2 : 32;
} RW_BLE_ISOTRCNL2_b;
};
/* Address 0x184 */
union {
__IO uint32_t RW_BLE_ISOEVTCNTLOFFSETL2;
struct {
__IO uint32_t rw_ble_isoevtcntloffsetl2 : 32;
} RW_BLE_ISOEVTCNTLOFFSETL2_b;
};
/* Address 0x188 */
union {
__IO uint32_t RW_BLE_ISOEVTCNTLOFFSETU2;
struct {
__IO uint32_t rw_ble_isoevtcntloffsetu2 : 32;
} RW_BLE_ISOEVTCNTLOFFSETU2_b;
};
/* Address 0x18C */
__O uint32_t RESERVED18C[1];
/* Address 0x190 */
union {
__IO uint32_t RW_BLE_BLEPRIOSCHARB;
struct {
__IO uint32_t rw_ble_bleprioscharb : 32;
} RW_BLE_BLEPRIOSCHARB_b;
};
/* Addresses 0x194 - 0xFF0 */
__O uint32_t RESERVED194[920];
} BLE_LINK_IF_Type;
#define BLELNK_RW_BLE_RWBLECNTL_RW_BLE_RWBLECNTL_Pos 0
#define BLELNK_RW_BLE_RWBLECNTL_RW_BLE_RWBLECNTL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_VERSION_RW_BLE_VERSION_Pos 0
#define BLELNK_RW_BLE_VERSION_RW_BLE_VERSION_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RWBLECONF_RW_BLE_RWBLECONF_Pos 0
#define BLELNK_RW_BLE_RWBLECONF_RW_BLE_RWBLECONF_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_INTCNTL_RW_BLE_INTCNTL_Pos 0
#define BLELNK_RW_BLE_INTCNTL_RW_BLE_INTCNTL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_INTSTAT_RW_BLE_INTSTAT_Pos 0
#define BLELNK_RW_BLE_INTSTAT_RW_BLE_INTSTAT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_INTRAWSTAT_RW_BLE_INTRAWSTAT_Pos 0
#define BLELNK_RW_BLE_INTRAWSTAT_RW_BLE_INTRAWSTAT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_INTACK_RW_BLE_INTACK_Pos 0
#define BLELNK_RW_BLE_INTACK_RW_BLE_INTACK_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_BASETIMECNT_RW_BLE_BASETIMECNT_Pos 0
#define BLELNK_RW_BLE_BASETIMECNT_RW_BLE_BASETIMECNT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_FINETIMECNT_RW_BLE_FINETIMECNT_Pos 0
#define BLELNK_RW_BLE_FINETIMECNT_RW_BLE_FINETIMECNT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_BDADDRL_RW_BLE_BDADDRL_Pos 0
#define BLELNK_RW_BLE_BDADDRL_RW_BLE_BDADDRL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_BDADDRU_RW_BLE_BDADDRU_Pos 0
#define BLELNK_RW_BLE_BDADDRU_RW_BLE_BDADDRU_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ET_CURRENTRXDESCPTR_RW_BLE_ET_CURRENTRXDESCPTR_Pos 0
#define BLELNK_RW_BLE_ET_CURRENTRXDESCPTR_RW_BLE_ET_CURRENTRXDESCPTR_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_DEEPSLCNTL_RW_BLE_DEEPSLCNTL_Pos 0
#define BLELNK_RW_BLE_DEEPSLCNTL_RW_BLE_DEEPSLCNTL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_DEEPSLWKUP_RW_BLE_DEEPSLWKUP_Pos 0
#define BLELNK_RW_BLE_DEEPSLWKUP_RW_BLE_DEEPSLWKUP_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_DEEPSLSTAT_RW_BLE_DEEPSLSTAT_Pos 0
#define BLELNK_RW_BLE_DEEPSLSTAT_RW_BLE_DEEPSLSTAT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ENBPRESET_RW_BLE_ENBPRESET_Pos 0
#define BLELNK_RW_BLE_ENBPRESET_RW_BLE_ENBPRESET_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_FINECNTCORR_RW_BLE_FINECNTCORR_Pos 0
#define BLELNK_RW_BLE_FINECNTCORR_RW_BLE_FINECNTCORR_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_BASETIMECNTCORR_RW_BLE_BASETIMECNTCORR_Pos 0
#define BLELNK_RW_BLE_BASETIMECNTCORR_RW_BLE_BASETIMECNTCORR_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_DIAGCNTL_RW_BLE_DIAGCNTL_Pos 0
#define BLELNK_RW_BLE_DIAGCNTL_RW_BLE_DIAGCNTL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_DIAGSTAT_RW_BLE_DIAGSTAT_Pos 0
#define BLELNK_RW_BLE_DIAGSTAT_RW_BLE_DIAGSTAT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_DEBUGADDMAX_RW_BLE_DEBUGADDMAX_Pos 0
#define BLELNK_RW_BLE_DEBUGADDMAX_RW_BLE_DEBUGADDMAX_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_DEBUGADDMIN_RW_BLE_DEBUGADDMIN_Pos 0
#define BLELNK_RW_BLE_DEBUGADDMIN_RW_BLE_DEBUGADDMIN_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ERRORTYPESTAT_RW_BLE_ERRORTYPESTAT_Pos 0
#define BLELNK_RW_BLE_ERRORTYPESTAT_RW_BLE_ERRORTYPESTAT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_SWPROFILING_RW_BLE_SWPROFILING_Pos 0
#define BLELNK_RW_BLE_SWPROFILING_RW_BLE_SWPROFILING_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RADIOCNTL0_RW_BLE_RADIOCNTL0_Pos 0
#define BLELNK_RW_BLE_RADIOCNTL0_RW_BLE_RADIOCNTL0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RADIOCNTL1_RW_BLE_RADIOCNTL1_Pos 0
#define BLELNK_RW_BLE_RADIOCNTL1_RW_BLE_RADIOCNTL1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RADIOCNTL2_RW_BLE_RADIOCNTL2_Pos 0
#define BLELNK_RW_BLE_RADIOCNTL2_RW_BLE_RADIOCNTL2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RADIOCNTL3_RW_BLE_RADIOCNTL3_Pos 0
#define BLELNK_RW_BLE_RADIOCNTL3_RW_BLE_RADIOCNTL3_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RADIOPWRUPDN_RW_BLE_RADIOPWRUPDN_Pos 0
#define BLELNK_RW_BLE_RADIOPWRUPDN_RW_BLE_RADIOPWRUPDN_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_SPIPTRCNTL0_RW_BLE_SPIPTRCNTL0_Pos 0
#define BLELNK_RW_BLE_SPIPTRCNTL0_RW_BLE_SPIPTRCNTL0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_SPIPTRCNTL1_RW_BLE_SPIPTRCNTL1_Pos 0
#define BLELNK_RW_BLE_SPIPTRCNTL1_RW_BLE_SPIPTRCNTL1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_SPIPTRCNTL2_RW_BLE_SPIPTRCNTL2_Pos 0
#define BLELNK_RW_BLE_SPIPTRCNTL2_RW_BLE_SPIPTRCNTL2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ADVCHMAP_RW_BLE_ADVCHMAP_Pos 0
#define BLELNK_RW_BLE_ADVCHMAP_RW_BLE_ADVCHMAP_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ADVTIM_RW_BLE_ADVTIM_Pos 0
#define BLELNK_RW_BLE_ADVTIM_RW_BLE_ADVTIM_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ACTSCANSTAT_RW_BLE_ACTSCANSTAT_Pos 0
#define BLELNK_RW_BLE_ACTSCANSTAT_RW_BLE_ACTSCANSTAT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_WLPUBADDPTR_RW_BLE_WLPUBADDPTR_Pos 0
#define BLELNK_RW_BLE_WLPUBADDPTR_RW_BLE_WLPUBADDPTR_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_WLPRIVADDPTR_RW_BLE_WLPRIVADDPTR_Pos 0
#define BLELNK_RW_BLE_WLPRIVADDPTR_RW_BLE_WLPRIVADDPTR_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_WLNBDEV_RW_BLE_WLNBDEV_Pos 0
#define BLELNK_RW_BLE_WLNBDEV_RW_BLE_WLNBDEV_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_AESCNTL_RW_BLE_AESCNTL_Pos 0
#define BLELNK_RW_BLE_AESCNTL_RW_BLE_AESCNTL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_AESKEY31_0_RW_BLE_AESKEY31_0_Pos 0
#define BLELNK_RW_BLE_AESKEY31_0_RW_BLE_AESKEY31_0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_AESKEY63_32_RW_BLE_AESKEY63_32_Pos 0
#define BLELNK_RW_BLE_AESKEY63_32_RW_BLE_AESKEY63_32_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_AESKEY95_64_RW_BLE_AESKEY95_64_Pos 0
#define BLELNK_RW_BLE_AESKEY95_64_RW_BLE_AESKEY95_64_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_AESKEY127_96_RW_BLE_AESKEY127_96_Pos 0
#define BLELNK_RW_BLE_AESKEY127_96_RW_BLE_AESKEY127_96_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_AESPTR_RW_BLE_AESPTR_Pos 0
#define BLELNK_RW_BLE_AESPTR_RW_BLE_AESPTR_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_TXMICVAL_RW_BLE_TXMICVAL_Pos 0
#define BLELNK_RW_BLE_TXMICVAL_RW_BLE_TXMICVAL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RXMICVAL_RW_BLE_RXMICVAL_Pos 0
#define BLELNK_RW_BLE_RXMICVAL_RW_BLE_RXMICVAL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RFTESTCNTL_RW_BLE_RFTESTCNTL_Pos 0
#define BLELNK_RW_BLE_RFTESTCNTL_RW_BLE_RFTESTCNTL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RFTESTTXSTAT_RW_BLE_RFTESTTXSTAT_Pos 0
#define BLELNK_RW_BLE_RFTESTTXSTAT_RW_BLE_RFTESTTXSTAT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RFTESTRXSTAT_RW_BLE_RFTESTRXSTAT_Pos 0
#define BLELNK_RW_BLE_RFTESTRXSTAT_RW_BLE_RFTESTRXSTAT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_TIMGENCNTL_RW_BLE_TIMGENCNTL_Pos 0
#define BLELNK_RW_BLE_TIMGENCNTL_RW_BLE_TIMGENCNTL_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_GROSSTIMTGT_RW_BLE_GROSSTIMTGT_Pos 0
#define BLELNK_RW_BLE_GROSSTIMTGT_RW_BLE_GROSSTIMTGT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_FINETIMTGT_RW_BLE_FINETIMTGT_Pos 0
#define BLELNK_RW_BLE_FINETIMTGT_RW_BLE_FINETIMTGT_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_COEXIFCNTL0_RW_BLE_COEXIFCNTL0_Pos 0
#define BLELNK_RW_BLE_COEXIFCNTL0_RW_BLE_COEXIFCNTL0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_COEXIFCNTL1_RW_BLE_COEXIFCNTL1_Pos 0
#define BLELNK_RW_BLE_COEXIFCNTL1_RW_BLE_COEXIFCNTL1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_COEXIFCNTL2_RW_BLE_COEXIFCNTL2_Pos 0
#define BLELNK_RW_BLE_COEXIFCNTL2_RW_BLE_COEXIFCNTL2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_BLEMPRIO0_RW_BLE_BLEMPRIO0_Pos 0
#define BLELNK_RW_BLE_BLEMPRIO0_RW_BLE_BLEMPRIO0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_BLEMPRIO1_RW_BLE_BLEMPRIO1_Pos 0
#define BLELNK_RW_BLE_BLEMPRIO1_RW_BLE_BLEMPRIO1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RALPTR_RW_BLE_RALPTR_Pos 0
#define BLELNK_RW_BLE_RALPTR_RW_BLE_RALPTR_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RALNBDEV_RW_BLE_RALNBDEV_Pos 0
#define BLELNK_RW_BLE_RALNBDEV_RW_BLE_RALNBDEV_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RAL_LOCAL_RND_RW_BLE_RAL_LOCAL_RND_Pos 0
#define BLELNK_RW_BLE_RAL_LOCAL_RND_RW_BLE_RAL_LOCAL_RND_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_RAL_PEER_RND_RW_BLE_RAL_PEER_RND_Pos 0
#define BLELNK_RW_BLE_RAL_PEER_RND_RW_BLE_RAL_PEER_RND_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCHANCNTL0_RW_BLE_ISOCHANCNTL0_Pos 0
#define BLELNK_RW_BLE_ISOCHANCNTL0_RW_BLE_ISOCHANCNTL0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOMUTECNTL0_RW_BLE_ISOMUTECNTL0_Pos 0
#define BLELNK_RW_BLE_ISOMUTECNTL0_RW_BLE_ISOMUTECNTL0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCURRENTTXPTR0_RW_BLE_ISOCURRENTTXPTR0_Pos 0
#define BLELNK_RW_BLE_ISOCURRENTTXPTR0_RW_BLE_ISOCURRENTTXPTR0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCURRENTRXPTR0_RW_BLE_ISOCURRENTRXPTR0_Pos 0
#define BLELNK_RW_BLE_ISOCURRENTRXPTR0_RW_BLE_ISOCURRENTRXPTR0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOTRCNL0_RW_BLE_ISOTRCNL0_Pos 0
#define BLELNK_RW_BLE_ISOTRCNL0_RW_BLE_ISOTRCNL0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL0_RW_BLE_ISOEVTCNTLOFFSETL0_Pos 0
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL0_RW_BLE_ISOEVTCNTLOFFSETL0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU0_RW_BLE_ISOEVTCNTLOFFSETU0_Pos 0
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU0_RW_BLE_ISOEVTCNTLOFFSETU0_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCHANCNTL1_RW_BLE_ISOCHANCNTL1_Pos 0
#define BLELNK_RW_BLE_ISOCHANCNTL1_RW_BLE_ISOCHANCNTL1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOMUTECNTL1_RW_BLE_ISOMUTECNTL1_Pos 0
#define BLELNK_RW_BLE_ISOMUTECNTL1_RW_BLE_ISOMUTECNTL1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCURRENTTXPTR1_RW_BLE_ISOCURRENTTXPTR1_Pos 0
#define BLELNK_RW_BLE_ISOCURRENTTXPTR1_RW_BLE_ISOCURRENTTXPTR1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCURRENTRXPTR1_RW_BLE_ISOCURRENTRXPTR1_Pos 0
#define BLELNK_RW_BLE_ISOCURRENTRXPTR1_RW_BLE_ISOCURRENTRXPTR1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOTRCNL1_RW_BLE_ISOTRCNL1_Pos 0
#define BLELNK_RW_BLE_ISOTRCNL1_RW_BLE_ISOTRCNL1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL1_RW_BLE_ISOEVTCNTLOFFSETL1_Pos 0
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL1_RW_BLE_ISOEVTCNTLOFFSETL1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU1_RW_BLE_ISOEVTCNTLOFFSETU1_Pos 0
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU1_RW_BLE_ISOEVTCNTLOFFSETU1_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCHANCNTL2_RW_BLE_ISOCHANCNTL2_Pos 0
#define BLELNK_RW_BLE_ISOCHANCNTL2_RW_BLE_ISOCHANCNTL2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOMUTECNTL2_RW_BLE_ISOMUTECNTL2_Pos 0
#define BLELNK_RW_BLE_ISOMUTECNTL2_RW_BLE_ISOMUTECNTL2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCURRENTTXPTR2_RW_BLE_ISOCURRENTTXPTR2_Pos 0
#define BLELNK_RW_BLE_ISOCURRENTTXPTR2_RW_BLE_ISOCURRENTTXPTR2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOCURRENTRXPTR2_RW_BLE_ISOCURRENTRXPTR2_Pos 0
#define BLELNK_RW_BLE_ISOCURRENTRXPTR2_RW_BLE_ISOCURRENTRXPTR2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOTRCNL2_RW_BLE_ISOTRCNL2_Pos 0
#define BLELNK_RW_BLE_ISOTRCNL2_RW_BLE_ISOTRCNL2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL2_RW_BLE_ISOEVTCNTLOFFSETL2_Pos 0
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETL2_RW_BLE_ISOEVTCNTLOFFSETL2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU2_RW_BLE_ISOEVTCNTLOFFSETU2_Pos 0
#define BLELNK_RW_BLE_ISOEVTCNTLOFFSETU2_RW_BLE_ISOEVTCNTLOFFSETU2_Msk 0x0ffffffffUL
#define BLELNK_RW_BLE_BLEPRIOSCHARB_RW_BLE_BLEPRIOSCHARB_Pos 0
#define BLELNK_RW_BLE_BLEPRIOSCHARB_RW_BLE_BLEPRIOSCHARB_Msk 0x0ffffffffUL
#endif // __BLE_LINK_IF_H__
third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_rfp_modem.h
Vendored
-21556
View File
File diff suppressed because it is too large Load Diff
third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_mac.h
Vendored
-930
View File
@@ -1,930 +0,0 @@
/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __ZB_MAC_IF_H__
#define __ZB_MAC_IF_H__
typedef struct {
/* Address 0x000 */
union {
__IO uint32_t SCMR0;
struct {
__IO uint32_t scmr0 : 32;
} SCMR0_b;
};
/* Address 0x004 */
union {
__IO uint32_t SCMR1;
struct {
__IO uint32_t scmr1 : 32;
} SCMR1_b;
};
/* Address 0x008 */
union {
__IO uint32_t SCMR2;
struct {
__IO uint32_t scmr2 : 32;
} SCMR2_b;
};
/* Address 0x00C */
union {
__IO uint32_t SCMR3;
struct {
__IO uint32_t scmr3 : 32;
} SCMR3_b;
};
/* Address 0x010 */
union {
__IO uint32_t SCTR0;
struct {
__IO uint32_t sctr0 : 32;
} SCTR0_b;
};
/* Address 0x014 */
union {
__IO uint32_t SCTR1;
struct {
__IO uint32_t sctr1 : 32;
} SCTR1_b;
};
/* Addresses 0x018 - 0x01C */
__O uint32_t RESERVED018[2];
/* Address 0x020 */
union {
__IO uint32_t SCTCR;
struct {
__IO uint32_t sctcr : 2;
__IO uint32_t reserved2 : 30;
} SCTCR_b;
};
/* Address 0x024 */
union {
__IO uint32_t SCFRC;
struct {
__IO uint32_t scfrc : 32;
} SCFRC_b;
};
/* Address 0x028 */
union {
__I uint32_t SCSSR;
struct {
__I uint32_t scssr : 32;
} SCSSR_b;
};
/* Address 0x02C */
union {
__IO uint32_t SCESL;
struct {
__IO uint32_t scesl : 32;
} SCESL_b;
};
/* Address 0x030 */
union {
__IO uint32_t RXETST;
struct {
__IO uint32_t rxetst : 32;
} RXETST_b;
};
/* Address 0x034 */
union {
__I uint32_t RXTSTP;
struct {
__I uint32_t rxtstp : 32;
} RXTSTP_b;
};
/* Address 0x038 */
union {
__IO uint32_t TXTSTP;
struct {
__IO uint32_t txtstp : 32;
} TXTSTP_b;
};
/* Address 0x03C */
union {
__IO uint32_t IER;
struct {
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
__IO uint32_t ier : 10;
__IO uint32_t reserved10 : 22;
#else
__IO uint32_t ier : 12;
__IO uint32_t reserved12 : 20;
#endif
} IER_b;
};
/* Address 0x040 */
union {
__IO uint32_t ISR;
struct {
__IO uint32_t txint : 1;
__IO uint32_t headerrxint : 1;
__IO uint32_t rxint : 1;
__IO uint32_t unused_3_3 : 1;
__IO uint32_t match : 4;
__IO uint32_t timeout : 2;
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
__IO uint32_t reserved10 : 22;
#else
__IO uint32_t rxaddnomatch : 1;
__IO uint32_t rxaddmatch : 1;
__IO uint32_t reserved12 : 20;
#endif
} ISR_b;
};
/* Address 0x044 */
union {
__IO uint32_t SCTL;
struct {
__IO uint32_t sctl : 7;
__IO uint32_t reserved7 : 25;
} SCTL_b;
};
/* Address 0x048 */
union {
__IO uint32_t PHYTXTUNETIME;
struct {
__IO uint32_t phytxtunetime : 8;
__IO uint32_t phyrx2txtime : 8;
__IO uint32_t reserved16 : 16;
} PHYTXTUNETIME_b;
};
/* Address 0x04C */
union {
__IO uint32_t PHYRXTUNETIME;
struct {
__IO uint32_t phyrxtunetime : 8;
__IO uint32_t reserved8 : 24;
} PHYRXTUNETIME_b;
};
/* Address 0x050 */
__O uint32_t RESERVED050[1];
/* Address 0x054 */
union {
__IO uint32_t TURNAROUNDTIME;
struct {
__IO uint32_t turnaroundtime : 8;
__IO uint32_t reserved8 : 24;
} TURNAROUNDTIME_b;
};
/* Address 0x058 */
union {
__IO uint32_t BACKOFFTIME;
struct {
__IO uint32_t backofftime : 8;
__IO uint32_t reserved8 : 24;
} BACKOFFTIME_b;
};
/* Addresses 0x05C - 0x06C */
__O uint32_t RESERVED05C[5];
/* Address 0x070 */
union {
__IO uint32_t PRBS_SEED;
struct {
__IO uint32_t prbs_seed : 15;
__IO uint32_t reserved15 : 17;
} PRBS_SEED_b;
};
/* Addresses 0x074 - 0x078 */
__O uint32_t RESERVED074[2];
/* Address 0x07C */
union {
__IO uint32_t SM_STATE;
struct {
__IO uint32_t sm_state : 7;
__IO uint32_t reserved7 : 25;
} SM_STATE_b;
};
/* Address 0x080 */
union {
__IO uint32_t LIFSTURNAROUNDTIME;
struct {
__IO uint32_t lifsturnaroundtime : 8;
__IO uint32_t reserved8 : 24;
} LIFSTURNAROUNDTIME_b;
};
/* Address 0x084 */
union {
__IO uint32_t HDR_CTRL;
struct {
__IO uint32_t hdr_ctrl : 2;
__IO uint32_t reserved2 : 30;
} HDR_CTRL_b;
};
/* Address 0x088 */
union {
__IO uint32_t MISR;
struct {
__IO uint32_t misr : 10;
__IO uint32_t reserved10 : 22;
} MISR_b;
};
/* Addresses 0x08C - 0x0F8 */
__O uint32_t RESERVED08C[28];
/* Address 0x0FC */
union {
__I uint32_t IDENTIFIER;
struct {
__I uint32_t identifier : 32;
} IDENTIFIER_b;
};
/* Addresses 0x100 - 0x1BC */
__O uint32_t RESERVED100[48];
/* Address 0x1C0 */
union {
__IO uint32_t TXCTL;
struct {
__IO uint32_t sch : 1;
__IO uint32_t ss : 1;
__IO uint32_t slotack : 1;
__IO uint32_t aa : 1;
__IO uint32_t mode : 2;
__IO uint32_t reserved6 : 26;
} TXCTL_b;
};
/* Address 0x1C4 */
union {
__I uint32_t TXSTAT;
struct {
__I uint32_t txstat : 5;
__I uint32_t txto : 1;
__I uint32_t txpcto : 1;
__I uint32_t reserved7 : 25;
} TXSTAT_b;
};
/* Address 0x1C8 */
union {
__IO uint32_t TXMBEBT;
struct {
__IO uint32_t minbe : 4;
__IO uint32_t maxbo : 3;
__IO uint32_t ble : 1;
__IO uint32_t maxbe : 4;
__IO uint32_t frcdly : 1;
__IO uint32_t hide : 4;
__IO uint32_t reserved17 : 15;
} TXMBEBT_b;
};
/* Address 0x1CC */
union {
__IO uint32_t TXCSMAC;
struct {
__IO uint32_t txcsmac : 18;
__IO uint32_t reserved18 : 14;
} TXCSMAC_b;
};
/* Address 0x1D0 */
union {
__IO uint32_t TXTRIES;
struct {
__IO uint32_t txtries : 4;
__IO uint32_t reserved4 : 28;
} TXTRIES_b;
};
/* Address 0x1D4 */
union {
__IO uint32_t TXPEND;
struct {
__IO uint32_t txpend : 1;
__IO uint32_t reserved1 : 31;
} TXPEND_b;
};
/* Address 0x1D8 */
union {
__IO uint32_t TXASC;
struct {
__IO uint32_t txasc : 1;
__IO uint32_t reserved1 : 31;
} TXASC_b;
};
/* Address 0x1DC */
union {
__IO uint32_t TXBUFAD;
struct {
__IO uint32_t txbufad : 32;
} TXBUFAD_b;
};
/* Address 0x1E0 */
union {
__IO uint32_t TXTO;
struct {
__IO uint32_t tx_to_len : 7;
__IO uint32_t tx_to_ena : 1;
__IO uint32_t tx_topc_ena : 1;
__IO uint32_t reserved9 : 23;
} TXTO_b;
};
/* Addresses 0x1E4 - 0x2BC */
__O uint32_t RESERVED1E4[55];
/* Address 0x2C0 */
union {
__IO uint32_t RXCTL;
struct {
__IO uint32_t rxctl : 5;
__IO uint32_t reserved5 : 27;
} RXCTL_b;
};
/* Address 0x2C4 */
union {
__I uint32_t RXSTAT;
struct {
__I uint32_t fcs_error : 1;
__I uint32_t abort : 1;
__I uint32_t unused_2_2 : 1;
__I uint32_t unused_3_3 : 1;
__I uint32_t mod_in_packet : 1;
__I uint32_t malformed : 1;
__I uint32_t reserved6 : 26;
} RXSTAT_b;
};
/* Address 0x2C8 */
union {
__IO uint32_t RXMPID;
struct {
__IO uint32_t rxmpid : 18;
__IO uint32_t reserved18 : 14;
} RXMPID_b;
};
/* Address 0x2CC */
union {
__IO uint32_t RXMSAD;
struct {
__IO uint32_t rxmsad : 16;
__IO uint32_t reserved16 : 16;
} RXMSAD_b;
};
/* Address 0x2D0 */
union {
__IO uint32_t RXMEADL;
struct {
__IO uint32_t rxmeadl : 32;
} RXMEADL_b;
};
/* Address 0x2D4 */
union {
__IO uint32_t RXMEADH;
struct {
__IO uint32_t rxmeadh : 32;
} RXMEADH_b;
};
/* Address 0x2D8 */
__O uint32_t RESERVED2D8[1];
/* Address 0x2DC */
union {
__IO uint32_t RXBUFAD;
struct {
__IO uint32_t rxbufad : 32;
} RXBUFAD_b;
};
/* Address 0x2E0 */
union {
__IO uint32_t RXPROM;
struct {
__IO uint32_t rxprom : 2;
__IO uint32_t reserved2 : 30;
} RXPROM_b;
};
/* Address 0x2E4 */
union {
__IO uint32_t RXMPID_SEC;
struct {
__IO uint32_t rxmpid_sec : 19;
__IO uint32_t reserved19 : 13;
} RXMPID_SEC_b;
};
/* Address 0x2E8 */
union {
__IO uint32_t RXMSAD_SEC;
struct {
__IO uint32_t rxmsad_sec : 16;
__IO uint32_t reserved16 : 16;
} RXMSAD_SEC_b;
};
/* Address 0x2EC */
union {
__IO uint32_t RXMEADL_SEC;
struct {
__IO uint32_t rxmeadl_sec : 32;
} RXMEADL_SEC_b;
};
/* Address 0x2F0 */
union {
__IO uint32_t RXMEADH_SEC;
struct {
__IO uint32_t rxmeadh_sec : 32;
} RXMEADH_SEC_b;
};
/* Addresses 0x2F4 - 0x2FC */
__O uint32_t RESERVED2F4[3];
/* Address 0x300 */
union {
__IO uint32_t DMA_ADDR;
struct {
__IO uint32_t dma_addr : 32;
} DMA_ADDR_b;
};
/* Address 0x304 */
union {
__I uint32_t DMA_RD_DATA;
struct {
__I uint32_t dma_rd_data : 32;
} DMA_RD_DATA_b;
};
/* Address 0x308 */
union {
__IO uint32_t DMA_WR_DATA;
struct {
__IO uint32_t dma_wr_data : 32;
} DMA_WR_DATA_b;
};
/* Address 0x30C */
union {
__IO uint32_t DMA_ADDR_OFFSET;
struct {
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
__IO uint32_t reserved0 : 15;
__IO uint32_t dma_addr_offset : 17;
#else
__IO uint32_t reserved0 : 17;
__IO uint32_t dma_addr_offset : 15;
#endif
} DMA_ADDR_OFFSET_b;
};
/* Addresses 0x310 - 0x3FC */
__O uint32_t RESERVED310[60];
/* Address 0x400 */
union {
__IO uint32_t DMA_FROM_ADC;
struct {
__IO uint32_t activate : 1;
__IO uint32_t mode : 4;
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
__IO uint32_t reserved5 : 27;
#else
__IO uint32_t safe : 1;
__IO uint32_t reserved6 : 26;
#endif
} DMA_FROM_ADC_b;
};
/* Address 0x404 */
union {
__IO uint32_t PHY_MCTRL;
struct {
__IO uint32_t bbc_rmi_req : 1;
__IO uint32_t reserved1 : 31;
} PHY_MCTRL_b;
};
/* Address 0x408 */
union {
__I uint32_t PHY_MSTATUS;
struct {
__I uint32_t bbc_rmi_ack : 1;
__I uint32_t reserved1 : 31;
} PHY_MSTATUS_b;
};
/* Addresses 0x40C - 0xFF0 */
__O uint32_t RESERVED40C[762];
/* Address 0xFF4 */
union {
__IO uint32_t POWERDOWN;
struct {
__IO uint32_t soft_reset : 1;
__IO uint32_t force_softreset : 1;
__IO uint32_t enable_flags_with_core_bus : 1;
__IO uint32_t reserved3 : 28;
__IO uint32_t powerdown : 1;
} POWERDOWN_b;
};
/* Address 0xFF8 */
__O uint32_t RESERVEDFF8[1];
/* Address 0xFFC */
union {
__I uint32_t MODULEID;
struct {
__I uint32_t aperture : 8;
__I uint32_t minor_revision : 4;
__I uint32_t major_revision : 4;
__I uint32_t identifier : 16;
} MODULEID_b;
};
} ZB_MAC_IF_Type;
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
#define ZBMAC_SCMR0_SCMR0_Pos 0
#define ZBMAC_SCMR0_SCMR0_Msk 0x0ffffffffUL
#define ZBMAC_SCMR1_SCMR1_Pos 0
#define ZBMAC_SCMR1_SCMR1_Msk 0x0ffffffffUL
#define ZBMAC_SCMR2_SCMR2_Pos 0
#define ZBMAC_SCMR2_SCMR2_Msk 0x0ffffffffUL
#define ZBMAC_SCMR3_SCMR3_Pos 0
#define ZBMAC_SCMR3_SCMR3_Msk 0x0ffffffffUL
#define ZBMAC_SCTR0_SCTR0_Pos 0
#define ZBMAC_SCTR0_SCTR0_Msk 0x0ffffffffUL
#define ZBMAC_SCTR1_SCTR1_Pos 0
#define ZBMAC_SCTR1_SCTR1_Msk 0x0ffffffffUL
#define ZBMAC_SCTCR_SCTCR_Pos 0
#define ZBMAC_SCTCR_SCTCR_Msk 0x03UL
#define ZBMAC_SCFRC_SCFRC_Pos 0
#define ZBMAC_SCFRC_SCFRC_Msk 0x0ffffffffUL
#define ZBMAC_SCSSR_SCSSR_Pos 0
#define ZBMAC_SCSSR_SCSSR_Msk 0x0ffffffffUL
#define ZBMAC_SCESL_SCESL_Pos 0
#define ZBMAC_SCESL_SCESL_Msk 0x0ffffffffUL
#define ZBMAC_RXETST_RXETST_Pos 0
#define ZBMAC_RXETST_RXETST_Msk 0x0ffffffffUL
#define ZBMAC_RXTSTP_RXTSTP_Pos 0
#define ZBMAC_RXTSTP_RXTSTP_Msk 0x0ffffffffUL
#define ZBMAC_TXTSTP_TXTSTP_Pos 0
#define ZBMAC_TXTSTP_TXTSTP_Msk 0x0ffffffffUL
#define ZBMAC_IER_IER_Pos 0
#define ZBMAC_IER_IER_Msk 0x03ffUL
#define ZBMAC_ISR_TXINT_Pos 0
#define ZBMAC_ISR_TXINT_Msk 0x01UL
#define ZBMAC_ISR_HEADERRXINT_Pos 1
#define ZBMAC_ISR_HEADERRXINT_Msk 0x02UL
#define ZBMAC_ISR_RXINT_Pos 2
#define ZBMAC_ISR_RXINT_Msk 0x04UL
#define ZBMAC_ISR_UNUSED_3_3_Pos 3
#define ZBMAC_ISR_UNUSED_3_3_Msk 0x08UL
#define ZBMAC_ISR_MATCH_Pos 4
#define ZBMAC_ISR_MATCH_Msk 0x0f0UL
#define ZBMAC_ISR_TIMEOUT_Pos 8
#define ZBMAC_ISR_TIMEOUT_Msk 0x0300UL
#define ZBMAC_SCTL_SCTL_Pos 0
#define ZBMAC_SCTL_SCTL_Msk 0x07fUL
#define ZBMAC_PHYTXTUNETIME_PHYTXTUNETIME_Pos 0
#define ZBMAC_PHYTXTUNETIME_PHYTXTUNETIME_Msk 0x0ffUL
#define ZBMAC_PHYTXTUNETIME_PHYRX2TXTIME_Pos 8
#define ZBMAC_PHYTXTUNETIME_PHYRX2TXTIME_Msk 0x0ff00UL
#define ZBMAC_PHYRXTUNETIME_PHYRXTUNETIME_Pos 0
#define ZBMAC_PHYRXTUNETIME_PHYRXTUNETIME_Msk 0x0ffUL
#define ZBMAC_TURNAROUNDTIME_TURNAROUNDTIME_Pos 0
#define ZBMAC_TURNAROUNDTIME_TURNAROUNDTIME_Msk 0x0ffUL
#define ZBMAC_BACKOFFTIME_BACKOFFTIME_Pos 0
#define ZBMAC_BACKOFFTIME_BACKOFFTIME_Msk 0x0ffUL
#define ZBMAC_PRBS_SEED_PRBS_SEED_Pos 0
#define ZBMAC_PRBS_SEED_PRBS_SEED_Msk 0x07fffUL
#define ZBMAC_SM_STATE_SM_STATE_Pos 0
#define ZBMAC_SM_STATE_SM_STATE_Msk 0x07fUL
#define ZBMAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Pos 0
#define ZBMAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Msk 0x0ffUL
#define ZBMAC_HDR_CTRL_HDR_CTRL_Pos 0
#define ZBMAC_HDR_CTRL_HDR_CTRL_Msk 0x03UL
#define ZBMAC_MISR_MISR_Pos 0
#define ZBMAC_MISR_MISR_Msk 0x03ffUL
#define ZBMAC_IDENTIFIER_IDENTIFIER_Pos 0
#define ZBMAC_IDENTIFIER_IDENTIFIER_Msk 0x0ffffffffUL
#define ZBMAC_TXCTL_SCH_Pos 0
#define ZBMAC_TXCTL_SCH_Msk 0x01UL
#define ZBMAC_TXCTL_SS_Pos 1
#define ZBMAC_TXCTL_SS_Msk 0x02UL
#define ZBMAC_TXCTL_SLOTACK_Pos 2
#define ZBMAC_TXCTL_SLOTACK_Msk 0x04UL
#define ZBMAC_TXCTL_AA_Pos 3
#define ZBMAC_TXCTL_AA_Msk 0x08UL
#define ZBMAC_TXCTL_MODE_Pos 4
#define ZBMAC_TXCTL_MODE_Msk 0x030UL
#define ZBMAC_TXSTAT_TXSTAT_Pos 0
#define ZBMAC_TXSTAT_TXSTAT_Msk 0x01fUL
#define ZBMAC_TXSTAT_TXTO_Pos 5
#define ZBMAC_TXSTAT_TXTO_Msk 0x020UL
#define ZBMAC_TXSTAT_TXPCTO_Pos 6
#define ZBMAC_TXSTAT_TXPCTO_Msk 0x040UL
#define ZBMAC_TXMBEBT_MINBE_Pos 0
#define ZBMAC_TXMBEBT_MINBE_Msk 0x0fUL
#define ZBMAC_TXMBEBT_MAXBO_Pos 4
#define ZBMAC_TXMBEBT_MAXBO_Msk 0x070UL
#define ZBMAC_TXMBEBT_BLE_Pos 7
#define ZBMAC_TXMBEBT_BLE_Msk 0x080UL
#define ZBMAC_TXMBEBT_MAXBE_Pos 8
#define ZBMAC_TXMBEBT_MAXBE_Msk 0x0f00UL
#define ZBMAC_TXMBEBT_FRCDLY_Pos 12
#define ZBMAC_TXMBEBT_FRCDLY_Msk 0x01000UL
#define ZBMAC_TXMBEBT_HIDE_Pos 13
#define ZBMAC_TXMBEBT_HIDE_Msk 0x01e000UL
#define ZBMAC_TXCSMAC_TXCSMAC_Pos 0
#define ZBMAC_TXCSMAC_TXCSMAC_Msk 0x03ffffUL
#define ZBMAC_TXTRIES_TXTRIES_Pos 0
#define ZBMAC_TXTRIES_TXTRIES_Msk 0x0fUL
#define ZBMAC_TXPEND_TXPEND_Pos 0
#define ZBMAC_TXPEND_TXPEND_Msk 0x01UL
#define ZBMAC_TXASC_TXASC_Pos 0
#define ZBMAC_TXASC_TXASC_Msk 0x01UL
#define ZBMAC_TXBUFAD_TXBUFAD_Pos 0
#define ZBMAC_TXBUFAD_TXBUFAD_Msk 0x0ffffffffUL
#define ZBMAC_TXTO_TX_TO_LEN_Pos 0
#define ZBMAC_TXTO_TX_TO_LEN_Msk 0x07fUL
#define ZBMAC_TXTO_TX_TO_ENA_Pos 7
#define ZBMAC_TXTO_TX_TO_ENA_Msk 0x080UL
#define ZBMAC_TXTO_TX_TOPC_ENA_Pos 8
#define ZBMAC_TXTO_TX_TOPC_ENA_Msk 0x0100UL
#define ZBMAC_RXCTL_RXCTL_Pos 0
#define ZBMAC_RXCTL_RXCTL_Msk 0x01fUL
#define ZBMAC_RXSTAT_FCS_ERROR_Pos 0
#define ZBMAC_RXSTAT_FCS_ERROR_Msk 0x01UL
#define ZBMAC_RXSTAT_ABORT_Pos 1
#define ZBMAC_RXSTAT_ABORT_Msk 0x02UL
#define ZBMAC_RXSTAT_UNUSED_2_2_Pos 2
#define ZBMAC_RXSTAT_UNUSED_2_2_Msk 0x04UL
#define ZBMAC_RXSTAT_UNUSED_3_3_Pos 3
#define ZBMAC_RXSTAT_UNUSED_3_3_Msk 0x08UL
#define ZBMAC_RXSTAT_MOD_IN_PACKET_Pos 4
#define ZBMAC_RXSTAT_MOD_IN_PACKET_Msk 0x010UL
#define ZBMAC_RXSTAT_MALFORMED_Pos 5
#define ZBMAC_RXSTAT_MALFORMED_Msk 0x020UL
#define ZBMAC_RXMPID_RXMPID_Pos 0
#define ZBMAC_RXMPID_RXMPID_Msk 0x03ffffUL
#define ZBMAC_RXMSAD_RXMSAD_Pos 0
#define ZBMAC_RXMSAD_RXMSAD_Msk 0x0ffffUL
#define ZBMAC_RXMEADL_RXMEADL_Pos 0
#define ZBMAC_RXMEADL_RXMEADL_Msk 0x0ffffffffUL
#define ZBMAC_RXMEADH_RXMEADH_Pos 0
#define ZBMAC_RXMEADH_RXMEADH_Msk 0x0ffffffffUL
#define ZBMAC_RXBUFAD_RXBUFAD_Pos 0
#define ZBMAC_RXBUFAD_RXBUFAD_Msk 0x0ffffffffUL
#define ZBMAC_RXPROM_RXPROM_Pos 0
#define ZBMAC_RXPROM_RXPROM_Msk 0x03UL
#define ZBMAC_RXMPID_SEC_RXMPID_SEC_Pos 0
#define ZBMAC_RXMPID_SEC_RXMPID_SEC_Msk 0x07ffffUL
#define ZBMAC_RXMSAD_SEC_RXMSAD_SEC_Pos 0
#define ZBMAC_RXMSAD_SEC_RXMSAD_SEC_Msk 0x0ffffUL
#define ZBMAC_RXMEADL_SEC_RXMEADL_SEC_Pos 0
#define ZBMAC_RXMEADL_SEC_RXMEADL_SEC_Msk 0x0ffffffffUL
#define ZBMAC_RXMEADH_SEC_RXMEADH_SEC_Pos 0
#define ZBMAC_RXMEADH_SEC_RXMEADH_SEC_Msk 0x0ffffffffUL
#define ZBMAC_DMA_ADDR_DMA_ADDR_Pos 0
#define ZBMAC_DMA_ADDR_DMA_ADDR_Msk 0x0ffffffffUL
#define ZBMAC_DMA_RD_DATA_DMA_RD_DATA_Pos 0
#define ZBMAC_DMA_RD_DATA_DMA_RD_DATA_Msk 0x0ffffffffUL
#define ZBMAC_DMA_WR_DATA_DMA_WR_DATA_Pos 0
#define ZBMAC_DMA_WR_DATA_DMA_WR_DATA_Msk 0x0ffffffffUL
#define ZBMAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Pos 15
#define ZBMAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Msk 0x0ffff8000UL
#define ZBMAC_DMA_FROM_ADC_ACTIVATE_Pos 0
#define ZBMAC_DMA_FROM_ADC_ACTIVATE_Msk 0x01UL
#define ZBMAC_DMA_FROM_ADC_MODE_Pos 1
#define ZBMAC_DMA_FROM_ADC_MODE_Msk 0x01eUL
#define ZBMAC_PHY_MCTRL_BBC_RMI_REQ_Pos 0
#define ZBMAC_PHY_MCTRL_BBC_RMI_REQ_Msk 0x01UL
#define ZBMAC_PHY_MSTATUS_BBC_RMI_ACK_Pos 0
#define ZBMAC_PHY_MSTATUS_BBC_RMI_ACK_Msk 0x01UL
#define ZBMAC_POWERDOWN_SOFT_RESET_Pos 0
#define ZBMAC_POWERDOWN_SOFT_RESET_Msk 0x01UL
#define ZBMAC_POWERDOWN_FORCE_SOFTRESET_Pos 1
#define ZBMAC_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
#define ZBMAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
#define ZBMAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
#define ZBMAC_POWERDOWN_POWERDOWN_Pos 31
#define ZBMAC_POWERDOWN_POWERDOWN_Msk 0x080000000UL
#define ZBMAC_MODULEID_APERTURE_Pos 0
#define ZBMAC_MODULEID_APERTURE_Msk 0x0ffUL
#define ZBMAC_MODULEID_MINOR_REVISION_Pos 8
#define ZBMAC_MODULEID_MINOR_REVISION_Msk 0x0f00UL
#define ZBMAC_MODULEID_MAJOR_REVISION_Pos 12
#define ZBMAC_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
#define ZBMAC_MODULEID_IDENTIFIER_Pos 16
#define ZBMAC_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
#else
#define ZB_MAC_SCMR0_SCMR0_Pos 0
#define ZB_MAC_SCMR0_SCMR0_Msk 0x0ffffffffUL
#define ZB_MAC_SCMR1_SCMR1_Pos 0
#define ZB_MAC_SCMR1_SCMR1_Msk 0x0ffffffffUL
#define ZB_MAC_SCMR2_SCMR2_Pos 0
#define ZB_MAC_SCMR2_SCMR2_Msk 0x0ffffffffUL
#define ZB_MAC_SCMR3_SCMR3_Pos 0
#define ZB_MAC_SCMR3_SCMR3_Msk 0x0ffffffffUL
#define ZB_MAC_SCTR0_SCTR0_Pos 0
#define ZB_MAC_SCTR0_SCTR0_Msk 0x0ffffffffUL
#define ZB_MAC_SCTR1_SCTR1_Pos 0
#define ZB_MAC_SCTR1_SCTR1_Msk 0x0ffffffffUL
#define ZB_MAC_SCTCR_SCTCR_Pos 0
#define ZB_MAC_SCTCR_SCTCR_Msk 0x03UL
#define ZB_MAC_SCFRC_SCFRC_Pos 0
#define ZB_MAC_SCFRC_SCFRC_Msk 0x0ffffffffUL
#define ZB_MAC_SCSSR_SCSSR_Pos 0
#define ZB_MAC_SCSSR_SCSSR_Msk 0x0ffffffffUL
#define ZB_MAC_SCESL_SCESL_Pos 0
#define ZB_MAC_SCESL_SCESL_Msk 0x0ffffffffUL
#define ZB_MAC_RXETST_RXETST_Pos 0
#define ZB_MAC_RXETST_RXETST_Msk 0x0ffffffffUL
#define ZB_MAC_RXTSTP_RXTSTP_Pos 0
#define ZB_MAC_RXTSTP_RXTSTP_Msk 0x0ffffffffUL
#define ZB_MAC_TXTSTP_TXTSTP_Pos 0
#define ZB_MAC_TXTSTP_TXTSTP_Msk 0x0ffffffffUL
#define ZB_MAC_IER_IER_Pos 0
#define ZB_MAC_IER_IER_Msk 0x0fffUL
#define ZB_MAC_ISR_TXINT_Pos 0
#define ZB_MAC_ISR_TXINT_Msk 0x01UL
#define ZB_MAC_ISR_HEADERRXINT_Pos 1
#define ZB_MAC_ISR_HEADERRXINT_Msk 0x02UL
#define ZB_MAC_ISR_RXINT_Pos 2
#define ZB_MAC_ISR_RXINT_Msk 0x04UL
#define ZB_MAC_ISR_UNUSED_3_3_Pos 3
#define ZB_MAC_ISR_UNUSED_3_3_Msk 0x08UL
#define ZB_MAC_ISR_MATCH_Pos 4
#define ZB_MAC_ISR_MATCH_Msk 0x0f0UL
#define ZB_MAC_ISR_TIMEOUT_Pos 8
#define ZB_MAC_ISR_TIMEOUT_Msk 0x0300UL
#define ZB_MAC_ISR_RXNOMATCH_Pos 10
#define ZB_MAC_ISR_RXNOMATCH_Msk 0x0400UL
#define ZB_MAC_ISR_RXMATCH_Pos 11
#define ZB_MAC_ISR_RXMATCH_Msk 0x0800UL
#define ZB_MAC_SCTL_SCTL_Pos 0
#define ZB_MAC_SCTL_SCTL_Msk 0x07fUL
#define ZB_MAC_PHYTXTUNETIME_PHYTXTUNETIME_Pos 0
#define ZB_MAC_PHYTXTUNETIME_PHYTXTUNETIME_Msk 0x0ffUL
#define ZB_MAC_PHYTXTUNETIME_PHYRX2TXTIME_Pos 8
#define ZB_MAC_PHYTXTUNETIME_PHYRX2TXTIME_Msk 0x0ff00UL
#define ZB_MAC_PHYRXTUNETIME_PHYRXTUNETIME_Pos 0
#define ZB_MAC_PHYRXTUNETIME_PHYRXTUNETIME_Msk 0x0ffUL
#define ZB_MAC_TURNAROUNDTIME_TURNAROUNDTIME_Pos 0
#define ZB_MAC_TURNAROUNDTIME_TURNAROUNDTIME_Msk 0x0ffUL
#define ZB_MAC_BACKOFFTIME_BACKOFFTIME_Pos 0
#define ZB_MAC_BACKOFFTIME_BACKOFFTIME_Msk 0x0ffUL
#define ZB_MAC_PRBS_SEED_PRBS_SEED_Pos 0
#define ZB_MAC_PRBS_SEED_PRBS_SEED_Msk 0x07fffUL
#define ZB_MAC_SM_STATE_SM_STATE_Pos 0
#define ZB_MAC_SM_STATE_SM_STATE_Msk 0x07fUL
#define ZB_MAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Pos 0
#define ZB_MAC_LIFSTURNAROUNDTIME_LIFSTURNAROUNDTIME_Msk 0x0ffUL
#define ZB_MAC_HDR_CTRL_HDR_CTRL_Pos 0
#define ZB_MAC_HDR_CTRL_HDR_CTRL_Msk 0x03UL
#define ZB_MAC_MISR_MISR_Pos 0
#define ZB_MAC_MISR_MISR_Msk 0x03ffUL
#define ZB_MAC_IDENTIFIER_IDENTIFIER_Pos 0
#define ZB_MAC_IDENTIFIER_IDENTIFIER_Msk 0x0ffffffffUL
#define ZB_MAC_TXCTL_SCH_Pos 0
#define ZB_MAC_TXCTL_SCH_Msk 0x01UL
#define ZB_MAC_TXCTL_SS_Pos 1
#define ZB_MAC_TXCTL_SS_Msk 0x02UL
#define ZB_MAC_TXCTL_SLOTACK_Pos 2
#define ZB_MAC_TXCTL_SLOTACK_Msk 0x04UL
#define ZB_MAC_TXCTL_AA_Pos 3
#define ZB_MAC_TXCTL_AA_Msk 0x08UL
#define ZB_MAC_TXCTL_MODE_Pos 4
#define ZB_MAC_TXCTL_MODE_Msk 0x030UL
#define ZB_MAC_TXSTAT_TXSTAT_Pos 0
#define ZB_MAC_TXSTAT_TXSTAT_Msk 0x01fUL
#define ZB_MAC_TXSTAT_TXTO_Pos 5
#define ZB_MAC_TXSTAT_TXTO_Msk 0x020UL
#define ZB_MAC_TXSTAT_TXPCTO_Pos 6
#define ZB_MAC_TXSTAT_TXPCTO_Msk 0x040UL
#define ZB_MAC_TXMBEBT_MINBE_Pos 0
#define ZB_MAC_TXMBEBT_MINBE_Msk 0x0fUL
#define ZB_MAC_TXMBEBT_MAXBO_Pos 4
#define ZB_MAC_TXMBEBT_MAXBO_Msk 0x070UL
#define ZB_MAC_TXMBEBT_BLE_Pos 7
#define ZB_MAC_TXMBEBT_BLE_Msk 0x080UL
#define ZB_MAC_TXMBEBT_MAXBE_Pos 8
#define ZB_MAC_TXMBEBT_MAXBE_Msk 0x0f00UL
#define ZB_MAC_TXMBEBT_FRCDLY_Pos 12
#define ZB_MAC_TXMBEBT_FRCDLY_Msk 0x01000UL
#define ZB_MAC_TXMBEBT_HIDE_Pos 13
#define ZB_MAC_TXMBEBT_HIDE_Msk 0x01e000UL
#define ZB_MAC_TXCSMAC_TXCSMAC_Pos 0
#define ZB_MAC_TXCSMAC_TXCSMAC_Msk 0x03ffffUL
#define ZB_MAC_TXTRIES_TXTRIES_Pos 0
#define ZB_MAC_TXTRIES_TXTRIES_Msk 0x0fUL
#define ZB_MAC_TXPEND_TXPEND_Pos 0
#define ZB_MAC_TXPEND_TXPEND_Msk 0x01UL
#define ZB_MAC_TXASC_TXASC_Pos 0
#define ZB_MAC_TXASC_TXASC_Msk 0x01UL
#define ZB_MAC_TXBUFAD_TXBUFAD_Pos 0
#define ZB_MAC_TXBUFAD_TXBUFAD_Msk 0x0ffffffffUL
#define ZB_MAC_TXTO_TX_TO_LEN_Pos 0
#define ZB_MAC_TXTO_TX_TO_LEN_Msk 0x07fUL
#define ZB_MAC_TXTO_TX_TO_ENA_Pos 7
#define ZB_MAC_TXTO_TX_TO_ENA_Msk 0x080UL
#define ZB_MAC_TXTO_TX_TOPC_ENA_Pos 8
#define ZB_MAC_TXTO_TX_TOPC_ENA_Msk 0x0100UL
#define ZB_MAC_RXCTL_RXCTL_Pos 0
#define ZB_MAC_RXCTL_RXCTL_Msk 0x01fUL
#define ZB_MAC_RXSTAT_FCS_ERROR_Pos 0
#define ZB_MAC_RXSTAT_FCS_ERROR_Msk 0x01UL
#define ZB_MAC_RXSTAT_ABORT_Pos 1
#define ZB_MAC_RXSTAT_ABORT_Msk 0x02UL
#define ZB_MAC_RXSTAT_UNUSED_2_2_Pos 2
#define ZB_MAC_RXSTAT_UNUSED_2_2_Msk 0x04UL
#define ZB_MAC_RXSTAT_UNUSED_3_3_Pos 3
#define ZB_MAC_RXSTAT_UNUSED_3_3_Msk 0x08UL
#define ZB_MAC_RXSTAT_MOD_IN_PACKET_Pos 4
#define ZB_MAC_RXSTAT_MOD_IN_PACKET_Msk 0x010UL
#define ZB_MAC_RXSTAT_MALFORMED_Pos 5
#define ZB_MAC_RXSTAT_MALFORMED_Msk 0x020UL
#define ZB_MAC_RXMPID_RXMPID_Pos 0
#define ZB_MAC_RXMPID_RXMPID_Msk 0x03ffffUL
#define ZB_MAC_RXMSAD_RXMSAD_Pos 0
#define ZB_MAC_RXMSAD_RXMSAD_Msk 0x0ffffUL
#define ZB_MAC_RXMEADL_RXMEADL_Pos 0
#define ZB_MAC_RXMEADL_RXMEADL_Msk 0x0ffffffffUL
#define ZB_MAC_RXMEADH_RXMEADH_Pos 0
#define ZB_MAC_RXMEADH_RXMEADH_Msk 0x0ffffffffUL
#define ZB_MAC_RXBUFAD_RXBUFAD_Pos 0
#define ZB_MAC_RXBUFAD_RXBUFAD_Msk 0x0ffffffffUL
#define ZB_MAC_RXPROM_RXPROM_Pos 0
#define ZB_MAC_RXPROM_RXPROM_Msk 0x03UL
#define ZB_MAC_RXMPID_SEC_RXMPID_SEC_Pos 0
#define ZB_MAC_RXMPID_SEC_RXMPID_SEC_Msk 0x07ffffUL
#define ZB_MAC_RXMSAD_SEC_RXMSAD_SEC_Pos 0
#define ZB_MAC_RXMSAD_SEC_RXMSAD_SEC_Msk 0x0ffffUL
#define ZB_MAC_RXMEADL_SEC_RXMEADL_SEC_Pos 0
#define ZB_MAC_RXMEADL_SEC_RXMEADL_SEC_Msk 0x0ffffffffUL
#define ZB_MAC_RXMEADH_SEC_RXMEADH_SEC_Pos 0
#define ZB_MAC_RXMEADH_SEC_RXMEADH_SEC_Msk 0x0ffffffffUL
#define ZB_MAC_DMA_ADDR_DMA_ADDR_Pos 0
#define ZB_MAC_DMA_ADDR_DMA_ADDR_Msk 0x0ffffffffUL
#define ZB_MAC_DMA_RD_DATA_DMA_RD_DATA_Pos 0
#define ZB_MAC_DMA_RD_DATA_DMA_RD_DATA_Msk 0x0ffffffffUL
#define ZB_MAC_DMA_WR_DATA_DMA_WR_DATA_Pos 0
#define ZB_MAC_DMA_WR_DATA_DMA_WR_DATA_Msk 0x0ffffffffUL
#define ZB_MAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Pos 17
#define ZB_MAC_DMA_ADDR_OFFSET_DMA_ADDR_OFFSET_Msk 0x0fffe0000UL
#define ZB_MAC_DMA_FROM_ADC_ACTIVATE_Pos 0
#define ZB_MAC_DMA_FROM_ADC_ACTIVATE_Msk 0x01UL
#define ZB_MAC_DMA_FROM_ADC_MODE_Pos 1
#define ZB_MAC_DMA_FROM_ADC_MODE_Msk 0x01eUL
#define ZB_MAC_DMA_FROM_ADC_SAFE_Pos 5
#define ZB_MAC_DMA_FROM_ADC_SAFE_Msk 0x020UL
#define ZB_MAC_PHY_MCTRL_BBC_RMI_REQ_Pos 0
#define ZB_MAC_PHY_MCTRL_BBC_RMI_REQ_Msk 0x01UL
#define ZB_MAC_PHY_MSTATUS_BBC_RMI_ACK_Pos 0
#define ZB_MAC_PHY_MSTATUS_BBC_RMI_ACK_Msk 0x01UL
#define ZB_MAC_POWERDOWN_SOFT_RESET_Pos 0
#define ZB_MAC_POWERDOWN_SOFT_RESET_Msk 0x01UL
#define ZB_MAC_POWERDOWN_FORCE_SOFTRESET_Pos 1
#define ZB_MAC_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
#define ZB_MAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
#define ZB_MAC_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
#define ZB_MAC_POWERDOWN_POWERDOWN_Pos 31
#define ZB_MAC_POWERDOWN_POWERDOWN_Msk 0x080000000UL
#define ZB_MAC_MODULEID_APERTURE_Pos 0
#define ZB_MAC_MODULEID_APERTURE_Msk 0x0ffUL
#define ZB_MAC_MODULEID_MINOR_REVISION_Pos 8
#define ZB_MAC_MODULEID_MINOR_REVISION_Msk 0x0f00UL
#define ZB_MAC_MODULEID_MAJOR_REVISION_Pos 12
#define ZB_MAC_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
#define ZB_MAC_MODULEID_IDENTIFIER_Pos 16
#define ZB_MAC_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
#endif
#endif // __ZB_MAC_IF_H__
third_party/nxp/JN5189/Radio_JN5189/Include/jn518x_zb_modem.h
Vendored
-405
View File
@@ -1,405 +0,0 @@
/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __ZB_MODEM_IF_H__
#define __ZB_MODEM_IF_H__
typedef struct {
/* Address 0x000 */
union {
__IO uint32_t MCCA_CTRL;
struct {
__IO uint32_t rx_cca_mode : 2;
__IO uint32_t rx_cca_thresh : 10;
__IO uint32_t rx_cca_or : 1;
__IO uint32_t reserved13 : 19;
} MCCA_CTRL_b;
};
/* Address 0x004 */
union {
__IO uint32_t MTX_CTRL;
struct {
__IO uint32_t tx_test_en : 1;
__IO uint32_t tx_test_mode : 1;
__IO uint32_t tx_pol : 1;
__IO uint32_t tx_inframe_sync : 1;
__IO uint32_t reserved4 : 28;
} MTX_CTRL_b;
};
/* Address 0x008 */
union {
__IO uint32_t MTX_TST_SEQ;
struct {
__IO uint32_t tx_test_seq : 32;
} MTX_TST_SEQ_b;
};
/* Address 0x00C */
union {
__IO uint32_t MRX_CTRL;
struct {
__IO uint32_t rx_cor_lo : 6;
__IO uint32_t rx_cor_hi : 6;
__IO uint32_t rx_sync_mode : 2;
__IO uint32_t rx_pol : 2;
__IO uint32_t rx_pre_num : 3;
__IO uint32_t rx_early_eop : 2;
__IO uint32_t rx_agc_rst_en : 1;
__IO uint32_t rx_agc_rst_thr : 7;
__IO uint32_t rx_rssi_avg_en : 1;
__IO uint32_t rx_rssi_pulse_mode : 1;
__IO uint32_t reserved31 : 1;
} MRX_CTRL_b;
};
/* Address 0x010 */
union {
__I uint32_t MSTAT;
struct {
__I uint32_t rx_pre_state : 2;
__I uint32_t rx_pre_cnt : 3;
__I uint32_t rx_ad_ant : 1;
__I uint32_t rx_rssi_avg : 10;
__I uint32_t rx_sqi : 8;
__I uint32_t rx_ccas : 1;
__I uint32_t rx_ad_switch : 1;
__I uint32_t reserved26 : 6;
} MSTAT_b;
};
/* Address 0x014 */
union {
__IO uint32_t RXFE_CONFIG;
struct {
__IO uint32_t selfi : 4;
__IO uint32_t specinv : 1;
__IO uint32_t bypass_lpf : 1;
__IO uint32_t bypass_adj : 1;
__IO uint32_t selfe4demod : 1;
__IO uint32_t selfe4agc : 1;
__IO uint32_t loopback : 1;
__IO uint32_t bitinv : 1;
__IO uint32_t xcorr_mode : 1;
__IO uint32_t reserved12 : 20;
} RXFE_CONFIG_b;
};
/* Address 0x018 */
union {
__IO uint32_t PHY_MCTRL;
struct {
__IO uint32_t reserved0 : 1;
__IO uint32_t miom : 1;
__IO uint32_t mphyon : 1;
__IO uint32_t mphydir : 1;
__IO uint32_t mccat : 1;
__IO uint32_t medt : 1;
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
/* ES1 if explicitly configured */
__IO uint32_t reserved6 : 26;
#else
/* ES2 default */
__IO uint32_t aedt : 1;
__IO uint32_t reserved7 : 25;
#endif
} PHY_MCTRL_b;
};
/* Address 0x01C */
union {
__IO uint32_t PHY_CHAN;
struct {
__IO uint32_t chan : 5;
__IO uint32_t unused_6_5 : 2;
__IO uint32_t man_freq_en : 1;
__IO uint32_t man_freq : 8;
__IO uint32_t reserved16 : 16;
} PHY_CHAN_b;
};
/* Address 0x020 */
union {
__IO uint32_t PHY_PWR;
struct {
__IO uint32_t pwr : 8;
__IO uint32_t reserved8 : 24;
} PHY_PWR_b;
};
/* Address 0x024 */
union {
__I uint32_t RX_PP;
struct {
__I uint32_t rx_cpp : 10;
__I uint32_t rx_ppp : 10;
__I uint32_t rx_ipp : 10;
__I uint32_t reserved30 : 2;
} RX_PP_b;
};
/* Address 0x028 */
union {
__IO uint32_t ANT_DIV_P;
struct {
__IO uint32_t sw_toogle : 1;
__IO uint32_t reserved1 : 31;
} ANT_DIV_P_b;
};
/* Address 0x02C */
union {
__IO uint32_t ANT_DIV;
struct {
__IO uint32_t ad_rssi_thr : 10;
__IO uint32_t rx_ad_en : 1;
__IO uint32_t tx_ad_en : 1;
__IO uint32_t rx_ad_timer : 4;
__IO uint32_t reserved16 : 16;
} ANT_DIV_b;
};
/* Addresses 0x030 - 0xFDC */
__O uint32_t RESERVED030[1004];
/* Address 0xFE0 */
union {
__I uint32_t ZB_EVENTS_STATUS;
struct {
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
__I uint32_t status : 13;
__I uint32_t reserved13 : 19;
#else
__I uint32_t status : 15;
__I uint32_t reserved15 : 17;
#endif
} ZB_EVENTS_STATUS_b;
};
/* Address 0xFE4 */
union {
__IO uint32_t ZB_EVENTS_ENABLE;
struct {
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
__IO uint32_t enable : 13;
__IO uint32_t reserved13 : 19;
#else
__IO uint32_t enable : 15;
__IO uint32_t reserved15 : 17;
#endif
} ZB_EVENTS_ENABLE_b;
};
/* Address 0xFE8 */
union {
__IO uint32_t ZB_EVENTS_CLEAR;
struct {
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
__IO uint32_t clear : 13;
__IO uint32_t reserved13 : 19;
#else
__IO uint32_t clear : 15;
__IO uint32_t reserved15 : 17;
#endif
} ZB_EVENTS_CLEAR_b;
};
/* Address 0xFEC */
union {
__IO uint32_t ZB_EVENTS_SET;
struct {
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
__IO uint32_t set : 13;
__IO uint32_t reserved13 : 19;
#else
__IO uint32_t set : 15;
__IO uint32_t reserved15 : 17;
#endif
} ZB_EVENTS_SET_b;
};
/* Address 0xFF0 */
__O uint32_t RESERVEDFF0[1];
/* Address 0xFF4 */
union {
__IO uint32_t POWERDOWN;
struct {
__IO uint32_t soft_reset : 1;
__IO uint32_t force_softreset : 1;
__IO uint32_t enable_flags_with_core_bus : 1;
__IO uint32_t reserved3 : 28;
__IO uint32_t powerdown : 1;
} POWERDOWN_b;
};
/* Address 0xFF8 */
__O uint32_t RESERVEDFF8[1];
/* Address 0xFFC */
union {
__I uint32_t MODULEID;
struct {
__I uint32_t aperture : 8;
__I uint32_t minor_revision : 4;
__I uint32_t major_revision : 4;
__I uint32_t identifier : 16;
} MODULEID_b;
};
} ZB_MODEM_IF_Type;
#define ZB_MODEM_MCCA_CTRL_RX_CCA_MODE_Pos 0
#define ZB_MODEM_MCCA_CTRL_RX_CCA_MODE_Msk 0x03UL
#define ZB_MODEM_MCCA_CTRL_RX_CCA_THRESH_Pos 2
#define ZB_MODEM_MCCA_CTRL_RX_CCA_THRESH_Msk 0x0ffcUL
#define ZB_MODEM_MCCA_CTRL_RX_CCA_OR_Pos 12
#define ZB_MODEM_MCCA_CTRL_RX_CCA_OR_Msk 0x01000UL
#define ZB_MODEM_MTX_CTRL_TX_TEST_EN_Pos 0
#define ZB_MODEM_MTX_CTRL_TX_TEST_EN_Msk 0x01UL
#define ZB_MODEM_MTX_CTRL_TX_TEST_MODE_Pos 1
#define ZB_MODEM_MTX_CTRL_TX_TEST_MODE_Msk 0x02UL
#define ZB_MODEM_MTX_CTRL_TX_POL_Pos 2
#define ZB_MODEM_MTX_CTRL_TX_POL_Msk 0x04UL
#define ZB_MODEM_MTX_CTRL_TX_INFRAME_SYNC_Pos 3
#define ZB_MODEM_MTX_CTRL_TX_INFRAME_SYNC_Msk 0x08UL
#define ZB_MODEM_MTX_TST_SEQ_TX_TEST_SEQ_Pos 0
#define ZB_MODEM_MTX_TST_SEQ_TX_TEST_SEQ_Msk 0x0ffffffffUL
#define ZB_MODEM_MRX_CTRL_RX_COR_LO_Pos 0
#define ZB_MODEM_MRX_CTRL_RX_COR_LO_Msk 0x03fUL
#define ZB_MODEM_MRX_CTRL_RX_COR_HI_Pos 6
#define ZB_MODEM_MRX_CTRL_RX_COR_HI_Msk 0x0fc0UL
#define ZB_MODEM_MRX_CTRL_RX_SYNC_MODE_Pos 12
#define ZB_MODEM_MRX_CTRL_RX_SYNC_MODE_Msk 0x03000UL
#define ZB_MODEM_MRX_CTRL_RX_POL_Pos 14
#define ZB_MODEM_MRX_CTRL_RX_POL_Msk 0x0c000UL
#define ZB_MODEM_MRX_CTRL_RX_PRE_NUM_Pos 16
#define ZB_MODEM_MRX_CTRL_RX_PRE_NUM_Msk 0x070000UL
#define ZB_MODEM_MRX_CTRL_RX_EARLY_EOP_Pos 19
#define ZB_MODEM_MRX_CTRL_RX_EARLY_EOP_Msk 0x0180000UL
#define ZB_MODEM_MRX_CTRL_RX_AGC_RST_EN_Pos 21
#define ZB_MODEM_MRX_CTRL_RX_AGC_RST_EN_Msk 0x0200000UL
#define ZB_MODEM_MRX_CTRL_RX_AGC_RST_THR_Pos 22
#define ZB_MODEM_MRX_CTRL_RX_AGC_RST_THR_Msk 0x01fc00000UL
#define ZB_MODEM_MRX_CTRL_RX_RSSI_AVG_EN_Pos 29
#define ZB_MODEM_MRX_CTRL_RX_RSSI_AVG_EN_Msk 0x020000000UL
#define ZB_MODEM_MRX_CTRL_RX_RSSI_PULSE_MODE_Pos 30
#define ZB_MODEM_MRX_CTRL_RX_RSSI_PULSE_MODE_Msk 0x040000000UL
#define ZB_MODEM_MSTAT_RX_PRE_STATE_Pos 0
#define ZB_MODEM_MSTAT_RX_PRE_STATE_Msk 0x03UL
#define ZB_MODEM_MSTAT_RX_PRE_CNT_Pos 2
#define ZB_MODEM_MSTAT_RX_PRE_CNT_Msk 0x01cUL
#define ZB_MODEM_MSTAT_RX_AD_ANT_Pos 5
#define ZB_MODEM_MSTAT_RX_AD_ANT_Msk 0x020UL
#define ZB_MODEM_MSTAT_RX_RSSI_AVG_Pos 6
#define ZB_MODEM_MSTAT_RX_RSSI_AVG_Msk 0x0ffc0UL
#define ZB_MODEM_MSTAT_RX_SQI_Pos 16
#define ZB_MODEM_MSTAT_RX_SQI_Msk 0x0ff0000UL
#define ZB_MODEM_MSTAT_RX_CCAS_Pos 24
#define ZB_MODEM_MSTAT_RX_CCAS_Msk 0x01000000UL
#define ZB_MODEM_MSTAT_RX_AD_SWITCH_Pos 25
#define ZB_MODEM_MSTAT_RX_AD_SWITCH_Msk 0x02000000UL
#define ZB_MODEM_RXFE_CONFIG_SELFI_Pos 0
#define ZB_MODEM_RXFE_CONFIG_SELFI_Msk 0x0fUL
#define ZB_MODEM_RXFE_CONFIG_SPECINV_Pos 4
#define ZB_MODEM_RXFE_CONFIG_SPECINV_Msk 0x010UL
#define ZB_MODEM_RXFE_CONFIG_BYPASS_LPF_Pos 5
#define ZB_MODEM_RXFE_CONFIG_BYPASS_LPF_Msk 0x020UL
#define ZB_MODEM_RXFE_CONFIG_BYPASS_ADJ_Pos 6
#define ZB_MODEM_RXFE_CONFIG_BYPASS_ADJ_Msk 0x040UL
#define ZB_MODEM_RXFE_CONFIG_SELFE4DEMOD_Pos 7
#define ZB_MODEM_RXFE_CONFIG_SELFE4DEMOD_Msk 0x080UL
#define ZB_MODEM_RXFE_CONFIG_SELFE4AGC_Pos 8
#define ZB_MODEM_RXFE_CONFIG_SELFE4AGC_Msk 0x0100UL
#define ZB_MODEM_RXFE_CONFIG_LOOPBACK_Pos 9
#define ZB_MODEM_RXFE_CONFIG_LOOPBACK_Msk 0x0200UL
#define ZB_MODEM_RXFE_CONFIG_BITINV_Pos 10
#define ZB_MODEM_RXFE_CONFIG_BITINV_Msk 0x0400UL
#define ZB_MODEM_RXFE_CONFIG_XCORR_MODE_Pos 11
#define ZB_MODEM_RXFE_CONFIG_XCORR_MODE_Msk 0x0800UL
#define ZB_MODEM_PHY_MCTRL_MIOM_Pos 1
#define ZB_MODEM_PHY_MCTRL_MIOM_Msk 0x02UL
#define ZB_MODEM_PHY_MCTRL_MPHYON_Pos 2
#define ZB_MODEM_PHY_MCTRL_MPHYON_Msk 0x04UL
#define ZB_MODEM_PHY_MCTRL_MPHYDIR_Pos 3
#define ZB_MODEM_PHY_MCTRL_MPHYDIR_Msk 0x08UL
#define ZB_MODEM_PHY_MCTRL_MCCAT_Pos 4
#define ZB_MODEM_PHY_MCTRL_MCCAT_Msk 0x010UL
#define ZB_MODEM_PHY_MCTRL_MEDT_Pos 5
#define ZB_MODEM_PHY_MCTRL_MEDT_Msk 0x020UL
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
#else
#define ZB_MODEM_PHY_MCTRL_AEDT_Pos 6
#define ZB_MODEM_PHY_MCTRL_AEDT_Msk 0x040UL
#endif
#define ZB_MODEM_PHY_CHAN_CHAN_Pos 0
#define ZB_MODEM_PHY_CHAN_CHAN_Msk 0x01fUL
#define ZB_MODEM_PHY_CHAN_UNUSED_6_5_Pos 5
#define ZB_MODEM_PHY_CHAN_UNUSED_6_5_Msk 0x060UL
#define ZB_MODEM_PHY_CHAN_MAN_FREQ_EN_Pos 7
#define ZB_MODEM_PHY_CHAN_MAN_FREQ_EN_Msk 0x080UL
#define ZB_MODEM_PHY_CHAN_MAN_FREQ_Pos 8
#define ZB_MODEM_PHY_CHAN_MAN_FREQ_Msk 0x0ff00UL
#define ZB_MODEM_PHY_PWR_PWR_Pos 0
#define ZB_MODEM_PHY_PWR_PWR_Msk 0x0ffUL
#define ZB_MODEM_RX_PP_RX_CPP_Pos 0
#define ZB_MODEM_RX_PP_RX_CPP_Msk 0x03ffUL
#define ZB_MODEM_RX_PP_RX_PPP_Pos 10
#define ZB_MODEM_RX_PP_RX_PPP_Msk 0x0ffc00UL
#define ZB_MODEM_RX_PP_RX_IPP_Pos 20
#define ZB_MODEM_RX_PP_RX_IPP_Msk 0x03ff00000UL
#define ZB_MODEM_ANT_DIV_P_SW_TOOGLE_Pos 0
#define ZB_MODEM_ANT_DIV_P_SW_TOOGLE_Msk 0x01UL
#define ZB_MODEM_ANT_DIV_AD_RSSI_THR_Pos 0
#define ZB_MODEM_ANT_DIV_AD_RSSI_THR_Msk 0x03ffUL
#define ZB_MODEM_ANT_DIV_RX_AD_EN_Pos 10
#define ZB_MODEM_ANT_DIV_RX_AD_EN_Msk 0x0400UL
#define ZB_MODEM_ANT_DIV_TX_AD_EN_Pos 11
#define ZB_MODEM_ANT_DIV_TX_AD_EN_Msk 0x0800UL
#define ZB_MODEM_ANT_DIV_RX_AD_TIMER_Pos 12
#define ZB_MODEM_ANT_DIV_RX_AD_TIMER_Msk 0x0f000UL
#define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Pos 0
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
#define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Msk 0x01fffUL
#else
#define ZB_MODEM_ZB_EVENTS_STATUS_STATUS_Msk 0x07fffUL
#endif
#define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Pos 0
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
#define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Msk 0x01fffUL
#else
#define ZB_MODEM_ZB_EVENTS_ENABLE_ENABLE_Msk 0x07fffUL
#endif
#define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Pos 0
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
#define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Msk 0x01fffUL
#else
#define ZB_MODEM_ZB_EVENTS_CLEAR_CLEAR_Msk 0x07fffUL
#endif
#define ZB_MODEM_ZB_EVENTS_SET_SET_Pos 0
#if defined(CPU_JN518X_REV)&&(CPU_JN518X_REV == 1)
#define ZB_MODEM_ZB_EVENTS_SET_SET_Msk 0x01fffUL
#else
#define ZB_MODEM_ZB_EVENTS_SET_SET_Msk 0x07fffUL
#endif
#define ZB_MODEM_POWERDOWN_SOFT_RESET_Pos 0
#define ZB_MODEM_POWERDOWN_SOFT_RESET_Msk 0x01UL
#define ZB_MODEM_POWERDOWN_FORCE_SOFTRESET_Pos 1
#define ZB_MODEM_POWERDOWN_FORCE_SOFTRESET_Msk 0x02UL
#define ZB_MODEM_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Pos 2
#define ZB_MODEM_POWERDOWN_ENABLE_FLAGS_WITH_CORE_BUS_Msk 0x04UL
#define ZB_MODEM_POWERDOWN_POWERDOWN_Pos 31
#define ZB_MODEM_POWERDOWN_POWERDOWN_Msk 0x080000000UL
#define ZB_MODEM_MODULEID_APERTURE_Pos 0
#define ZB_MODEM_MODULEID_APERTURE_Msk 0x0ffUL
#define ZB_MODEM_MODULEID_MINOR_REVISION_Pos 8
#define ZB_MODEM_MODULEID_MINOR_REVISION_Msk 0x0f00UL
#define ZB_MODEM_MODULEID_MAJOR_REVISION_Pos 12
#define ZB_MODEM_MODULEID_MAJOR_REVISION_Msk 0x0f000UL
#define ZB_MODEM_MODULEID_IDENTIFIER_Pos 16
#define ZB_MODEM_MODULEID_IDENTIFIER_Msk 0x0ffff0000UL
#endif // __ZB_MODEM_IF_H__
third_party/nxp/JN5189/Radio_JN5189/Include/radio_jn518x.h
Vendored
-72
View File
@@ -1,72 +0,0 @@
/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __RADIO_JN518X_H_
#define __RADIO_JN518X_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "radio.h"
/****************************************************************************/
/*** Macro/Type Definitions ***/
/****************************************************************************/
#define RADIO_JN518X_VERSION RADIO_VERSION
#define RADIO_JN5189_MAX_RSSI_REPORT RADIO_MAX_RSSI_REPORT
#define RADIO_JN5189_MIN_RSSI_REPORT RADIO_MIN_RSSI_REPORT
#define vRadio_Jn518x_RadioInit vRadio_RadioInit
#define vRadio_Jn518x_RadioDeInit vRadio_RadioDeInit
#define vRadio_Jn518x_Standard_Init vRadio_Standard_Init
#define u8Radio_Jn518x_GetEDfromRSSI u8Radio_GetEDfromRSSI
#define u32Radio_Jn518x_RadioModesAvailable u32Radio_RadioModesAvailable
#define u32Radio_Jn518x_RadioGetVersion u32Radio_RadioGetVersion
#define vRadio_JN518x_Temp_Update vRadio_Temp_Update
#define vRadio_JN518x_ConfigCalFlashUsage vRadio_ConfigCalFlashUsage
#define vRadio_jn518x_Save_ApplicationData_Retention vRadio_Save_ApplicationData_Retention
#define vRadio_jn518x_Restore_Retention_ApplicationData vRadio_Restore_Retention_ApplicationData
#define vRadio_JN518xRecal vRadio_Recal
#define vRadio_Jn518x_RFT1778_bad_crc vRadio_RFT1778_bad_crc
#define vRadio_Jn518x_LockupCheckAndAbortRadio vRadio_LockupCheckAndAbortRadio
#define i16Radio_Jn518x_GetRSSI i16Radio_GetRSSI
#define i16Radio_Jn518x_GetNbRSSISync i16Radio_GetNbRSSISync
#define i16Radio_Jn518x_GetNbRSSISyncCor i16Radio_GetNbRSSISyncCor
#define i8Radio_Jn518x_GetLastPacketRSSI i8Radio_GetLastPacketRSSI
#define i16Radio_Jn518x_BoundRssiValue i16Radio_BoundRssiValue
#define vRadio_Jn518x_BLE_ResetOn vRadio_BLE_ResetOn
#define vRadio_Jn518x_BLE_ResetOff vRadio_BLE_ResetOff
#define vRadio_Jn518x_remove_patch_ISR vRadio_remove_patch_ISR
#define vRadio_Jn518x_SingleRX_AgcReadyPatch vRadio_SingleRX_AgcReadyPatch
#define vRadio_Jn518x_MultiRX_AgcReadyPatch vRadio_MultiRX_AgcReadyPatch
#define vRadio_Jn518x_Enable_AgcReadyPatch vRadio_Enable_AgcReadyPatch;
#define vRadio_Jn518x_Disable_AgcReadyPatch vRadio_Disable_AgcReadyPatch
#define vRadio_Jn518x_SkipXTALInit vRadio_SkipXTALInit
#define vRadio_Jn518x_EnableXTALInit vRadio_EnableXTALInit
#define vRadio_jn518x_ActivateXtal32MRadioBiasing vRadio_ActivateXtal32MRadioBiasing
#define vRadio_jn518x_DisableZBRadio vRadio_DisableZBRadio
#define vRadio_jn518x_DisableBLERadio vRadio_DisableBLERadio
#define vRadio_jn518x_EnableBLEFastTX vRadio_EnableBLEFastTX
#define vRadio_jn518x_DisableBLEFastTX vRadio_DisableBLEFastTX
#define vRadio_jn518x_ZBtoBLE vRadio_ZBtoBLE
#define vRadio_jn518x_BLEtoZB vRadio_BLEtoZB
#define u32Radio_JN518x_Get_Next_Recal_Duration u32Radio_Get_Next_Recal_Duration
#define vRadio_Jn518x_AntennaDiversityTxRxEnable vRadio_AntennaDiversityTxRxEnable
#define vRadio_Jn518x_AntennaDiversityConfigure vRadio_AntennaDiversityConfigure
#define vRadio_Jn518x_AntennaDiversitySwitch vRadio_AntennaDiversitySwitch
#define u8Radio_Jn518x_AntennaDiversityStatus u8Radio_AntennaDiversityStatus
#ifdef __cplusplus
}
#endif
#endif /* __RADIO_JN518X_H_ */
third_party/nxp/JN5189/Radio_JN5189/Include/system_jn518x.h
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#ifndef SYSTEM_JN518X_H
#define SYSTEM_JN518X_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/* *** JN518x *** */
/** \brief Exceptions and Interrupts vectors structure.
*/
typedef struct
{
uint32_t pExceptions[16]; /*!< System exceptions vectors */
uint32_t pIsr[240]; /*!< User interrupt vectors */
} VectorTable_Type;
extern const uint32_t XSW_VTOR_BASE ;
#define JN518X_ISR_TABLE ((VectorTable_Type *) XSW_VTOR_BASE)
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_JN518X_H */
third_party/nxp/JN5189/drivers/fsl_debug_console.h
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/*
* Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Debug console shall provide input and output functions to scan and print formatted data.
* o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
* - [flags] :'-', '+', '#', ' ', '0'
* - [width]: number (0,1...)
* - [.precision]: number (0,1...)
* - [length]: do not support
* - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
* o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
* - [*]: is supported.
* - [width]: number (0,1...)
* - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
* - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
*/
#ifndef _FSL_DEBUGCONSOLE_H_
#define _FSL_DEBUGCONSOLE_H_
#include "fsl_common.h"
/*
* @addtogroup debugconsole
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Definition to select sdk or toolchain printf, scanf. */
#ifndef SDK_DEBUGCONSOLE
#define SDK_DEBUGCONSOLE 1U
#endif
#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
#include <stdio.h>
#endif
/*! @brief Definition to printf the float number. */
#ifndef PRINTF_FLOAT_ENABLE
#define PRINTF_FLOAT_ENABLE 0U
#endif /* PRINTF_FLOAT_ENABLE */
/*! @brief Definition to scanf the float number. */
#ifndef SCANF_FLOAT_ENABLE
#define SCANF_FLOAT_ENABLE 0U
#endif /* SCANF_FLOAT_ENABLE */
/*! @brief Definition to support advanced format specifier for printf. */
#ifndef PRINTF_ADVANCED_ENABLE
#define PRINTF_ADVANCED_ENABLE 0U
#endif /* PRINTF_ADVANCED_ENABLE */
/*! @brief Definition to support advanced format specifier for scanf. */
#ifndef SCANF_ADVANCED_ENABLE
#define SCANF_ADVANCED_ENABLE 0U
#endif /* SCANF_ADVANCED_ENABLE */
#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */
#define PRINTF DbgConsole_Printf
#define SCANF DbgConsole_Scanf
#define PUTCHAR DbgConsole_Putchar
#define GETCHAR DbgConsole_Getchar
#else /* Select printf, scanf, putchar, getchar of toolchain. */
#define PRINTF printf
#define SCANF scanf
#define PUTCHAR putchar
#define GETCHAR getchar
#endif /* SDK_DEBUGCONSOLE */
/*******************************************************************************
* Prototypes
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*! @name Initialization*/
/* @{ */
/*!
* @brief Initializes the the peripheral used for debug messages.
*
* Call this function to enable debug log messages to be output via the specified peripheral,
* frequency of peripheral source clock, and base address at the specified baud rate.
* After this function has returned, stdout and stdin are connected to the selected peripheral.
*
* @param baseAddr Indicates the address of the peripheral used to send debug messages.
* @param baudRate The desired baud rate in bits per second.
* @param device Low level device type for the debug console, can be one of the following.
* @arg DEBUG_CONSOLE_DEVICE_TYPE_UART,
* @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART,
* @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI,
* @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC.
* @param clkSrcFreq Frequency of peripheral source clock.
*
* @return Indicates whether initialization was successful or not.
* @retval kStatus_Success Execution successfully
* @retval kStatus_Fail Execution failure
* @retval kStatus_InvalidArgument Invalid argument existed
*/
status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq);
/*!
* @brief De-initializes the peripheral used for debug messages.
*
* Call this function to disable debug log messages to be output via the specified peripheral
* base address and at the specified baud rate.
*
* @return Indicates whether de-initialization was successful or not.
*/
status_t DbgConsole_Deinit(void);
#if SDK_DEBUGCONSOLE
/*!
* @brief Writes formatted output to the standard output stream.
*
* Call this function to write a formatted output to the standard output stream.
*
* @param fmt_s Format control string.
* @return Returns the number of characters printed or a negative value if an error occurs.
*/
int DbgConsole_Printf(const char *fmt_s, ...);
/*!
* @brief Writes a character to stdout.
*
* Call this function to write a character to stdout.
*
* @param ch Character to be written.
* @return Returns the character written.
*/
int DbgConsole_Putchar(int ch);
/*!
* @brief Reads formatted data from the standard input stream.
*
* Call this function to read formatted data from the standard input stream.
*
* @param fmt_ptr Format control string.
* @return Returns the number of fields successfully converted and assigned.
*/
int DbgConsole_Scanf(char *fmt_ptr, ...);
/*!
* @brief Reads a character from standard input.
*
* Call this function to read a character from standard input.
*
* @return Returns the character read.
*/
int DbgConsole_Getchar(void);
#endif /* SDK_DEBUGCONSOLE */
/*! @} */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/*! @} */
#endif /* _FSL_DEBUGCONSOLE_H_ */
third_party/nxp/JN5189/libraries/libMicroSpecific_JN518x.a
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third_party/nxp/JN5189DK6/CMSIS/Include/arm_common_tables.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */
third_party/nxp/JN5189DK6/CMSIS/Include/arm_const_structs.h
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif
third_party/nxp/JN5189DK6/CMSIS/Include/arm_math.h
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return(result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */
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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
third_party/nxp/JN5189DK6/CMSIS/Include/core_cm0plus.h
Vendored Executable
+914
View File
@@ -0,0 +1,914 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex-M0+
@{
*/
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0+ header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
third_party/nxp/JN5189DK6/CMSIS/Include/core_cmInstr.h
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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */
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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */
third_party/nxp/JN5189DK6/CMSIS/Include/core_sc000.h
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/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup SC000
@{
*/
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000U
#warning "__SC000_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154U];
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the SC000 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of SC000 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
third_party/nxp/JN5189DK6/CMSIS/Include/core_sc300.h
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third_party/nxp/JN5189/dk6_jn5180/board.c → third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/board.c
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third_party/nxp/JN5189/dk6_jn5180/board.h → third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/board.h
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third_party/nxp/JN5189/dk6_jn5180/clock_config.c → third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.c
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#include "fsl_common.h"
#include "clock_config.h"
#include "system_JN5189.h"
/*******************************************************************************
* Definitions
******************************************************************************/
third_party/nxp/JN5189/dk6_jn5180/clock_config.h → third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/clock_config.h
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third_party/nxp/JN5189/dk6_jn5180/pin_mux.c → third_party/nxp/JN5189DK6/boards/jn5189dk6/wireless_examples/openthread/enablement/pin_mux.c
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third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.c
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third_party/nxp/JN5189DK6/components/serial_manager/serial_manager.h
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/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SERIAL_MANAGER_H__
#define __SERIAL_MANAGER_H__
/*!
* @addtogroup serialmanager
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
#else
#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
#endif
#endif
/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
#ifndef SERIAL_PORT_TYPE_UART
#define SERIAL_PORT_TYPE_UART (1U)
#endif
/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
#ifndef SERIAL_PORT_TYPE_USBCDC
#define SERIAL_PORT_TYPE_USBCDC (0U)
#endif
/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
#ifndef SERIAL_PORT_TYPE_SWO
#define SERIAL_PORT_TYPE_SWO (0U)
#endif
/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL
#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)
#endif
/*! @brief Set serial manager write handle size */
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
#else
#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
#endif
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
#include "serial_port_uart.h"
#endif
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#error The serial manager blocking mode cannot be supported for USB CDC.
#endif
#include "serial_port_usb.h"
#endif
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
#include "serial_port_swo.h"
#endif
#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#error The serial manager blocking mode cannot be supported for USB CDC.
#endif
#include "serial_port_usb_virtual.h"
#endif
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
#endif
#endif
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
#endif
#endif
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
#endif
#endif
#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE
#endif
#endif
/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
#else
#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.
#endif
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)
#else
#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
#endif
#define SERIAL_MANAGER_USE_COMMON_TASK (1U)
#define SERIAL_MANAGER_TASK_PRIORITY (2U)
#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
typedef void *serial_handle_t;
typedef void *serial_write_handle_t;
typedef void *serial_read_handle_t;
/*! @brief serial port type*/
typedef enum _serial_port_type
{
kSerialPort_Uart = 1U, /*!< Serial port UART */
kSerialPort_UsbCdc, /*!< Serial port USB CDC */
kSerialPort_Swo, /*!< Serial port SWO */
kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */
} serial_port_type_t;
/*! @brief serial manager config structure*/
typedef struct _serial_manager_config
{
uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.
Besides, the memory space cannot be free during the lifetime of the serial
manager module. */
uint32_t ringBufferSize; /*!< The size of the ring buffer */
serial_port_type_t type; /*!< Serial port type */
void *portConfig; /*!< Serial port configuration */
} serial_manager_config_t;
/*! @brief serial manager error code*/
typedef enum _serial_manager_status
{
kStatus_SerialManager_Success = kStatus_Success, /*!< Success */
kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
kStatus_SerialManager_Canceled =
MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
kStatus_SerialManager_RingBufferOverflow =
MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
} serial_manager_status_t;
/*! @brief Callback message structure */
typedef struct _serial_manager_callback_message
{
uint8_t *buffer; /*!< Transferred buffer */
uint32_t length; /*!< Transferred data length */
} serial_manager_callback_message_t;
/*! @brief callback function */
typedef void (*serial_manager_callback_t)(void *callbackParam,
serial_manager_callback_message_t *message,
serial_manager_status_t status);
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* _cplusplus */
/*!
* @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
*
* This function configures the Serial Manager module with user-defined settings. The user can configure the
* configuration
* structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
* allocated by the caller.
* The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB
* CDC.
* Please refer to #serial_port_type_t for serial port setting. These two types can be set by using
* #serial_manager_config_t.
*
* Example below shows how to use this API to configure the Serial Manager.
* For UART,
* @code
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
* static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
* static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
*
* serial_manager_config_t config;
* serial_port_uart_config_t uartConfig;
* config.type = kSerialPort_Uart;
* config.ringBuffer = &s_ringBuffer[0];
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
* uartConfig.instance = 0;
* uartConfig.clockRate = 24000000;
* uartConfig.baudRate = 115200;
* uartConfig.parityMode = kSerialManager_UartParityDisabled;
* uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
* uartConfig.enableRx = 1;
* uartConfig.enableTx = 1;
* config.portConfig = &uartConfig;
* SerialManager_Init(s_serialHandle, &config);
* @endcode
* For USB CDC,
* @code
* #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
* static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
* static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
* static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
*
* serial_manager_config_t config;
* serial_port_usb_cdc_config_t usbCdcConfig;
* config.type = kSerialPort_UsbCdc;
* config.ringBuffer = &s_ringBuffer[0];
* config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
* usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
* config.portConfig = &usbCdcConfig;
* SerialManager_Init(s_serialHandle, &config);
* @endcode
*
* @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
* @param config Pointer to user-defined configuration structure.
* @retval kStatus_SerialManager_Error An error occurred.
* @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
*/
serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);
/*!
* @brief De-initializes the serial manager module instance.
*
* This function de-initializes the serial manager module instance. If the opened writing or
* reading handle is not closed, the function will return kStatus_SerialManager_Busy.
*
* @param serialHandle The serial manager module handle pointer.
* @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
* @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
*/
serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
/*!
* @brief Opens a writing handle for the serial manager module.
*
* This function Opens a writing handle for the serial manager module. If the serial manager needs to
* be used in different tasks, the task should open a dedicated write handle for itself by calling
* #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
* handle at the same time, multiple writing handles need to be opened when the multiple transmission
* is needed for a task.
*
* @param serialHandle The serial manager module handle pointer.
* @param writeHandle The serial manager module writing handle pointer.
* @retval kStatus_SerialManager_Error An error occurred.
* @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
* @retval kStatus_SerialManager_Success The writing handle is opened.
*
* Example below shows how to use this API to write data.
* For task 1,
* @code
* static uint8_t s_serialWriteHandleBuffer1[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
* static serial_write_handle_t s_serialWriteHandle1 = &s_serialWriteHandleBuffer1[0];
* static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
* SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);
* SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);
* SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);
* @endcode
* For task 2,
* @code
* static uint8_t s_serialWriteHandleBuffer2[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
* static serial_write_handle_t s_serialWriteHandle2 = &s_serialWriteHandleBuffer2[0];
* static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
* SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);
* SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);
* SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);
* @endcode
*/
serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
/*!
* @brief Closes a writing handle for the serial manager module.
*
* This function Closes a writing handle for the serial manager module.
*
* @param writeHandle The serial manager module writing handle pointer.
* @retval kStatus_SerialManager_Success The writing handle is closed.
*/
serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
/*!
* @brief Opens a reading handle for the serial manager module.
*
* This function Opens a reading handle for the serial manager module. The reading handle can not be
* opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
* the previous reading handle is not closed. And There can only be one buffer for receiving for the
* reading handle at the same time.
*
* @param serialHandle The serial manager module handle pointer.
* @param readHandle The serial manager module reading handle pointer.
* @retval kStatus_SerialManager_Error An error occurred.
* @retval kStatus_SerialManager_Success The reading handle is opened.
* @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
*
* Example below shows how to use this API to read data.
* @code
* static uint8_t s_serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
* static serial_read_handle_t s_serialReadHandle = &s_serialReadHandleBuffer[0];
* SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);
* static uint8_t s_nonBlockingBuffer[64];
* SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);
* SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));
* @endcode
*/
serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
/*!
* @brief Closes a reading for the serial manager module.
*
* This function Closes a reading for the serial manager module.
*
* @param readHandle The serial manager module reading handle pointer.
* @retval kStatus_SerialManager_Success The reading handle is closed.
*/
serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
/*!
* @brief Transmits data with the blocking mode.
*
* This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
* This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
* And There can only one buffer for transmission for the writing handle at the same time.
*
* @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
* cannot be used at the same time.
* And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.
*
* @param writeHandle The serial manager module handle pointer.
* @param buffer Start address of the data to write.
* @param length Length of the data to write.
* @retval kStatus_SerialManager_Success Successfully sent all data.
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
* @retval kStatus_SerialManager_Error An error occurred.
*/
serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
uint8_t *buffer,
uint32_t length);
/*!
* @brief Reads data with the blocking mode.
*
* This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
* This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
* And There can only one buffer for receiving for the reading handle at the same time.
*
* @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
* cannot be used at the same time.
* And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.
*
* @param readHandle The serial manager module handle pointer.
* @param buffer Start address of the data to store the received data.
* @param length The length of the data to be received.
* @retval kStatus_SerialManager_Success Successfully received all data.
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
* @retval kStatus_SerialManager_Error An error occurred.
*/
serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
/*!
* @brief Transmits data with the non-blocking mode.
*
* This is a non-blocking function, which returns directly without waiting for all data to be sent.
* When all data is sent, the module notifies the upper layer through a TX callback function and passes
* the status parameter @ref kStatus_SerialManager_Success.
* This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
* And There can only one buffer for transmission for the writing handle at the same time.
*
* @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
* cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
*
* @param writeHandle The serial manager module handle pointer.
* @param buffer Start address of the data to write.
* @param length Length of the data to write.
* @retval kStatus_SerialManager_Success Successfully sent all data.
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
* @retval kStatus_SerialManager_Error An error occurred.
*/
serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
uint8_t *buffer,
uint32_t length);
/*!
* @brief Reads data with the non-blocking mode.
*
* This is a non-blocking function, which returns directly without waiting for all data to be received.
* When all data is received, the module driver notifies the upper layer
* through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
* This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
* And There can only one buffer for receiving for the reading handle at the same time.
*
* @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
* cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
*
* @param readHandle The serial manager module handle pointer.
* @param buffer Start address of the data to store the received data.
* @param length The length of the data to be received.
* @retval kStatus_SerialManager_Success Successfully received all data.
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
* @retval kStatus_SerialManager_Error An error occurred.
*/
serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
uint8_t *buffer,
uint32_t length);
/*!
* @brief Tries to read data.
*
* The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
* copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
* After the data is copied, the actual data length is passed by the parameter length.
* And There can only one buffer for receiving for the reading handle at the same time.
*
* @param readHandle The serial manager module handle pointer.
* @param buffer Start address of the data to store the received data.
* @param length The length of the data to be received.
* @param receivedLength Length received from the ring buffer directly.
* @retval kStatus_SerialManager_Success Successfully received all data.
* @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
* @retval kStatus_SerialManager_Error An error occurred.
*/
serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
uint8_t *buffer,
uint32_t length,
uint32_t *receivedLength);
/*!
* @brief Cancels unfinished send transmission.
*
* The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
* through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
*
* @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
* the function #SerialManager_WriteBlocking.
*
* @param writeHandle The serial manager module handle pointer.
* @retval kStatus_SerialManager_Success Get successfully abort the sending.
* @retval kStatus_SerialManager_Error An error occurred.
*/
serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
/*!
* @brief Cancels unfinished receive transmission.
*
* The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
* layer
* through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
*
* @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
* the function #SerialManager_ReadBlocking.
*
* @param readHandle The serial manager module handle pointer.
* @retval kStatus_SerialManager_Success Get successfully abort the receiving.
* @retval kStatus_SerialManager_Error An error occurred.
*/
serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
/*!
* @brief Installs a TX callback and callback parameter.
*
* This function is used to install the TX callback and callback parameter for the serial manager module.
* When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
* function. And the status is also passed as status parameter when the callback is called.
*
* @param writeHandle The serial manager module handle pointer.
* @param callback The callback function.
* @param callbackParam The parameter of the callback function.
* @retval kStatus_SerialManager_Success Successfully install the callback.
*/
serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
serial_manager_callback_t callback,
void *callbackParam);
/*!
* @brief Installs a RX callback and callback parameter.
*
* This function is used to install the RX callback and callback parameter for the serial manager module.
* When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
* function. And the status is also passed as status parameter when the callback is called.
*
* @param readHandle The serial manager module handle pointer.
* @param callback The callback function.
* @param callbackParam The parameter of the callback function.
* @retval kStatus_SerialManager_Success Successfully install the callback.
*/
serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
serial_manager_callback_t callback,
void *callbackParam);
#endif
/*!
* @brief Prepares to enter low power consumption.
*
* This function is used to prepare to enter low power consumption.
*
* @param serialHandle The serial manager module handle pointer.
* @retval kStatus_SerialManager_Success Successful operation.
*/
serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
/*!
* @brief Restores from low power consumption.
*
* This function is used to restore from low power consumption.
*
* @param serialHandle The serial manager module handle pointer.
* @retval kStatus_SerialManager_Success Successful operation.
*/
serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* __SERIAL_MANAGER_H__ */
third_party/nxp/JN5189DK6/components/serial_manager/serial_port_internal.h
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/*
* Copyright 2019 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SERIAL_PORT_INTERNAL_H__
#define __SERIAL_PORT_INTERNAL_H__
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* _cplusplus */
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
#endif
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam);
serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam);
void Serial_UartIsrFunction(serial_handle_t serialHandle);
#endif
#endif
#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam);
serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam);
void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
#endif
#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
#endif
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam);
serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam);
void Serial_SwoIsrFunction(serial_handle_t serialHandle);
#endif
#endif
#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config);
serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle);
serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle);
serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam);
serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam);
void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle);
#endif
#if defined(__cplusplus)
}
#endif
#endif /* __SERIAL_PORT_INTERNAL_H__ */
third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.c
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/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "serial_manager.h"
#include "serial_port_internal.h"
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
#include "uart.h"
#include "serial_port_uart.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#ifndef NDEBUG
#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
#undef assert
#define assert(n)
#endif
#endif
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
typedef struct _serial_uart_send_state
{
serial_manager_callback_t callback;
void *callbackParam;
uint8_t *buffer;
uint32_t length;
volatile uint8_t busy;
} serial_uart_send_state_t;
typedef struct _serial_uart_recv_state
{
serial_manager_callback_t callback;
void *callbackParam;
volatile uint8_t busy;
uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
} serial_uart_recv_state_t;
#endif
typedef struct _serial_uart_state
{
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serial_uart_send_state_t tx;
serial_uart_recv_state_t rx;
#endif
uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE];
} serial_uart_state_t;
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
/* UART user callback */
static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
{
serial_uart_state_t *serialUartHandle;
serial_manager_callback_message_t msg;
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
hal_uart_transfer_t transfer;
#endif
if (NULL == userData)
{
return;
}
serialUartHandle = (serial_uart_state_t *)userData;
if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
{
if ((NULL != serialUartHandle->rx.callback))
{
msg.buffer = &serialUartHandle->rx.readBuffer[0];
msg.length = sizeof(serialUartHandle->rx.readBuffer);
serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success);
}
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
transfer.data = &serialUartHandle->rx.readBuffer[0];
transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
if (kStatus_HAL_UartSuccess ==
HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
#else
if ((hal_uart_status_t)kStatus_HAL_UartSuccess ==
HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
&serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
#endif
{
serialUartHandle->rx.busy = 1U;
}
else
{
serialUartHandle->rx.busy = 0U;
}
}
else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
{
if (serialUartHandle->tx.busy != 0U)
{
serialUartHandle->tx.busy = 0U;
if ((NULL != serialUartHandle->tx.callback))
{
msg.buffer = serialUartHandle->tx.buffer;
msg.length = serialUartHandle->tx.length;
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success);
}
}
}
else
{
}
}
#endif
serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
{
serial_uart_state_t *serialUartHandle;
serial_port_uart_config_t *uartConfig;
hal_uart_config_t config;
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
hal_uart_transfer_t transfer;
#endif
#endif
assert(serialConfig);
assert(serialHandle);
assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
uartConfig = (serial_port_uart_config_t *)serialConfig;
serialUartHandle = (serial_uart_state_t *)serialHandle;
config.baudRate_Bps = uartConfig->baudRate;
config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode;
config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount;
config.enableRx = uartConfig->enableRx;
config.enableTx = uartConfig->enableTx;
config.srcClock_Hz = uartConfig->clockRate;
config.instance = uartConfig->instance;
if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config))
{
return kStatus_SerialManager_Error;
}
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
if (kStatus_HAL_UartSuccess !=
HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
Serial_UartCallback, serialUartHandle))
#else
if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
Serial_UartCallback, serialUartHandle))
#endif
{
return kStatus_SerialManager_Error;
}
if (uartConfig->enableRx != 0U)
{
serialUartHandle->rx.busy = 1U;
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
transfer.data = &serialUartHandle->rx.readBuffer[0];
transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
if (kStatus_HAL_UartSuccess !=
HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
#else
if (kStatus_HAL_UartSuccess !=
HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
&serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
#endif
{
serialUartHandle->rx.busy = 0U;
return kStatus_SerialManager_Error;
}
}
#endif
return kStatus_SerialManager_Success;
}
serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
{
serial_uart_state_t *serialUartHandle;
assert(serialHandle);
serialUartHandle = (serial_uart_state_t *)serialHandle;
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
(void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
#else
(void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
#endif
#endif
(void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serialUartHandle->tx.busy = 0U;
serialUartHandle->rx.busy = 0U;
#endif
return kStatus_SerialManager_Success;
}
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
{
serial_uart_state_t *serialUartHandle;
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
hal_uart_transfer_t transfer;
#endif
assert(serialHandle);
assert(buffer);
assert(length);
serialUartHandle = (serial_uart_state_t *)serialHandle;
if (serialUartHandle->tx.busy != 0U)
{
return kStatus_SerialManager_Busy;
}
serialUartHandle->tx.busy = 1U;
serialUartHandle->tx.buffer = buffer;
serialUartHandle->tx.length = length;
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
transfer.data = buffer;
transfer.dataSize = length;
if (kStatus_HAL_UartSuccess !=
HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
#else
if (kStatus_HAL_UartSuccess !=
HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length))
#endif
{
serialUartHandle->tx.busy = 0U;
return kStatus_SerialManager_Error;
}
return kStatus_SerialManager_Success;
}
#else
serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
{
serial_uart_state_t *serialUartHandle;
assert(serialHandle);
assert(buffer);
assert(length);
serialUartHandle = (serial_uart_state_t *)serialHandle;
return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
buffer, length);
}
serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
{
serial_uart_state_t *serialUartHandle;
assert(serialHandle);
assert(buffer);
assert(length);
serialUartHandle = (serial_uart_state_t *)serialHandle;
return (serial_manager_status_t)HAL_UartReceiveBlocking(
((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
}
#endif
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
{
serial_uart_state_t *serialUartHandle;
serial_manager_callback_message_t msg;
uint32_t primask;
uint8_t isBusy = 0U;
assert(serialHandle);
serialUartHandle = (serial_uart_state_t *)serialHandle;
primask = DisableGlobalIRQ();
isBusy = serialUartHandle->tx.busy;
serialUartHandle->tx.busy = 0U;
EnableGlobalIRQ(primask);
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
(void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
#else
(void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
#endif
if (isBusy != 0U)
{
if ((NULL != serialUartHandle->tx.callback))
{
msg.buffer = serialUartHandle->tx.buffer;
msg.length = serialUartHandle->tx.length;
serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled);
}
}
return kStatus_SerialManager_Success;
}
serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam)
{
serial_uart_state_t *serialUartHandle;
assert(serialHandle);
serialUartHandle = (serial_uart_state_t *)serialHandle;
serialUartHandle->tx.callback = callback;
serialUartHandle->tx.callbackParam = callbackParam;
return kStatus_SerialManager_Success;
}
serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
serial_manager_callback_t callback,
void *callbackParam)
{
serial_uart_state_t *serialUartHandle;
assert(serialHandle);
serialUartHandle = (serial_uart_state_t *)serialHandle;
serialUartHandle->rx.callback = callback;
serialUartHandle->rx.callbackParam = callbackParam;
return kStatus_SerialManager_Success;
}
void Serial_UartIsrFunction(serial_handle_t serialHandle)
{
serial_uart_state_t *serialUartHandle;
assert(serialHandle);
serialUartHandle = (serial_uart_state_t *)serialHandle;
HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
}
#endif
#endif
third_party/nxp/JN5189DK6/components/serial_manager/serial_port_uart.h
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/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SERIAL_PORT_UART_H__
#define __SERIAL_PORT_UART_H__
/*!
* @addtogroup serial_port_uart
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief serial port uart handle size*/
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
#define SERIAL_PORT_UART_HANDLE_SIZE (166U)
#else
#define SERIAL_PORT_UART_HANDLE_SIZE (4U)
#endif
/*! @brief serial port uart parity mode*/
typedef enum _serial_port_uart_parity_mode
{
kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */
kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */
} serial_port_uart_parity_mode_t;
/*! @brief serial port uart stop bit count*/
typedef enum _serial_port_uart_stop_bit_count
{
kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
} serial_port_uart_stop_bit_count_t;
/*! @brief serial port uart config struct*/
typedef struct _serial_port_uart_config
{
uint32_t clockRate; /*!< clock rate */
uint32_t baudRate; /*!< baud rate */
serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
please refer to the SOC corresponding RM. */
uint8_t enableRx; /*!< Enable RX */
uint8_t enableTx; /*!< Enable TX */
} serial_port_uart_config_t;
/*! @} */
#endif /* __SERIAL_PORT_UART_H__ */
third_party/nxp/JN5189DK6/components/uart/uart.h
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/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __HAL_UART_ADAPTER_H__
#define __HAL_UART_ADAPTER_H__
#if defined(FSL_RTOS_FREE_RTOS)
#include "FreeRTOS.h"
#endif
/*!
* @addtogroup UART_Adapter
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
#else
#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
#else
#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
#endif
#endif
#if defined(__GIC_PRIO_BITS)
#define HAL_UART_ISR_PRIORITY (25U)
#else
#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
#else
/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
* The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
* priority is 3 (2^2 - 1). So, the default value is 3.
*/
#define HAL_UART_ISR_PRIORITY (3U)
#endif
#endif
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
#define HAL_UART_HANDLE_SIZE (90U)
#else
#define HAL_UART_HANDLE_SIZE (4U)
#endif
/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
#define HAL_UART_TRANSFER_MODE (0U)
typedef void *hal_uart_handle_t;
/*! @brief UART status */
typedef enum _hal_uart_status
{
kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
kStatus_HAL_UartBaudrateNotSupport =
MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
kStatus_HAL_UartProtocolError = MAKE_STATUS(
kStatusGroup_HAL_UART,
6), /*!< Error occurs for Noise, Framing, Parity, etc.
For transactional transfer, The up layer needs to abort the transfer and then starts again */
kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
} hal_uart_status_t;
/*! @brief UART parity mode. */
typedef enum _hal_uart_parity_mode
{
kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */
kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */
} hal_uart_parity_mode_t;
/*! @brief UART stop bit count. */
typedef enum _hal_uart_stop_bit_count
{
kHAL_UartOneStopBit = 0U, /*!< One stop bit */
kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
} hal_uart_stop_bit_count_t;
/*! @brief UART configuration structure. */
typedef struct _hal_uart_config
{
uint32_t srcClock_Hz; /*!< Source clock */
uint32_t baudRate_Bps; /*!< Baud rate */
hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
uint8_t enableRx; /*!< Enable RX */
uint8_t enableTx; /*!< Enable TX */
uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
SOC corresponding RM.
Invalid instance value will cause initialization failure. */
} hal_uart_config_t;
/*! @brief UART transfer callback function. */
typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
/*! @brief UART transfer structure. */
typedef struct _hal_uart_transfer
{
uint8_t *data; /*!< The buffer of data to be transfer.*/
size_t dataSize; /*!< The byte count to be transfer. */
} hal_uart_transfer_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* _cplusplus */
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief Initializes a UART instance with the UART handle and the user configuration structure.
*
* This function configures the UART module with user-defined settings. The user can configure the configuration
* structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
* the caller. Example below shows how to use this API to configure the UART.
* @code
* uint8_t g_UartHandleBuffer[HAL_UART_HANDLE_SIZE];
* hal_uart_handle_t g_UartHandle = &g_UartHandleBuffer[0];
* hal_uart_config_t config;
* config.srcClock_Hz = 48000000;
* config.baudRate_Bps = 115200U;
* config.parityMode = kHAL_UartParityDisabled;
* config.stopBitCount = kHAL_UartOneStopBit;
* config.enableRx = 1;
* config.enableTx = 1;
* config.instance = 0;
* HAL_UartInit(g_UartHandle, &config);
* @endcode
*
* @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
* @param config Pointer to user-defined configuration structure.
* @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
* @retval kStatus_HAL_UartSuccess UART initialization succeed
*/
hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config);
/*!
* @brief Deinitializes a UART instance.
*
* This function waits for TX complete, disables TX and RX, and disables the UART clock.
*
* @param handle UART handle pointer.
* @retval kStatus_HAL_UartSuccess UART de-initialization succeed
*/
hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
/*! @}*/
/*!
* @name Blocking bus Operations
* @{
*/
/*!
* @brief Reads RX data register using a blocking method.
*
* This function polls the RX register, waits for the RX register to be full or for RX FIFO to
* have data, and reads data from the RX register.
*
* @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
* cannot be used at the same time.
* And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
*
* @param handle UART handle pointer.
* @param data Start address of the buffer to store the received data.
* @param length Size of the buffer.
* @retval kStatus_HAL_UartError An error occurred while receiving data.
* @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
* @retval kStatus_HAL_UartSuccess Successfully received all data.
*/
hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
/*!
* @brief Writes to the TX register using a blocking method.
*
* This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
* to have room and writes data to the TX buffer.
*
* @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
* cannot be used at the same time.
* And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
*
* @param handle UART handle pointer.
* @param data Start address of the data to write.
* @param length Size of the data to write.
* @retval kStatus_HAL_UartSuccess Successfully sent all data.
*/
hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
/*! @}*/
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
/*!
* @name Transactional
* @note The transactional API and the functional API cannot be used at the same time. The macro
* #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
* functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
* @{
*/
/*!
* @brief Installs a callback and callback parameter.
*
* This function is used to install the callback and callback parameter for UART module.
* When any status of the UART changed, the driver will notify the upper layer by the installed callback
* function. And the status is also passed as status parameter when the callback is called.
*
* @param handle UART handle pointer.
* @param callback The callback function.
* @param callbackParam The parameter of the callback function.
* @retval kStatus_HAL_UartSuccess Successfully install the callback.
*/
hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
hal_uart_transfer_callback_t callback,
void *callbackParam);
/*!
* @brief Receives a buffer of data using an interrupt method.
*
* This function receives data using an interrupt method. This is a non-blocking function, which
* returns directly without waiting for all data to be received.
* The receive request is saved by the UART driver.
* When the new data arrives, the receive request is serviced first.
* When all data is received, the UART driver notifies the upper layer
* through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
*
* @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
* cannot be used at the same time.
*
* @param handle UART handle pointer.
* @param transfer UART transfer structure, see #hal_uart_transfer_t.
* @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
* @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
* @retval kStatus_HAL_UartError An error occurred.
*/
hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
/*!
* @brief Transmits a buffer of data using the interrupt method.
*
* This function sends data using an interrupt method. This is a non-blocking function, which
* returns directly without waiting for all data to be written to the TX register. When
* all data is written to the TX register in the ISR, the UART driver calls the callback
* function and passes the @ref kStatus_UART_TxIdle as status parameter.
*
* @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
* cannot be used at the same time.
*
* @param handle UART handle pointer.
* @param transfer UART transfer structure. See #hal_uart_transfer_t.
* @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
* @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
* @retval kStatus_HAL_UartError An error occurred.
*/
hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
/*!
* @brief Gets the number of bytes that have been received.
*
* This function gets the number of bytes that have been received.
*
* @param handle UART handle pointer.
* @param count Receive bytes count.
* @retval kStatus_HAL_UartError An error occurred.
* @retval kStatus_Success Get successfully through the parameter \p count.
*/
hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
/*!
* @brief Gets the number of bytes written to the UART TX register.
*
* This function gets the number of bytes written to the UART TX
* register by using the interrupt method.
*
* @param handle UART handle pointer.
* @param count Send bytes count.
* @retval kStatus_HAL_UartError An error occurred.
* @retval kStatus_Success Get successfully through the parameter \p count.
*/
hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
/*!
* @brief Aborts the interrupt-driven data receiving.
*
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
* how many bytes are not received yet.
*
* @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
* the function #HAL_UartReceiveBlocking.
*
* @param handle UART handle pointer.
* @retval kStatus_Success Get successfully abort the receiving.
*/
hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
/*!
* @brief Aborts the interrupt-driven data sending.
*
* This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
* how many bytes are not sent out.
*
* @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
* the function #HAL_UartSendBlocking.
*
* @param handle UART handle pointer.
* @retval kStatus_Success Get successfully abort the sending.
*/
hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
/*! @}*/
#else
/*!
* @name Functional API with non-blocking mode.
* @note The functional API and the transactional API cannot be used at the same time. The macro
* #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
* functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
* @{
*/
/*!
* @brief Installs a callback and callback parameter.
*
* This function is used to install the callback and callback parameter for UART module.
* When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
* function. And the status is also passed as status parameter when the callback is called.
*
* @param handle UART handle pointer.
* @param callback The callback function.
* @param callbackParam The parameter of the callback function.
* @retval kStatus_HAL_UartSuccess Successfully install the callback.
*/
hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
hal_uart_transfer_callback_t callback,
void *callbackParam);
/*!
* @brief Receives a buffer of data using an interrupt method.
*
* This function receives data using an interrupt method. This is a non-blocking function, which
* returns directly without waiting for all data to be received.
* The receive request is saved by the UART adapter.
* When the new data arrives, the receive request is serviced first.
* When all data is received, the UART adapter notifies the upper layer
* through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
*
* @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
* cannot be used at the same time.
*
* @param handle UART handle pointer.
* @param data Start address of the data to write.
* @param length Size of the data to write.
* @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
* @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
* @retval kStatus_HAL_UartError An error occurred.
*/
hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
/*!
* @brief Transmits a buffer of data using the interrupt method.
*
* This function sends data using an interrupt method. This is a non-blocking function, which
* returns directly without waiting for all data to be written to the TX register. When
* all data is written to the TX register in the ISR, the UART driver calls the callback
* function and passes the @ref kStatus_UART_TxIdle as status parameter.
*
* @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
* cannot be used at the same time.
*
* @param handle UART handle pointer.
* @param data Start address of the data to write.
* @param length Size of the data to write.
* @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
* @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
* @retval kStatus_HAL_UartError An error occurred.
*/
hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
/*!
* @brief Gets the number of bytes that have been received.
*
* This function gets the number of bytes that have been received.
*
* @param handle UART handle pointer.
* @param count Receive bytes count.
* @retval kStatus_HAL_UartError An error occurred.
* @retval kStatus_Success Get successfully through the parameter \p count.
*/
hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
/*!
* @brief Gets the number of bytes written to the UART TX register.
*
* This function gets the number of bytes written to the UART TX
* register by using the interrupt method.
*
* @param handle UART handle pointer.
* @param count Send bytes count.
* @retval kStatus_HAL_UartError An error occurred.
* @retval kStatus_Success Get successfully through the parameter \p count.
*/
hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
/*!
* @brief Aborts the interrupt-driven data receiving.
*
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
* how many bytes are not received yet.
*
* @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
* the function #HAL_UartReceiveBlocking.
*
* @param handle UART handle pointer.
* @retval kStatus_Success Get successfully abort the receiving.
*/
hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
/*!
* @brief Aborts the interrupt-driven data sending.
*
* This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
* how many bytes are not sent out.
*
* @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
* the function #HAL_UartSendBlocking.
*
* @param handle UART handle pointer.
* @retval kStatus_Success Get successfully abort the sending.
*/
hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
/*! @}*/
#endif
#endif
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
/*!
* @brief UART IRQ handle function.
*
* This function handles the UART transmit and receive IRQ request.
*
* @param handle UART handle pointer.
*/
void HAL_UartIsrFunction(hal_uart_handle_t handle);
#endif
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* __HAL_UART_ADAPTER_H__ */
third_party/nxp/JN5189DK6/components/uart/usart_adapter.c
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/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_usart.h"
#include "fsl_flexcomm.h"
#include "uart.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#ifndef NDEBUG
#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
#undef assert
#define assert(n)
#endif
#endif
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
/*! @brief uart RX state structure. */
typedef struct _hal_uart_receive_state
{
volatile uint8_t *buffer;
volatile uint32_t bufferLength;
volatile uint32_t bufferSofar;
} hal_uart_receive_state_t;
/*! @brief uart TX state structure. */
typedef struct _hal_uart_send_state
{
volatile uint8_t *buffer;
volatile uint32_t bufferLength;
volatile uint32_t bufferSofar;
} hal_uart_send_state_t;
#endif
/*! @brief uart state structure. */
typedef struct _hal_uart_state
{
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
hal_uart_transfer_callback_t callback;
void *callbackParam;
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
usart_handle_t hardwareHandle;
#endif
hal_uart_receive_state_t rx;
hal_uart_send_state_t tx;
#endif
uint8_t instance;
} hal_uart_state_t;
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
/* Array of USART IRQ number. */
static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
#endif
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
static hal_uart_status_t HAL_UartGetStatus(status_t status)
{
hal_uart_status_t uartStatus = kStatus_HAL_UartError;
switch (status)
{
case kStatus_Success:
uartStatus = kStatus_HAL_UartSuccess;
break;
case kStatus_USART_TxBusy:
uartStatus = kStatus_HAL_UartTxBusy;
break;
case kStatus_USART_RxBusy:
uartStatus = kStatus_HAL_UartRxBusy;
break;
case kStatus_USART_TxIdle:
uartStatus = kStatus_HAL_UartTxIdle;
break;
case kStatus_USART_RxIdle:
uartStatus = kStatus_HAL_UartRxIdle;
break;
case kStatus_USART_BaudrateNotSupport:
uartStatus = kStatus_HAL_UartBaudrateNotSupport;
break;
case kStatus_USART_NoiseError:
case kStatus_USART_FramingError:
case kStatus_USART_ParityError:
uartStatus = kStatus_HAL_UartProtocolError;
break;
default:
break;
}
return uartStatus;
}
#else
static hal_uart_status_t HAL_UartGetStatus(status_t status)
{
if (kStatus_Success == status)
{
return kStatus_HAL_UartSuccess;
}
else
{
return kStatus_HAL_UartError;
}
}
#endif
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
{
hal_uart_state_t *uartHandle;
hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
assert(callbackParam);
uartHandle = (hal_uart_state_t *)callbackParam;
if (kStatus_HAL_UartProtocolError == uartStatus)
{
if (uartHandle->hardwareHandle.rxDataSize)
{
uartStatus = kStatus_HAL_UartError;
}
}
if (uartHandle->callback)
{
uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
}
}
#else
static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
{
hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
uint32_t status;
uint8_t instance;
if (NULL == uartHandle)
{
return;
}
instance = uartHandle->instance;
status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
/* Receive data register full */
if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) &&
(USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))
{
if (uartHandle->rx.buffer)
{
uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
{
USART_DisableInterrupts(s_UsartAdapterBase[instance],
USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
uartHandle->rx.buffer = NULL;
if (uartHandle->callback)
{
uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
}
}
}
}
/* Send data register empty and the interrupt is enabled. */
if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) &&
(USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))
{
if (uartHandle->tx.buffer)
{
USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
{
USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
uartHandle->tx.buffer = NULL;
if (uartHandle->callback)
{
uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
}
}
}
}
#if 1
USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
#endif
}
#endif
#endif
hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config)
{
hal_uart_state_t *uartHandle;
usart_config_t usartConfig;
status_t status;
assert(handle);
assert(config);
assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
assert(s_UsartAdapterBase[config->instance]);
if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t))
{
return kStatus_HAL_UartError;
}
USART_GetDefaultConfig(&usartConfig);
usartConfig.baudRate_Bps = config->baudRate_Bps;
if (kHAL_UartParityEven == config->parityMode)
{
usartConfig.parityMode = kUSART_ParityEven;
}
else if (kHAL_UartParityOdd == config->parityMode)
{
usartConfig.parityMode = kUSART_ParityOdd;
}
else
{
usartConfig.parityMode = kUSART_ParityDisabled;
}
if (kHAL_UartTwoStopBit == config->stopBitCount)
{
usartConfig.stopBitCount = kUSART_TwoStopBit;
}
else
{
usartConfig.stopBitCount = kUSART_OneStopBit;
}
usartConfig.enableRx = config->enableRx;
usartConfig.enableTx = config->enableTx;
usartConfig.txWatermark = kUSART_TxFifo0;
usartConfig.rxWatermark = kUSART_RxFifo1;
status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
if (kStatus_Success != status)
{
return HAL_UartGetStatus(status);
}
uartHandle = (hal_uart_state_t *)handle;
uartHandle->instance = config->instance;
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,
(usart_transfer_callback_t)HAL_UartCallback, handle);
#else
/* Enable interrupt in NVIC. */
FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle,
handle);
NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
EnableIRQ(s_UsartIRQ[config->instance]);
#endif
#endif
return kStatus_HAL_UartSuccess;
}
hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
{
hal_uart_state_t *uartHandle;
assert(handle);
uartHandle = (hal_uart_state_t *)handle;
USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
return kStatus_HAL_UartSuccess;
}
hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
{
hal_uart_state_t *uartHandle;
status_t status;
assert(handle);
assert(data);
assert(length);
uartHandle = (hal_uart_state_t *)handle;
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
if (uartHandle->rx.buffer)
{
return kStatus_HAL_UartRxBusy;
}
#endif
status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
return HAL_UartGetStatus(status);
}
hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(data);
assert(length);
uartHandle = (hal_uart_state_t *)handle;
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
if (uartHandle->tx.buffer)
{
return kStatus_HAL_UartTxBusy;
}
#endif
USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
return kStatus_HAL_UartSuccess;
}
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
hal_uart_transfer_callback_t callback,
void *callbackParam)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
uartHandle->callbackParam = callbackParam;
uartHandle->callback = callback;
return kStatus_HAL_UartSuccess;
}
hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
{
hal_uart_state_t *uartHandle;
status_t status;
assert(handle);
assert(transfer);
assert(HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
(usart_transfer_t *)transfer, NULL);
return HAL_UartGetStatus(status);
}
hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
{
hal_uart_state_t *uartHandle;
status_t status;
assert(handle);
assert(transfer);
assert(HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
(usart_transfer_t *)transfer);
return HAL_UartGetStatus(status);
}
hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
{
hal_uart_state_t *uartHandle;
status_t status;
assert(handle);
assert(count);
assert(HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
status =
USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
return HAL_UartGetStatus(status);
}
hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
{
hal_uart_state_t *uartHandle;
status_t status;
assert(handle);
assert(count);
assert(HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
return HAL_UartGetStatus(status);
}
hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
return kStatus_HAL_UartSuccess;
}
hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
return kStatus_HAL_UartSuccess;
}
#else
/* None transactional API with non-blocking mode. */
hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
hal_uart_transfer_callback_t callback,
void *callbackParam)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(!HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
uartHandle->callbackParam = callbackParam;
uartHandle->callback = callback;
return kStatus_HAL_UartSuccess;
}
hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(data);
assert(length);
assert(!HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
if (uartHandle->rx.buffer)
{
return kStatus_HAL_UartRxBusy;
}
uartHandle->rx.bufferLength = length;
uartHandle->rx.bufferSofar = 0;
uartHandle->rx.buffer = data;
USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
return kStatus_HAL_UartSuccess;
}
hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(data);
assert(length);
assert(!HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
if (uartHandle->tx.buffer)
{
return kStatus_HAL_UartTxBusy;
}
uartHandle->tx.bufferLength = length;
uartHandle->tx.bufferSofar = 0;
uartHandle->tx.buffer = (volatile uint8_t *)data;
USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
return kStatus_HAL_UartSuccess;
}
hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(reCount);
assert(!HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
if (uartHandle->rx.buffer)
{
*reCount = uartHandle->rx.bufferSofar;
return kStatus_HAL_UartSuccess;
}
return kStatus_HAL_UartError;
}
hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(seCount);
assert(!HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
if (uartHandle->tx.buffer)
{
*seCount = uartHandle->tx.bufferSofar;
return kStatus_HAL_UartSuccess;
}
return kStatus_HAL_UartError;
}
hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(!HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
if (uartHandle->rx.buffer)
{
USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
uartHandle->rx.buffer = NULL;
}
return kStatus_HAL_UartSuccess;
}
hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(!HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
if (uartHandle->tx.buffer)
{
USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
uartHandle->tx.buffer = NULL;
}
return kStatus_HAL_UartSuccess;
}
#endif
#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
void HAL_UartIsrFunction(hal_uart_handle_t handle)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
#if 0
DisableIRQ(s_UsartIRQ[uartHandle->instance]);
#endif
USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
#if 0
NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
EnableIRQ(s_UsartIRQ[uartHandle->instance]);
#endif
}
#else
void HAL_UartIsrFunction(hal_uart_handle_t handle)
{
hal_uart_state_t *uartHandle;
assert(handle);
assert(!HAL_UART_TRANSFER_MODE);
uartHandle = (hal_uart_state_t *)handle;
#if 0
DisableIRQ(s_UsartIRQ[uartHandle->instance]);
#endif
HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
#if 0
NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
EnableIRQ(s_UsartIRQ[uartHandle->instance]);
#endif
}
#endif
#endif
third_party/nxp/JN5189/JN5189.h → third_party/nxp/JN5189DK6/devices/JN5189/JN5189.h
Vendored
+185 -645
View File
File diff suppressed because it is too large Load Diff
third_party/nxp/JN5189/JN5189_features.h → third_party/nxp/JN5189DK6/devices/JN5189/JN5189_features.h
Vendored
+187 -165
View File
@@ -1,13 +1,14 @@
/*
** ###################################################################
** Version: rev. 1.0, 2016-05-09
** Build: b160714
** Version: rev. 1.0, 2018-07-31
** Build: b191225
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
@@ -15,206 +16,227 @@
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2016-05-09)
** - rev. 1.0 (2018-07-31)
** Initial version.
**
** ###################################################################
*/
#ifndef _JN518X_FEATURES_H_
#define _JN518X_FEATURES_H_
#ifndef _JN5189_FEATURES_H_
#define _JN5189_FEATURES_H_
/* SOC module features */
/* @brief ADC availability on the SoC. */
#define FSL_FEATURE_SOC_ADC_COUNT (1)
/* @brief AES availability on the SoC. */
#define FSL_FEATURE_SOC_AES_COUNT (1)
/* @brief ASYNC_SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief CIC_IRB availability on the SoC. */
#define FSL_FEATURE_SOC_CIC_IRB_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (2)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (1)
/* @brief Number of DMA channels on the SOC. */
/* @brief DMIC availability on the SoC. */
#define FSL_FEATURE_SOC_DMIC_COUNT (1)
/* @brief FLASH availability on the SoC. */
#define FSL_FEATURE_SOC_FLASH_COUNT (1)
/* @brief FLEXCOMM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (7)
/* @brief GINT availability on the SoC. */
#define FSL_FEATURE_SOC_GINT_COUNT (1)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (3)
/* @brief INPUTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
/* @brief IOCON availability on the SoC. */
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
/* @brief LPC_GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_GPIO_COUNT (1)
/* @brief LPC_RTC availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_RTC_COUNT (1)
/* @brief PINT availability on the SoC. */
#define FSL_FEATURE_SOC_PINT_COUNT (1)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (1)
/* @brief PWM availability on the SoC. */
#define FSL_FEATURE_SOC_PWM_COUNT (1)
/* @brief SHA availability on the SoC. */
#define FSL_FEATURE_SOC_SHA_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (2)
/* @brief SPIFI availability on the SoC. */
#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
/* @brief TRNG availability on the SoC. */
#define FSL_FEATURE_SOC_TRNG_COUNT (1)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (2)
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
/* ADC module features */
/* @brief ADC data alignment mode. */
#define FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT (1)
/* @brief ADC data alignment mode. */
#define FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL (1)
/* @brief Has no Calibration function. */
#define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1)
/* @brief ADC has single SEQ. */
#define FSL_FEATURE_ADC_HAS_SINGLE_SEQ (1)
/* @brief Has ADC_INIT bitfile in STARTUP register. */
#define FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT (0)
/* @brief Has OFFSET_CAL bitfile in GPADC_CTRL1 reigster. */
#define FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL (1)
/* @brief Has LDO_POWER_EN bitfile in GPADC_CTRL0 reigster. */
#define FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN (1)
/* @brief ADC require a delay. */
#define FSL_FEATURE_ADC_REQUIRE_DELAY (1)
/* @brief ADC TEMPSENSORCTRL in ASYNC_SYSCON. */
#define FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
/* @brief Has ADTrim register */
#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
/* @brief Has Calibration register. */
#define FSL_FEATURE_ADC_HAS_CALIB_REG (0)
/* ASYNC_SYSCON module features */
/* @brief FMEAS FMEAS_INDEX is 20. */
#define FSL_FEATURE_FMEAS_INDEX_20 (1)
/* @brief FMEAS FREQMECTRL in ASYNC_SYSCON. */
#define FSL_FEATURE_FMEAS_ASYNC_SYSCON_FREQMECTRL (1)
/* @brief FMEAS SYSCON use ASYNC_SYSCON. */
#define FSL_FEATURE_FMEAS_USE_ASYNC_SYSCON (1)
/* @brief FMEAS start frequency with ASYNC_SYSCON. */
#define FSL_FEATURE_FMEAS_START_FRG_ASYNC_SYSCON (1)
/* @brief FMEAS get frequency with ASYNC_SYSCON. */
#define FSL_FEATURE_FMEAS_GET_FRG_ASYNC_SYSCON (1)
/* @brief FMEAS get clock count with scale. */
#define FSL_FEATURE_FMEAS_GET_COUNT_SCALE (1)
/* @brief FMEAS start measure with scale. */
#define FSL_FEATURE_FMEAS_STARTMEAS_SCALE (1)
/* CTIMER module features */
/* @brief CTIMER capture 3 interrupt. */
#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
/* @brief CTIMER has no capture channel. */
#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (1)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (19)
/* @brief Align size of DMA descriptor */
#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
/* @brief DMA head link descriptor table align size */
#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
/* @brief DMIC availability on the SoC. */
#define FSL_FEATURE_SOC_DMIC_COUNT (1)
/* @brief FLEXCOMM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (7)
/* @brief GINT availability on the SoC. */
#define FSL_FEATURE_SOC_GINT_COUNT (1)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_GPIO_COUNT (1)
#define FSL_FEATURE_SOC_GPIO_COUNT FSL_FEATURE_SOC_LPC_GPIO_COUNT
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (3)
/* @brief I2C are FLEXCOMM on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_I2C_COUNT FSL_FEATURE_SOC_I2C_COUNT
/* @brief INPUTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
/* @brief IOCON availability on the SoC. */
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
/* @brief MAILBOX availability on the SoC. */
#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
/* @brief MRT availability on the SoC. */
#define FSL_FEATURE_SOC_MRT_COUNT (1)
/* @brief PINT availability on the SoC. */
#define FSL_FEATURE_SOC_PINT_COUNT (1)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_RTC_COUNT (1)
/* @brief SCT availability on the SoC. */
#define FSL_FEATURE_SOC_SCT_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (2)
/* @brief SPI are FLEXCOMM on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_SPI_COUNT FSL_FEATURE_SOC_SPI_COUNT
/* @brief SPIFI availability on the SoC. */
#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (2)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (2)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_USART_COUNT FSL_FEATURE_SOC_USART_COUNT
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
/* @brief IRB availability on the SoC. */
#define FSL_FEATURE_SOC_CIC_IRB_COUNT (1)
/* @brief reduced functionality FLEXCOMM for low power JN518x family */
#define FSL_REDUCED_FUNCTION_FLEXCOMM
/* @brief PWM availability on the Soc */
#define FSL_FEATURE_SOC_PWM_COUNT (10)
/* @brief HASH/SHA availability on the SoC. */
#define FSL_FEATURE_SOC_SHA_COUNT (1)
/* @brief AES availability on the SoC. */
#define FSL_FEATURE_SOC_AES_COUNT (1)
/* @brief RNG availability on the SoC. */
#define FSL_FEATURE_SOC_TRNG_COUNT (1)
/* SPIFI module features */
/* @brief SPIFI start address */
#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
/* @brief SPIFI end address */
#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
/* @brief SPIFI DATALEN bitfile in CMD register*/
#define FSL_FEATURE_SPIFI_DATALEN_CTRL (1)
/* @brief Pointer to ROM IAP entry functions */
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
/* PINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
/* @brief Number of PIOs */
#define FSL_FEATURE_GPIO_PIO_COUNT (22)
/* PMC module features */
/* @brief FRO1M trim address */
#define FSL_FEATURE_PMC_FRO1M_ADDRESS (0x9FCD0U)
/* @brief FRO1M trim valid mask */
#define FSL_FEATURE_PMC_FRO1M_VALID_MASK (0x1U)
/* SPI module features */
/* @brief SPI SIZE bitfile in FIFOCFG register */
#define FSL_FEATURE_SPI_FIFOSIZE_CFG (1)
/* @brief SPI has only three SSEL pins */
#define FSL_FEATURE_IS_SPI_SSEL_PIN_COUNT_EQUAL_TO_THREE (1)
/* ADC module features */
/* @brief ADC data alignment mode */
#define FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT (1)
/* @brief ADC synchronous mode do not modify CTRL.TSAMP [14:12] */
#define FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL (1)
/* @brief ADC temp cal flash addr */
#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL (0x9FC80)
/* @brief ADC temp cal flash data vaild mask*/
#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID (0x1)
/* @brief Has ASYNMODE bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
/* @brief Has RESOL bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
/* @brief Has BYPASSCAL bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0)
/* @brief Has TSAMP bitfile in CTRL reigster. */
#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
/* @brief ADC NO calibration*/
#define FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC (1)
/* @brief ADC TEMPSENSORCTRL in ASYNC_SYSCON*/
#define FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP (1)
/* @brief ADC require a delay*/
#define FSL_FEATURE_ADC_REQUIRE_DELAY (1)
/* @brief Has LDO_POWER_EN bitfile in GPADC_CTRL0 register. */
#define FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN (1)
/* @brief Has OFFSET_CAL bitfile in GPADC_CTRL1 register. */
#define FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL (1)
/* @brief Has ADC_INIT bitfile in STARTUP register. */
#define FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT (0)
/* @brief ADC has single SEQ */
#define FSL_FEATURE_ADC_HAS_SINGLE_SEQ (1)
/* SYSCON module features */
/* FLASH module features */
/* @brief P-Flash write unit size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (512U)
/* @brief P-Flash sector size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (512U)
/* @brief P-Flash block count */
/* @brief P-Flash block count. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
/* @brief P-Flash block size. */
#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0xA0000U)
/* @brief ADC temp cal flash addr. */
#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL (0x9FC80)
/* @brief ADC temp cal flash data vaild mask. */
#define FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID (0x1)
/* CTIMER module features */
/* @brief CTIMER capture channel 3. */
#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
/* @brief CTIMER capture 3 interrupt. */
#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
/* FLEXCOMM module features */
/* WWDT module features */
/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (1)
/* @brief WWDT NO PDCFG*/
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
/* @brief Has no reset in FLEXCOMM register. */
#define FSL_FEATURE_FLEXCOMM_HAS_NO_RESET (1)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_USART_COUNT (FSL_FEATURE_SOC_USART_COUNT)
/* @brief SPI are FLEXCOMM on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_SPI_COUNT (FSL_FEATURE_SOC_SPI_COUNT)
/* @brief I2C are FLEXCOMM on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_I2C_COUNT (FSL_FEATURE_SOC_I2C_COUNT)
/* GPIO module features */
/* @brief GPIO DIRSET and DIRCLR register. */
#define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1)
/* @brief Number of PIOs. */
#define FSL_FEATURE_GPIO_PIO_COUNT (22)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (FSL_FEATURE_SOC_LPC_GPIO_COUNT)
/* I2C module features */
/* @brief I2C peripheral clock frequency 8MHz */
/* @brief I2C peripheral clock frequency 8MHz. */
#define FSL_FEATURE_I2C_PREPCLKFRG_8MHZ (1)
/* GPIO module feature */
/* @brief GPIO DIRSET and DIRCLR register */
#define FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR (1)
/* IOCON module features */
/* FMEAS module feature */
/* @brief FMEAS FMEAS_INDEX is 20 */
#define FSL_FEATURE_FMEAS_INDEX_20 (1)
/* @brief FMEAS FREQMECTRL in ASYNC_SYSCON */
#define FSL_FEATURE_FMEAS_ASYNC_SYSCON_FREQMECTRL (1)
/* @brief FMEAS SYSCON use ASYNC_SYSCON */
#define FSL_FEATURE_FMEAS_USE_ASYNC_SYSCON (1)
/* @brief FMEAS start frequency with ASYNC_SYSCON */
#define FSL_FEATURE_FMEAS_START_FRG_ASYNC_SYSCON (1)
/* @brief FMEAS get frequency with ASYNC_SYSCON */
#define FSL_FEATURE_FMEAS_GET_FRG_ASYNC_SYSCON (1)
/* @brief FMEAS get clock count with scale */
#define FSL_FEATURE_FMEAS_GET_COUNT_SCALE (1)
/* @brief FMEAS start measure with scale */
#define FSL_FEATURE_FMEAS_STARTMEAS_SCALE (1)
/* @brief Func bit field width */
#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (3)
/* PINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
/* PMC module features */
/* @brief FRO1M trim address. */
#define FSL_FEATURE_PMC_FRO1M_ADDRESS (0x9FCD0U)
/* @brief FRO1M trim valid mask. */
#define FSL_FEATURE_PMC_FRO1M_VALID_MASK (0x1U)
/* RTC module features */
/* @brief Has no separate RTC OSC PD in CTRL register. */
#define FSL_FEATURE_RTC_HAS_NO_OSC_PD (1)
/* FLEXCOMM module features */
/* @brief Has no reset in FLEXCOMM register. */
#define FSL_FEATURE_FLEXCOMM_HAS_NO_RESET (1)
/* SPI module features */
#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (1)
#endif /* _JN518X_FEATURES_H_ */
/* @brief SPI SIZE bitfile in FIFOCFG register */
#define FSL_FEATURE_SPI_FIFOSIZE_CFG (1)
/* @brief SPI has only three SSEL pins */
#define FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE (1)
/* SPIFI module features */
/* @brief SPIFI start address */
#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
/* @brief SPIFI end address */
#define FSL_FEATURE_SPIFI_END_ADDR (0x103FFFFF)
/* @brief SPIFI DATALEN bitfile in CMD register */
#define FSL_FEATURE_SPIFI_DATALEN_CTRL (1)
/* SYSCON module features */
/* No feature definitions */
/* WWDT module features */
/* @brief WWDT WDTOF is not set in case of WD reset - get info from PMC instead. */
#define FSL_FEATURE_WWDT_WDTRESET_FROM_PMC (1)
/* @brief WWDT NO PDCFG. */
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
/* @brief WWDT LOCK bitfile in MOD register */
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
#endif /* _JN5189_FEATURES_H_ */
third_party/nxp/JN5189/rom_apis/flash_header.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/flash_header.h
Vendored
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third_party/nxp/JN5189/drivers/aes/fsl_aes.c → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_aes.c
Vendored
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third_party/nxp/JN5189/drivers/aes/fsl_aes.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_aes.h
Vendored
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third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.c
Vendored Executable
+1191
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File diff suppressed because it is too large Load Diff
third_party/nxp/JN5189/drivers/fsl_clock.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_clock.h
Vendored
+18 -20
View File
@@ -20,6 +20,12 @@
/*! @file */
/*! @name Driver version */
/*@{*/
/*! @brief CLOCK driver version 2.1.0. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
#ifdef FPGA_50MHZ
#define SYSCON_BASE_CLOCK_DIV (6)
#define SYSCON_BASE_CLOCK_MUL (5)
@@ -134,10 +140,8 @@ typedef enum
*/
typedef enum _clock_name
{
kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ROM_SHIFT), /*!< ROM clock */
kCLOCK_Sram0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL0_SHIFT), /*!< SRAM0 clock */
kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT), /*!< SRAM1 clock */
kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_FLASH_SHIFT), /*!< Flash clock */
kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_SPIFI_SHIFT), /*!< SPIFI clock */
kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_MUX_SHIFT), /*!< InputMux clock */
kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_IOCON_SHIFT), /*!< IOCON clock */
@@ -154,7 +158,6 @@ typedef enum _clock_name
kCLOCK_WakeTmr =
CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_WAKE_UP_TIMERS_SHIFT), /*!< Wake up Timers clock */
kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_ADC_SHIFT), /*!< ADC0 clock */
kCLOCK_Efuse = CLK_GATE_DEFINE(AHB_CLK_CTRL0, SYSCON_AHBCLKCTRL0_EFUSE_SHIFT), /*!< EFuse clock */
kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART0_SHIFT), /*!< FlexComm0 clock */
kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_USART1_SHIFT), /*!< FlexComm1 clock */
kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, SYSCON_AHBCLKCTRL1_I2C0_SHIFT), /*!< FlexComm2 clock */
@@ -246,7 +249,7 @@ typedef enum _clock_attach_id
kFRO32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Select FRO 32K for CLKOUT */
kXTAL32M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Select XTAL 32M for CLKOUT */
kDCDC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Select DCDC for CLKOUT */
kFROM48M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Select FRO 48M for CLKOUT */
kFRO48M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Select FRO 48M for CLKOUT */
kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Select FRO 1M for CLKOUT */
kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< No clock for CLKOUT */
@@ -297,10 +300,11 @@ typedef enum _clock_attach_id
kFRO12M_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 5), /*!< Select FRO 12M for DMIC */
kNONE_to_DMI_CLK = MUX_A(CM_DMICLKSEL, 6), /*!< No clock for DMIC */
kOSC32K_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 0),
kFRO1M_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 1),
kNONE_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 2),
kTESTCLK_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 3),
kOSC32K_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 0), /*!< Select OSC 32K for WKT */
kNONE_to_WKT_CLK = MUX_A(CM_WKTCLKSEL, 3), /*!< No clock for WKT */
kXTAL32M_DIV2_to_ZIGBEE_CLK = MUX_A(CM_MODEMCLKSEL, 0), /*!< Select XTAL 32M for ZIGBEE */
kNONE_to_ZIGBEE_CLK = MUX_A(CM_MODEMCLKSEL, 1), /*!< No clock for ZIGBEE */
kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), /*!< Select main clock for Asynchronous APB */
kXTAL32M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), /*!< Select XTAL 32M for Asynchronous APB */
@@ -447,9 +451,13 @@ typedef struct
uint32_t clk_XtalNPcbParCappF_x100; /*< XTAL PCB -ve parasitic capacitance */
} ClockCapacitanceCompensation_t;
#ifdef __cplusplus
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
#endif /* __cplusplus */
/**
* @brief Obtains frequency of specified clock
@@ -572,16 +580,6 @@ void CLOCK_SetXtal32M_LDO(void);
*/
void CLOCK_Xtal32M_WaitUntilStable(uint32_t u32AdditionalWait_us);
/*!
* @brief Use DWT to delay at least for some time.
* Please note that, this API will calculate the microsecond period with the maximum devices
* supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
* delay count was needed, please implement a new timer count to achieve this function.
*
* @param delay_us Delay time in unit of microsecond.
*/
void SDK_DelayAtLeastUs(uint32_t delay_us);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
third_party/nxp/JN5189/drivers/fsl_common.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_common.h
Vendored
+12 -2
View File
@@ -38,8 +38,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief common driver version 2.1.3. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
/*! @brief common driver version 2.2.0. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
/* Debug console type definition. */
@@ -611,6 +611,16 @@ _Pragma("diag_suppress=Pm120")
*/
void SDK_Free(void *ptr);
/*!
* @brief Delay at least for some time.
* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
* if precise delay count was needed, please implement a new delay function with hardware timer.
*
* @param delay_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
#if defined(__cplusplus)
}
#endif
third_party/nxp/JN5189/drivers/fsl_ctimer.c → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_ctimer.c
Vendored
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third_party/nxp/JN5189/drivers/fsl_ctimer.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_ctimer.h
Vendored
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third_party/nxp/JN5189/drivers/fsl_flash.c → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flash.c
Vendored
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third_party/nxp/JN5189/drivers/fsl_flash.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flash.h
Vendored
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third_party/nxp/JN5189/drivers/fsl_flexcomm.c → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flexcomm.c
Vendored
View File
third_party/nxp/JN5189/drivers/fsl_flexcomm.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_flexcomm.h
Vendored
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third_party/nxp/JN5189/drivers/fsl_gpio.c → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_gpio.c
Vendored
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third_party/nxp/JN5189/drivers/fsl_gpio.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_gpio.h
Vendored
View File
third_party/nxp/JN5189/drivers/fsl_iocon.h → third_party/nxp/JN5189DK6/devices/JN5189/drivers/fsl_iocon.h
Vendored
+9 -1
View File
@@ -60,7 +60,7 @@ typedef struct _iocon_group
#define IOCON_MODE_PULLDOWN IOCON_PIO_MODE(3) /*!< Selects pull-down function */
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis ??*/
#define IOCON_GPIO_MODE IOCON_PIO_SLEW0(1) /*!< GPIO Mode */
#define IOCON_GPIO_MODE IOCON_PIO_EGP(1) /*!< GPIO Mode */
#define IOCON_I2C_SLEW IOCON_PIO_SLEW0(1) /*!< I2C Slew Rate Control */
#define IOCON_INV_EN IOCON_PIO_INVERT(1) /*!< Enables invert function on input */
@@ -90,6 +90,14 @@ typedef struct _iocon_group
#define IOCON_IO_CLAMPING_NORMAL_MFIO (1 << 11)
#define IOCON_IO_CLAMPING_COMBO_MFIO_I2C (1 << 12) /* Use this flag for PIO11 and PIO12 only */
#define IOCON_PIO_DBG_FUNC_MASK (0xF000U)
#define IOCON_PIO_DBG_FUNC_SHIFT (12U)
#define IOCON_PIO_DBG_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DBG_FUNC_SHIFT)) & IOCON_PIO_DBG_FUNC_MASK)
#define IOCON_PIO_DBG_MODE_MASK (0x10000U)
#define IOCON_PIO_DBG_MODE_SHIFT (16U)
#define IOCON_PIO_DBG_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DBG_MODE_SHIFT)) & IOCON_PIO_DBG_MODE_MASK)
#define IOCON_CFG(dbg_func) (IOCON_PIO_FUNC(0) | IOCON_MODE_PULLDOWN |\
IOCON_DIGITAL_EN | IOCON_INPFILT_OFF | \
IOCON_PIO_DBG_FUNC(dbg_func) | IOCON_PIO_DBG_MODE(1))

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