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[da15000] misc improvements for Dialog platform (#2216)

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* New Platform Startup
        * Flash memory handling improved
        * Ramdom generator improved
        * Faster platform reboot
        * UART based on interrupts intruduced
        * ARM core and linker related files moved to "third_party" folder
        * Radio Sleep Fixed
        * TLS config fixed
        * Software FIFO for UART added
This commit is contained in:
JakubBrachTieto
2017-09-25 23:10:05 -07:00
committed by Jonathan Hui
parent 3db75ab31f
commit 831fd9b173
28 changed files with 3119 additions and 1015 deletions
Download Patch File Download Diff File Expand all files Collapse all files
examples/apps/cli/Makefile.am
+1 -1
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@@ -118,7 +118,7 @@ LDADD_COMMON += \
$(NULL)
LDFLAGS_COMMON += \
-T $(top_srcdir)/examples/platforms/da15000/da15000.ld \
-T $(top_srcdir)/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld \
$(NULL)
endif # OPENTHREAD_EXAMPLES_DA15000
examples/apps/ncp/Makefile.am
+1 -1
View File
@@ -118,7 +118,7 @@ LDADD_COMMON += \
$(NULL)
LDFLAGS_COMMON += \
-T $(top_srcdir)/examples/platforms/da15000/da15000.ld \
-T $(top_srcdir)/third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld \
$(NULL)
endif # OPENTHREAD_EXAMPLES_DA15000
examples/platforms/da15000/Makefile.am
+5 -5
View File
@@ -65,12 +65,7 @@ PLATFORM_SOURCES
platform.c \
radio.c \
random.c \
vector.c \
cstartup.c \
uart.c \
cortex-m_cstartup.c \
startup-gcc.c \
clock.c \
misc.c \
crypto/aes_alt.c \
$(NULL)
@@ -79,6 +74,7 @@ DIALOG_SOURCES
@top_builddir@/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c \
@@ -92,6 +88,10 @@ DIALOG_SOURCES
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/startup/config.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/startup/startup_ARMCM0.S \
@top_builddir@/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/startup/vector_table.S \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c \
examples/platforms/da15000/clock.c
-62
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@@ -1,62 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file clock.c
* Clock init for Dialog da15000.
*
*/
#include "sdk_defs.h"
#include "hw_cpm.h"
#include "hw_watchdog.h"
volatile uint8_t xtal16_settled = 0;
extern void XTAL16RDY_Handler(void);
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions.
DO NOT CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT
THAT HAS A HIGHER PRIORITY THAN THIS! (higher priorities are lower
numeric values on an ARM Cortex-M). */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1
void switch_to_rc16(void)
{
if (!hw_cpm_check_rc16_status()) // RC16 is disabled
{
hw_cpm_enable_rc16(); // Enable RC16
hw_cpm_short_delay(); // Wait until it is stable
}
// fast --> slow clock switch
hw_cpm_set_sysclk(SYS_CLK_IS_RC16); // Set RC16 as sys_clk
//cm_adjust_otp_access_timings(); // Adjust OTP timings
}
examples/platforms/da15000/cortex-m_cstartup.c
-136
View File
@@ -1,136 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file cortex-m_cstartup.c
* ARM Cortex-M generic cstartup.
*
* Setup RAM as needed based on GCC linker script sections.
*/
#include <stdint.h>
#include "sdk_defs.h"
//#include <tool.h>
#define __NAKED __attribute__((naked))
#define __USED __attribute__((used))
#define __NO_RETURN __attribute__((noreturn))
// forward declaration
extern void main(void);
extern void __cpu_startup(void);
extern void __gcc_program_start(void);
extern uint32_t _sdata; // Start of .data region in RAM
extern uint32_t _edata; // End of .data region in RAM
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __init_array_start;
extern uint32_t __init_array_end;
extern uint32_t __rwdata_start__; // End of .text region in FLASH
/********************************************************************/
void cstartup_rwdata()
{
// Get the addresses for the .data section (initialized data section)
uint32_t *data_rom = (uint32_t *) &__rwdata_start__;
uint32_t *data_ram = (uint32_t *) &_sdata;
uint32_t *data_ram_end = (uint32_t *) &_edata;
// Copy initialized data from ROM to RAM
while (data_ram < data_ram_end)
{
*data_ram++ = *data_rom++;
}
}
void cstartup_bss()
{
/* Clear the zero-initialized data section */
uint32_t *bss_start = (uint32_t *) &__bss_start__;
uint32_t *bss_end = (uint32_t *) &__bss_end__;
while (bss_start < bss_end)
{
*bss_start++ = 0;
}
}
void cstartup(void)
{
cstartup_rwdata();
cstartup_bss();
}
/********************************************************************/
/**
* ARM Cortex-M Start
*
* This function calls all of the needed startup routines and then
* branches to the main process.
*
* This contains the very first instructions that are run on boot.
*/
void __USED __NAKED __NO_RETURN __gcc_program_start(void)
{
// early platform initialization - configure clocks, etc.
__cpu_startup();
// C/C++ runtime initialization (BSS, Data, relocation, etc.)
cstartup();
// TBD we should pass parameters here.
main();
// No actions to perform after this so wait forever
while (1);
}
uint32_t DA15000_phy_addr(uint32_t addr)
{
static const uint32_t remap[] =
{
MEMORY_ROM_BASE,
MEMORY_OTP_BASE,
MEMORY_QSPIF_BASE,
MEMORY_SYSRAM_BASE,
MEMORY_QSPIF_BASE,
MEMORY_OTP_BASE,
MEMORY_CACHERAM_BASE,
0
};
if (addr >= MEMORY_REMAPPED_END)
{
return addr;
}
return addr + remap[REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0)];
}
examples/platforms/da15000/crypto/da15000-mbedtls-config.h
+5 -4
View File
@@ -31,8 +31,9 @@
#include <stdlib.h>
#include "openthread/platform/logging.h"
#include "openthread/platform/memory.h"
#include <openthread/config.h>
#include <openthread/platform/logging.h>
#include <openthread/platform/memory.h>
#if defined(_WIN32)
#include <stdarg.h>
@@ -1974,7 +1975,7 @@ __inline int windows_kernel_snprintf(char * s, size_t n, const char * format, ..
*
* Enable this module to enable the buffer memory allocator.
*/
#ifndef OPENTHREAD_MULTIPLE_INSTANCE
#if !OPENTHREAD_ENABLE_MULTIPLE_INSTANCES
#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
#endif
@@ -2548,7 +2549,7 @@ __inline int windows_kernel_snprintf(char * s, size_t n, const char * format, ..
/* Platform options */
//#define MBEDTLS_PLATFORM_STD_MEM_HDR <stdlib.h> /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */
#ifdef OPENTHREAD_MULTIPLE_INSTANCE
#if OPENTHREAD_ENABLE_MULTIPLE_INSTANCES
#define MBEDTLS_PLATFORM_STD_CALLOC otPlatCAlloc /**< Default allocator to use, can be undefined */
#define MBEDTLS_PLATFORM_STD_FREE otPlatFree /**< Default free to use, can be undefined */
#endif
examples/platforms/da15000/cstartup.c
-53
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@@ -1,53 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file cstartup.c
* cstartup for Dialog da15000.
* Called by __BOOT_STARTUP to initialize the processor on boot.
* The caller is aliased in tool.h to a compiler dependant value:
* IAR: __low_level_init
* GCC: __gcc_program_start
*
* For Cortex-M cores, called from cpu/arm/cortex-m/boot/cstartup.c.
*/
#include "sdk_defs.h"
#include "bsp/include/core_cm0.h"
void __cpu_startup(void)
{
// SetWord16(CLK_AMBA_REG, 0x00); // set clocks (hclk and pclk ) 16MHz
// SetWord16(SET_FREEZE_REG,FRZ_WDOG); // stop watchdog
// SetBits16(SYS_CTRL_REG,PAD_LATCH_EN,1); // enable pads
ENABLE_DEBUGGER; // enable debugger
// SetBits16(PMU_CTRL_REG, PERIPH_SLEEP,0); // exit peripheral power down
// SetBits16(PMU_CTRL_REG, RETAIN_RAM, dg_configMEM_RETENTION_MODE);
// SetBits16(AON_SPARE_REG, EN_BATSYS_RET, 1); // Power GPIOs during sleep
}
examples/platforms/da15000/custom_config_qspi.h
+2 -9
View File
@@ -82,8 +82,6 @@
#define dg_configUSE_SW_CURSOR (1)
#define dg_configCACHEABLE_QSPI_AREA_LEN NVMS_PARAM_PART_start
#define dg_configFEM_DLG_REF_BOARD (1)
#define dg_configPOWER_1V8P (1)
@@ -109,17 +107,12 @@
#define FTDF_LITE
#define dg_configFLASH_ADAPTER (0)
#define dg_configUART_SOFTWARE_FIFO (1)
#define dg_configUART2_SOFTWARE_FIFO_SIZE (256)
#define dg_configNVMS_ADAPTER (0)
#define dg_configNVMS_VES (0)
#define dg_configUSE_WDOG (0)
/* Include bsp default values */
#include "bsp_defaults.h"
/*************************************************************************************************\
* Open Thread specific config
*/
#define SETTINGS_CONFIG_BASE_ADDRESS (0x7B000)
#endif /* CUSTOM_CONFIG_QSPI_H_ */
examples/platforms/da15000/da15000.ld
-205
View File
@@ -1,205 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
_BOOTLOADER_SIZE = 0 ;
_QSPI_SIZE = 2048K ; /* ld doesn't allow defines to be used for MEMORY */
_EXE_SIZE = 108K ; /* In RAM config, reserve space for the executable... */
_TEXT_START = 0x140 ;
MEMORY
{
vector (rx) : ORIGIN = 0x00000000, LENGTH = 0x0C0
magic (r) : ORIGIN = 0x000000C0, LENGTH = 0x080 /* patch table */
flash (rx) : ORIGIN = 0x00000140, LENGTH = 2048K
rom (rx) : ORIGIN = 0x07F00000, LENGTH = 256K
otp (rx) : ORIGIN = 0x07F80000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x07FC0000+0x140, LENGTH = 128K-0x140
cacheram (rwx) : ORIGIN = 0x07FE0000, LENGTH = 16K
qspi (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
}
/**
* GCC linker script for ARM Cortex-M microcontrollers.
*/
/*
ENTRY(_start)
*/
ENTRY(__gcc_program_start)
/*
* Reserve memory for heap and stack. The linker will issue an error if there
* is not enough memory.
*
* NOTE: The reserved heap and stack will be added to the bss column of the
* binutils size command.
*/
_heap_size = 0x0; /* required amount of heap */
_stack_size = 0x0; /* required amount of stack */
/*
* The stack starts at the end of RAM and grows downwards. Full-descending
* stack; decrement first, then store.
*/
__stack_start__ = ORIGIN(ram) + LENGTH(ram);
__stack_end__ = __stack_start__ - _stack_size;
EXTERN(__vector_table)
SECTIONS
{
/* Reset and ISR vectors */
.isr_vector :
{
__isr_vector_start__ = .;
__cs3_interrupt_vector = __vector_table;
KEEP(*(.isr_vector))
ASSERT(. != __isr_vector_start__, "The .isr_vector section is empty");
} >vector
/* Special configuration section for some processors */
.magic :
{
KEEP(*(.magic))
} >magic
/* Text section (code and read-only data) */
.text :
{
. = _TEXT_START;
. = ALIGN(4);
_stext = .;
*(.text*) /* code */
_etext = .;
__rodata_start__ = .;
*(.rodata*) /* read only data */
/*
* Note: No ARM/Thumb interworking, so no .glue_7 or .glue_7t sections
*/
*(.ctors)
*(.dtors)
/* Static constructors and destructors */
KEEP(*(.init))
KEEP(*(.fini))
. = ALIGN(4);
} >flash
/*
* Stack unwinding and exception handling sections.
*
* ARM compilers emit object files with .ARM.extab and .ARM.exidx sections
* when using C++ exceptions. Also, at least GCC emits those sections when
* dividing large numbers (64-bit) in C. So we have to handle them.
*
* (ARM uses .ARM.extab and .ARM.exidx instead of the .eh_frame section
* used on x86.)
*/
.ARM.extab : /* exception unwinding information */
{
*(.ARM.extab*)
} >flash
.ARM.exidx : /* index entries for section unwinding */
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >flash
/*
* Initialized data section. This section is programmed into FLASH (LMA
* address) and copied to RAM (VMA address) in startup code.
*/
. = ALIGN(4);
__rwdata_start__ = .; /* LMA address is _sidata (in FLASH) */
.data : AT(__rwdata_start__)
{
. = ALIGN(4);
_sdata = .; /* data section VMA address */
*(text_retained)
. = ALIGN(4);
*(.data*)
. = ALIGN(4);
_edata = .;
} >ram
/* Uninitialized data section (zeroed out by startup code) */
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__end__ = .;
} >ram
/*
* Reserve memory for heap and stack. The linker will issue an error if
* there is not enough memory.
*/
._heap :
{
. = ALIGN(4);
_sheap = .;
. = . + _heap_size;
. = ALIGN(4);
_eheap = .;
} >ram
._stack :
{
. = ALIGN(4);
. = . + _stack_size;
. = ALIGN(4);
} >ram
}
/* Nice to have */
__isr_vector_size__ = SIZEOF(.isr_vector);
__text_size__ = SIZEOF(.text);
__data_size__ = SIZEOF(.data);
__bss_size__ = SIZEOF(.bss);
PROVIDE (end = .);
examples/platforms/da15000/flash.c
+75 -60
View File
@@ -27,43 +27,36 @@
*/
#include <openthread/config.h>
#include <openthread/types.h>
#include <openthread/platform/alarm-milli.h>
#include "hw_qspi.h"
#include "qspi_automode.h"
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_BUFFER_SIZE 0x2000
#define FLASH_BUFFER_SIZE 0x2000
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_PAGE_SIZE 0x0100
#define W25Q_READ_STATUS_REGISTER1 0x05
/*
* In case that user tries to write data to flash passing as source QSPI mapped flash address
* data must be first copied to RAM as during write QSPI controller can't read flash.
* To achieve this, small on stack buffer will be used to copy data to RAM first.
* This define specifies how much stack can be used for this purpose.
*/
#define ON_STACK_BUFFER_SIZE 16
/* Erase/Write in progress */
#define W25Q_STATUS1_BUSY_BIT 0
#define W25Q_STATUS1_BUSY_MASK (1 << W25Q_STATUS1_BUSY_BIT)
static uint32_t sWaitStatusTimeout;
QSPI_SECTION static uint8_t qspi_get_erase_status(void)
otError utilsFlashInit(void)
{
QSPIC->QSPIC_CHCKERASE_REG = 0;
return HW_QSPIC_REG_GETF(ERASECTRL, ERS_STATE);
return OT_ERROR_NONE;
}
volatile bool DisableErase = false;
uint32_t utilsFlashGetSize(void)
{
return (uint32_t)FLASH_BUFFER_SIZE;
}
// Erase QSPI memory section as non-blocking function. Remember to check utilsFlashStatusWait before write or read!!
otError utilsFlashErasePage(uint32_t aAddress)
{
uint32_t flash_offset = aAddress & ~(FLASH_SECTOR_SIZE - 1);
uint32_t flash_offset = (aAddress) & ~(FLASH_SECTOR_SIZE - 1);
if (DisableErase)
{
return OT_ERROR_NONE;
}
qspi_automode_init();
qspi_automode_erase_flash_sector(flash_offset);
CACHE->CACHE_CTRL1_REG = CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk;
@@ -71,62 +64,84 @@ otError utilsFlashErasePage(uint32_t aAddress)
return OT_ERROR_NONE;
}
uint32_t utilsFlashGetSize(void)
{
return (uint32_t)FLASH_BUFFER_SIZE;
}
otError utilsFlashStatusWait(uint32_t aTimeout)
{
(void)aTimeout;
sWaitStatusTimeout = otPlatAlarmMilliGetNow();
while (qspi_get_erase_status() && ((otPlatAlarmMilliGetNow() - sWaitStatusTimeout) < aTimeout));
if (qspi_get_erase_status())
{
return OT_ERROR_BUSY;
}
else
{
return OT_ERROR_NONE;
}
return OT_ERROR_NONE;
}
otError utilsFlashInit(void)
static inline bool FlashQspiAddress(const void *aBuf)
{
qspi_automode_flash_power_up();
if (((uint32_t) aBuf >= MEMORY_QSPIF_BASE) && ((uint32_t) aBuf < MEMORY_QSPIF_END))
{
return true;
}
if (utilsFlashStatusWait(1000) == OT_ERROR_BUSY)
{
return OT_ERROR_FAILED;
}
else
{
return OT_ERROR_NONE;
}
return ((uint32_t) aBuf >= MEMORY_REMAPPED_BASE) && ((uint32_t) aBuf < MEMORY_REMAPPED_END)
&& (REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0) == 2);
}
uint32_t utilsFlashWrite(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
static size_t FlashWriteFromQspi(uint32_t aAddress, const uint8_t *aQspiBuf, size_t aSize)
{
size_t offset = 0;
size_t written;
size_t offset = 0;
uint8_t buf[ON_STACK_BUFFER_SIZE];
/*
* qspi_automode_write_flash_page can't write data if source address points to QSPI mapped
* memory. To write data from QSPI flash, it will be first copied to small on stack
* buffer. This buffer can be accessed when QSPI controller is working in manual mode.
*/
while (offset < aSize)
{
written = qspi_automode_write_flash_page(aAddress + offset, aData + offset,
aSize - offset);
size_t chunk = sizeof(buf) > aSize - offset ? aSize - offset : sizeof(buf);
memcpy(buf, aQspiBuf + offset, chunk);
written = qspi_automode_write_flash_page(aAddress + offset, buf, chunk);
offset += written;
}
return offset;
}
uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
uint32_t utilsFlashWrite(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
{
memcpy(aData, (void *)(MEMORY_QSPIF_BASE + aAddress), aSize);
size_t written;
size_t offset = 0;
bool buf_from_flash = FlashQspiAddress(aData);
while (offset < aSize)
{
/*
* If buf is QSPI Flash memory, use function that will copy source data to RAM
* first.
*/
if (buf_from_flash)
{
written = FlashWriteFromQspi(aAddress + offset, aData + offset,
aSize - offset);
}
else
{
/*
* Try write everything, lower driver will reduce this value to accommodate
* page boundary and and maximum write size limitation
*/
written = qspi_automode_write_flash_page(aAddress + offset, aData + offset,
aSize - offset);
}
offset += written;
}
CACHE->CACHE_CTRL1_REG = CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk;
return aSize;
}
uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
{
return qspi_automode_read(aAddress, aData, aSize);;
}
examples/platforms/da15000/misc.c
+1 -1
View File
@@ -37,7 +37,7 @@
void otPlatReset(otInstance *aInstance)
{
(void)aInstance;
WDOG->WATCHDOG_CTRL_REG |= (1 << (WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos));
hw_cpm_reboot_system();
}
otPlatResetReason otPlatGetResetReason(otInstance *aInstance)
examples/platforms/da15000/openthread-core-da15000-config.h
+9 -1
View File
@@ -47,7 +47,15 @@
*
* The base address of the pages to be used for non-volatile-settings storage.
*/
#define SETTINGS_CONFIG_BASE_ADDRESS (0x7B000)
#define SETTINGS_CONFIG_BASE_ADDRESS 0x7B000
/**
* @def SETTINGS_CONFIG_PAGE_SIZE
*
* The page size of settings.
*
*/
#define SETTINGS_CONFIG_PAGE_SIZE 0x1000
/**
* @def OPENTHREAD_CONFIG_ENABLE_SOFTWARE_ACK_TIMEOUT
examples/platforms/da15000/platform.c
-28
View File
@@ -61,38 +61,12 @@ static int sMsCounter;
static otInstance *sInstance = NULL;
void ClkInit(void)
{
NVIC_ClearPendingIRQ(XTAL16RDY_IRQn);
NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ
hw_cpm_set_divn(false); // External crystal is 16MHz
hw_cpm_enable_rc32k();
hw_cpm_lp_set_rc32k();
hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K);
hw_cpm_enable_xtal16m(); // Enable XTAL16M
hw_cpm_configure_xtal32k_pins(); // Configure XTAL32K pins
hw_cpm_configure_xtal32k(); // Configure XTAL32K
hw_cpm_enable_xtal32k(); // Enable XTAL32K
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_recharge_period((uint16_t)dg_configSET_RECHARGE_PERIOD);
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M);
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
hw_otpc_init();
hw_otpc_set_speed(HW_OTPC_SYS_CLK_FREQ_16);
}
/*
* Example function. Blink LED according to node state
* Leader - 5Hz
* Router - 2Hz
* Child - 0.5Hz
*/
void ExampleProcess(otInstance *aInstance)
{
static int aliveLEDcounter = 0;
@@ -156,8 +130,6 @@ void ExampleProcess(otInstance *aInstance)
void PlatformInit(int argc, char *argv[])
{
// Initialize System Clock
ClkInit();
// Initialize Random number generator
da15000RandomInit();
// Initialize Alarm
examples/platforms/da15000/radio.c
+7 -1
View File
@@ -589,11 +589,13 @@ void da15000RadioProcess(otInstance *aInstance)
if ((frameHeader.options & FTDF_OPT_ACK_REQUESTED) == 0 || sTransmitStatus != OT_ERROR_NONE)
{
sRadioState = OT_RADIO_STATE_RECEIVE;
otPlatRadioTxDone(sThreadInstance, &sTransmitFrame, NULL, sTransmitStatus);
}
else
{
otEXPECT(sAckFrame);
sRadioState = OT_RADIO_STATE_RECEIVE;
otPlatRadioTxDone(sThreadInstance, &sTransmitFrame, sReceiveFrameAck, sTransmitStatus);
sAckFrame = false;
}
@@ -601,7 +603,6 @@ void da15000RadioProcess(otInstance *aInstance)
sTransmitDoneFrame = false;
otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL);
sRadioState = OT_RADIO_STATE_RECEIVE;
}
exit:
@@ -647,6 +648,11 @@ void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength,
if (status == FTDF_TRANSPARENT_RCV_SUCCESSFUL)
{
#if OPENTHREAD_ENABLE_RAW_LINK_API
// Timestamp
sReceiveFrameAck.mMsec = otPlatAlarmMilliGetNow();
sReceiveFrameAck.mUsec = 0; // Don't support microsecond timer for now.
#endif
sReceiveFrame[sWriteFrame].mChannel = sChannel;
sReceiveFrame[sWriteFrame].mLength = frameLength;
sReceiveFrame[sWriteFrame].mLqi = lqi;
examples/platforms/da15000/random.c
+66 -43
View File
@@ -28,10 +28,7 @@
/**
* @file
* This file implements a pseudo-random number generator.
*
* @warning
* This implementation is not a true random number generator and does @em satisfy the Thread requirements.
* This file implements true random number generator.
*/
#include <string.h>
@@ -42,64 +39,90 @@
#include "hw_trng.h"
#include "sdk_defs.h"
#define HW_TRNG_RAM (0x40040000)
#define RANDOM_SIZE_OF_BUFFER 32
static uint32_t sState = 1;
static uint32_t sSeed;
static uint32_t sRandomNumbers[RANDOM_SIZE_OF_BUFFER];
static uint8_t sRandomNextNumberIndex = 0;
static bool sRandomGeneratorStarted = false;
int zhal_get_entropy(uint8_t *outEntropy, size_t inSize)
static void RandomCallback(void)
{
uint32_t randword;
unsigned char *pbuf = outEntropy;
const size_t req_words = inSize >> 2;
const unsigned char *pbuf_end = outEntropy + inSize;
const unsigned char *preq_words_end = (unsigned char *)(((uint32_t *)outEntropy) + req_words);
ptrdiff_t remainder_bytes = pbuf_end - preq_words_end;
hw_trng_get_numbers(sRandomNumbers, RANDOM_SIZE_OF_BUFFER);
sRandomNextNumberIndex = 0;
hw_trng_stop();
hw_trng_disable_clk();
hw_trng_disable_interrupt();
sRandomGeneratorStarted = false;
}
hw_trng_enable(NULL);
for (pbuf = outEntropy; pbuf < preq_words_end; pbuf += 4)
{
/* Wait for a random word to become available in the TRNG FIFO. */
while ((TRNG->TRNG_FIFOLVL_REG & TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk) == 0);
randword = *((volatile uint32_t *)HW_TRNG_RAM);
memcpy(pbuf, &randword, 4);
}
if (remainder_bytes)
{
while ((TRNG->TRNG_FIFOLVL_REG & TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk) == 0);
randword = *((volatile uint32_t *)HW_TRNG_RAM);
memcpy(pbuf, &randword, remainder_bytes);
}
hw_trng_disable();
return 0;
static void StartGenerator(void)
{
hw_trng_enable(RandomCallback);
sRandomGeneratorStarted = true;
}
void da15000RandomInit(void)
{
zhal_get_entropy((uint8_t *)&sSeed, sizeof(sSeed));
sState = sSeed;
StartGenerator();
}
uint32_t otPlatRandomGet(void)
{
uint32_t mlcg;
zhal_get_entropy((uint8_t *)&mlcg, sizeof(mlcg));
return mlcg;
uint32_t randomNumber;
bool randomGet = false;
do
{
GLOBAL_INT_DISABLE();
if (sRandomNextNumberIndex < RANDOM_SIZE_OF_BUFFER)
{
randomNumber = sRandomNumbers[sRandomNextNumberIndex++];
randomGet = true;
if (sRandomNextNumberIndex == RANDOM_SIZE_OF_BUFFER)
{
StartGenerator();
}
}
else if (hw_trng_get_fifo_level() > 0)
{
randomNumber = hw_trng_get_number();
randomGet = true;
}
else if (!sRandomGeneratorStarted)
{
StartGenerator();
}
GLOBAL_INT_RESTORE();
}
while (!randomGet);
return randomNumber;
}
otError otPlatRandomGetTrue(uint8_t *aOutput, uint16_t aOutputLength)
{
uint32_t randomNumber;
for (uint16_t length = 0; length < aOutputLength; length++)
while (aOutputLength)
{
aOutput[length] = (uint8_t)otPlatRandomGet();
randomNumber = otPlatRandomGet();
if (aOutputLength < 4)
{
memcpy(aOutput, &randomNumber, aOutputLength);
aOutputLength = 0;
}
else
{
memcpy(aOutput, &randomNumber, 4);
aOutputLength -= 4;
aOutput += 4;
}
}
return OT_ERROR_NONE;
}
examples/platforms/da15000/startup-gcc.c
-59
View File
@@ -1,59 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* Stubs out exception handling and general C++ bloat
* for suitability for embedded environments.
*/
#include <stdint.h>
__extension__ typedef int __guard __attribute__((mode(__DI__)));
extern int __cxa_guard_acquire(__guard *g);
extern void __cxa_guard_release(__guard *g);
extern void __cxa_guard_abort(__guard *g);
extern void __cxa_pure_virtual(void);
int __cxa_guard_acquire(__guard *g)
{
return !*(char *)(g);
}
void __cxa_guard_release(__guard *g)
{
*(char *)g = 1;
}
void __cxa_guard_abort(__guard *g)
{
(void) g;
}
void __cxa_pure_virtual(void)
{
while (1);
}
void *__dso_handle;
examples/platforms/da15000/startup_ARMCM0.S
+370
View File
@@ -0,0 +1,370 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file startup_ARMCM0.S
* Startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V2.0
* Date: 16 August 2013
*/
.syntax unified
.arch armv6-m
.section text_reset
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
#if (dg_configSKIP_MAGIC_CHECK_AT_START == 0)
/* If the Magic Word {0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEAD10CC} is found at 0x7fd0000 then the
* execution will block for a while in order to give time to a debugger to attach. */
ldr r4, =0x7fd0000
ldmia r4!, {r0-r3}
ldr r4, =0xDEADBEEF
cmp r0, r4
bne .code_starts
cmp r1, r4
bne .code_starts
cmp r2, r4
bne .code_starts
ldr r4, =0xDEAD10CC
cmp r3, r4
bne .code_starts
/* Enable debugger */
ldr r4, =0x50000012
ldrh r5, [r4]
mov r6, r5
movs r1, #128
orrs r5, r5, r1
strh r5, [r4]
/* Block for 2'' */
ldr r0, =0x150000
.delay_loop:
subs r0, #1
bgt .delay_loop
/* Make sure that this will happen only once! */
ldr r4, =0x7fd0000
movs r0, #0
str r0, [r4]
/* Restore debugger setting */
ldr r4, =0x50000012
strh r6, [r4]
.code_starts:
#endif
/* RAM shuffling configuration should be determined from the image in the QSPI Flash or OTP
* and must be applied at the beginning of the Reset Vector. The interrupt vector table must
* be copied to the RAM base after the shuffling is done.
* NOTE: Even though there is an OTP field specifically for the shuffling configuration
* we must bypass it here since the shuffling might change between different
* QSPI FLASH image versions. For OTP images RAM shuffling configuration will never change,
* but we also apply it to ignore the OTP field in any case. */
ldr r4, =0x50000012
movs r0, #0
ldrh r0, [r4]
movs r1, #0x18
bics r0, r0, r1
movs r1, #dg_configSHUFFLING_MODE<<3
orrs r0, r0, r1
/* Update SYS_CTRL_REG. */
strh r0, [r4]
/* Copy ISR VT from from QSPI Flash/OTP to RAM. This must be done
* after applying shuffling mode. */
# if (dg_configIMAGE_FLASH_OFFSET == 0)
ldr r1, =0x8000008
# else
ldr r1, =(0x8000000 + dg_configIMAGE_FLASH_OFFSET)
# endif
ldr r2, =0x7FC0000
ldr r3, =0x7FC00C0
/* Block should be a multiple of 16 to traverse correctly L_loopIV */
subs r3, r2
ble .L_loopIV_done
.L_loopIV:
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
subs r3, #16
bgt .L_loopIV
.L_loopIV_done:
bl SystemInitPre
bl SystemInit
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#define __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r0, =__copy_table_end__
.L_loop0:
cmp r4, r0
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
push {r4}
.L_loop0_0:
subs r3, #16
blt .L_loop0_0_done
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
b .L_loop0_0
.L_loop0_0_done:
pop {r4}
adds r4, #12
b .L_loop0
.L_loop0_done:
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#define __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r0, =__zero_table_end__
movs r4, 0
movs r5, r4
mov r6, r4
mov r7, r4
.L_loop2:
cmp r3, r0
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
.L_loop2_0:
subs r2, #32 // Requires 32-byte alignment!
blt .L_loop2_0_done
stmia r1!, {r4-r7}
stmia r1!, {r4-r7}
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
/* Copy the address of the retained NMI and HardFault handlers to the vector table. */
ldr r0, =0x7FC0008
ldr r1, =NMI_Handler
str r1, [r0, #0]
ldr r1, =HardFault_Handler
str r1, [r0, #4]
bl SystemInitPost
bl main
.pool
.size Reset_Handler, . - Reset_Handler
.text
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
/*
* enable debugger:
* CRG_TOP->SYS_CTRL_REG_b.DEBUGGER_ENABLE = 1;
*/
movs r1, #0x50
lsls r1, #24
ldrh r2, [r1, #0x12]
movs r3, #0x80
orrs r2, r2, r3
strh r2, [r1, #0x12]
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.thumb
.thumb_func
.align 1
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler BLE_WAKEUP_LP_Handler
def_irq_handler BLE_GEN_Handler
def_irq_handler FTDF_WAKEUP_Handler
def_irq_handler FTDF_GEN_Handler
def_irq_handler RFCAL_Handler
def_irq_handler COEX_Handler
def_irq_handler CRYPTO_Handler
def_irq_handler MRM_Handler
def_irq_handler UART_Handler
def_irq_handler UART2_Handler
def_irq_handler I2C_Handler
def_irq_handler I2C2_Handler
def_irq_handler SPI_Handler
def_irq_handler SPI2_Handler
def_irq_handler ADC_Handler
def_irq_handler KEYBRD_Handler
def_irq_handler IRGEN_Handler
def_irq_handler WKUP_GPIO_Handler
def_irq_handler SWTIM0_Handler
def_irq_handler SWTIM1_Handler
def_irq_handler QUADEC_Handler
def_irq_handler USB_Handler
def_irq_handler PCM_Handler
def_irq_handler SRC_IN_Handler
def_irq_handler SRC_OUT_Handler
def_irq_handler VBUS_Handler
def_irq_handler DMA_Handler
def_irq_handler RF_DIAG_Handler
def_irq_handler TRNG_Handler
def_irq_handler DCDC_Handler
def_irq_handler XTAL16RDY_Handler
def_irq_handler RESERVED31_Handler
.section text_retained
.align 1
.thumb
.thumb_func
.globl NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r1, =NMI_HandlerC
movs r0, #4
mov r2, lr
tst r0, r2
beq NMI_stacking_using_MSP
mrs r0, psp
b stack_check
NMI_stacking_using_MSP:
mrs r0, msp
b stack_check
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb
.thumb_func
.globl HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r1, =HardFault_HandlerC
movs r0, #4
mov r2, lr
tst r0, r2
beq HF_stacking_using_MSP
mrs r0, psp
b stack_check
HF_stacking_using_MSP:
mrs r0, msp
stack_check:
/* 0x7FC0000 is start of RAM */
ldr r2, =0x7FC0000
cmp r0, r2
blt Wrong_SP
/* Check SYS_CTRL_REG:CACHERAM_MUX */
ldr r2, =0x50000012
ldrh r2, [r2]
movs r3, #1
lsls r3, r3, #10
ands r2, r2, r3
bne cache_is_on
/* 0x7FE4000 marks end of RAM (assuming that the CACHE is used as RAM) */
ldr r2, =0x7FE4000-32
b check_end_of_ram
cache_is_on:
/* 0x7FE0000 marks end of RAM */
ldr r2, =0x7FE0000-32
check_end_of_ram:
cmp r0, r2
bgt Wrong_SP
bx r1
Wrong_SP:
/* Freeze WDog at all times */
ldr r0, =0x50003300
ldr r1, =8
strh r1, [r0, #0]
/* Enable debugger at all times */
ldr r4, =0x50000012
ldrh r0, [r4, #0]
movs r1, #0x80
orrs r0, r0, r1
/* Update SYS_CTRL_REG */
strh r0, [r4, #0]
/* Wait for the WDog to hit or a debug session to start */
b .
.size HardFault_Handler, . - HardFault_Handler
.end
examples/platforms/da15000/system_ARMCM0.c
+609
View File
@@ -0,0 +1,609 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file system_ARMCM0.c
* CMSIS Device System Source File for ARMCM0 Device Series.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <sys/errno.h>
#include "sdk_defs.h"
#include "interrupts.h"
#include "hw_cpm.h"
#include "hw_otpc.h"
#include "hw_qspi.h"
#include "hw_watchdog.h"
#include "sys_tcs.h"
#include "qspi_automode.h"
/*
* This is just so that compilation doesn't break for RAM builds.
* The code that uses it is optimized out in RAM builds.
*/
extern uint32_t NVMS_PARAM_PART_end;
/*
* TCS Offsets
*/
#define OTP_HEADER_BASE_ADDR_IN_OTP (0x7F8E9C0)
#define TCS_SECTION_OFFSET (184) /* 0x7F8EA78 - 0x7F8E9C0 */
#define TCS_SECTION_LENGTH (24) /* 24 entries, 16 bytes each for OTP */
#ifndef __SYSTEM_CLOCK
# define __SYSTEM_CLOCK (16000000UL) /* 16 MHz */
#endif
#if (dg_configUSE_LP_CLK == LP_CLK_32000)
# define LP_CLK_FREQ (32000)
#elif (dg_configUSE_LP_CLK == LP_CLK_32768)
# define LP_CLK_FREQ (32768)
#elif (dg_configUSE_LP_CLK == LP_CLK_RCX)
# define LP_CLK_FREQ (0)
#else
# error "dg_configUSE_LP_CLK is not defined or has an unknown value!"
#endif
/*
* Linker symbols
*
* Note: if any of them is missing, please correct your linker script. Please refer to the linker
* script of pxp_reporter.
*/
extern uint32_t __copy_table_start__;
extern uint32_t __copy_table_end__;
extern uint32_t __zero_table_start__;
extern uint32_t __zero_table_end__;
extern uint8_t end;
extern uint8_t __HeapLimit;
/*
* Global variables
*/
__RETAINED_RW static uint8_t *heapend = &end;
__RETAINED_UNINIT __attribute__((unused)) uint32_t black_orca_chip_version;
uint32_t SystemCoreClock __RETAINED = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
uint32_t SystemLPClock __RETAINED = LP_CLK_FREQ; /*!< System Low Power Clock Frequency (LP Clock)*/
/**
* @brief Memory safe implementation of newlib's _sbrk().
*
*/
__LTO_EXT
void *_sbrk(int incr)
{
uint8_t *newheapstart;
if (heapend + incr > &__HeapLimit)
{
/* Hitting this, means that the value of _HEAP_SIZE is too small.
* The value of incr is in stored_incr at this point. By checking the equation
* above, it is straightforward to determine the missing space.
*/
volatile int stored_incr __attribute__((unused));
stored_incr = incr;
ASSERT_ERROR(0);
errno = ENOMEM;
return (void *) - 1;
}
newheapstart = heapend;
heapend += incr;
return newheapstart;
}
/**
* Apply trim values from OTP.
*
* @brief Writes the trim values located in the OTP to the corresponding system registers.
*
* @param[out] tcs_array The valid <address, value> pairs are placed in this buffer.
* @param[out] valid_entries The number of valid pairs.
*
* @return True if at least one trim value has been applied, else false.
*
*/
static bool apply_trim_values_from_otp(uint32_t *tcs_array, uint32_t *valid_entries)
{
uint32_t address;
uint32_t inverted_address;
uint32_t value;
uint32_t inverted_value;
uint32_t *p;
int i;
int index = 0;
int vdd = 0;
int retries = 0;
bool forward_reading = true;
bool res = false;
p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET);
for (i = 0; i < TCS_SECTION_LENGTH; i++)
{
do
{
address = *p;
p++;
inverted_address = *p;
p++;
value = *p;
p++;
inverted_value = *p;
p++;
if ((address == 0) && (value == 0))
{
break;
}
// Check validity
if ((address != ~inverted_address) || (value != ~inverted_value))
{
// Change LDO core voltage level and retry
vdd++;
vdd &= 0x3;
REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, vdd);
// Wait for the voltage to settle...
SysTick->CTRL = 0;
SysTick->LOAD = 500; // 500 * (62.5 * 4) = 125usec
SysTick->VAL = 0;
SysTick->CTRL = 0x5; // Start using system clock
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {}
// Adjust the read pointer
p -= 4;
}
retries++;
if (retries == 32)
{
// Unrecoverable problem! Assert in development mode
ASSERT_WARNING(0);
// Unrecoverable problem! Issue a HW reset.
hw_cpm_reset_system();
}
}
while ((address != ~inverted_address) || (value != ~inverted_value));
retries = 0;
// Read the complete TCS area but skip empty entries.
if ((address == 0) && (value == 0))
{
if ((BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, E))
|| ((dg_configUSE_AUTO_CHIP_DETECTION == 1)
&& (CHIP_IS_AE || CHIP_IS_BA)))
{
if (!forward_reading)
{
break;
}
forward_reading = false;
p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET);
p += (TCS_SECTION_LENGTH - 1) * 4;
}
else
{
(void)forward_reading;
}
continue;
}
if (!forward_reading)
{
p -= 8;
}
sys_tcs_store_pair(address, value);
tcs_array[(index * 2) + 0] = address;
tcs_array[(index * 2) + 1] = value;
*valid_entries = index + 1;
index++;
res = true;
}
return res;
}
/**
* Check whether the code has been compiled for a chip version that is compatible with the chip
* it runs on.
*/
static bool is_compatible_chip_version(void)
{
const uint32_t ver = black_orca_get_chip_version();
/* Oldest supported version is AE. */
if ((ver < BLACK_ORCA_IC_VERSION(A, E)) && (dg_configUSE_AUTO_CHIP_DETECTION == 0))
{
return false;
}
if ((ver == BLACK_ORCA_TARGET_IC) || (dg_configUSE_AUTO_CHIP_DETECTION == 1))
{
return true;
}
return false;
}
#ifdef OS_BAREMETAL
static volatile bool nortos_xtal16m_settled = false;
void XTAL16RDY_Handler(void)
{
nortos_xtal16m_settled = true;
}
/* carry out clock initialization sequence */
static void nortos_clk_setup(void)
{
// Setup DIVN
if (dg_configEXT_CRYSTAL_FREQ == EXT_CRYSTAL_IS_16M)
{
hw_cpm_set_divn(false); // External crystal is 16MHz
}
else
{
hw_cpm_set_divn(true); // External crystal is 32MHz
}
hw_cpm_enable_rc32k();
hw_cpm_lp_set_rc32k();
NVIC_ClearPendingIRQ(XTAL16RDY_IRQn);
nortos_xtal16m_settled = false;
NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ
hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K);
hw_cpm_enable_xtal16m(); // Enable XTAL16M
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
/* Wait for XTAL16M to settle */
while (!nortos_xtal16m_settled);
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M);
}
#endif /* OS_BAREMETAL */
static __RETAINED_CODE void configure_cache(void)
{
bool flush = false;
GLOBAL_INT_DISABLE();
if (dg_configCACHEABLE_QSPI_AREA_LEN != -1)
{
uint32_t cache_len;
/* dg_configCACHEABLE_QSPI_AREA_LEN must be 64KB-aligned */
ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0xFFFF) == 0);
/*
* dg_configCACHEABLE_QSPI_AREA_LEN shouldn't set any bits that do not fit in
* CACHE_CTRL2_REG.CACHE_LEN (9 bits wide) after shifting out the lower 16 bits
*/
ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0x1FF0000)
== dg_configCACHEABLE_QSPI_AREA_LEN);
/*
* set cacheable area
*
* setting CACHE_CTRL2_REG.CACHE_LEN to N, actually sets the size of the cacheable
* area to (N + 1) * 64KB
* special cases:
* N == 0 --> no caching
* N == 1 --> 128KB are cached, i.e. no way to cache only 64KB
*/
cache_len = dg_configCACHEABLE_QSPI_AREA_LEN >> 16;
/* cannot cache only 64KB! */
ASSERT_WARNING(cache_len != 1);
if (cache_len > 1)
{
cache_len--;
}
REG_SETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN, cache_len);
}
if (dg_configCACHE_ASSOCIATIVITY != CACHE_ASSOC_AS_IS)
{
if (CACHE->CACHE_ASSOCCFG_REG != dg_configCACHE_ASSOCIATIVITY)
{
/* override the set associativity setting */
CACHE->CACHE_ASSOCCFG_REG = dg_configCACHE_ASSOCIATIVITY;
flush = true;
}
}
if (dg_configCACHE_LINESZ != CACHE_LINESZ_AS_IS)
{
if (CACHE->CACHE_LNSIZECFG_REG != dg_configCACHE_LINESZ)
{
/* override the cache line setting */
CACHE->CACHE_LNSIZECFG_REG = dg_configCACHE_LINESZ;
flush = true;
}
}
if (flush && (REG_GETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN) > 0))
{
/* flush cache */
REG_SET_BIT(CACHE, CACHE_CTRL1_REG, CACHE_FLUSH);
}
GLOBAL_INT_RESTORE();
}
/**
* Basic system setup
*
* @brief Setup the AMBA clocks. Ensure proper alignment of copy and zero table entries.
*/
void SystemInitPre(void) __attribute__((section("text_reset")));
void SystemInitPre(void)
{
/*
* Enable debugger.
*/
if (dg_configENABLE_DEBUGGER)
{
ENABLE_DEBUGGER;
}
/*
* Bandgap has already been set by the bootloader.
* Use fast clocks from now on.
*/
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
/*
* Ensure 16-byte alignment for all elements of each entry in the Copy Table. This is
* a requirement imposed by the fast start-up code! If any of the assertions below hits,
* please correct your linker script file accordingly!
*/
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
{
uint32_t *p;
for (p = &__copy_table_start__; p < &__copy_table_end__; p += 3)
{
ASSERT_WARNING_UNINIT((p[0] & 0xF) == 0); // from
ASSERT_WARNING_UNINIT((p[1] & 0xF) == 0); // to
ASSERT_WARNING_UNINIT((p[2] & 0xF) == 0); // size
}
}
/*
* Ensure 32-byte alignment for all elements of each entry in the Data Table. This is
* a requirement imposed by the fast start-up code! If any of the assertions below hits,
* please correct your linker script file accordingly!
*/
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
{
uint32_t *p;
for (p = &__zero_table_start__; p < &__zero_table_end__; p += 2)
{
ASSERT_WARNING_UNINIT((p[0] & 0x1F) == 0); // start at
ASSERT_WARNING_UNINIT((p[1] & 0x1F) == 0); // size
}
}
}
/**
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
/*
* Make sure we are running on a chip version that the code has been built for.
*/
ASSERT_WARNING_UNINIT(is_compatible_chip_version());
/*
* Detect chip version (optionally).
*/
if (dg_configUSE_AUTO_CHIP_DETECTION == 1)
{
black_orca_chip_version = black_orca_get_chip_version();
if (!CHIP_IS_AE && !CHIP_IS_BA)
{
// Oldest supported version is AE.
ASSERT_WARNING_UNINIT(0);
}
}
/*
* Initialize UNINIT variables.
*/
sys_tcs_init();
/*
* BOD protection
*/
if (dg_configUSE_BOD == 1)
{
/* BOD has already been enabled at this point but it must be reconfigured */
hw_cpm_configure_bod_protection();
}
else
{
hw_cpm_deactivate_bod_protection();
}
/*
* Apply default priorities to interrupts.
*/
set_interrupt_priorities(__dialog_interrupt_priorities);
/*
* If we are executing from RAM, make sure that code written in Flash won't have left the
* system in "unknown" state.
*/
if (dg_configCODE_LOCATION == NON_VOLATILE_IS_NONE)
{
GLOBAL_INT_DISABLE();
CRG_TOP->PMU_CTRL_REG |= 0xE;
CRG_TOP->PMU_CTRL_REG &= ~1;
GLOBAL_INT_RESTORE();
}
/*
* Switch to RC16.
*/
hw_cpm_set_sysclk(SYS_CLK_IS_RC16); // Use RC16
hw_cpm_disable_xtal16m(); // Disable XTAL16M
/*
* Set highest access speed for QSPI Flash.
*/
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED)
{
hw_qspi_set_div(HW_QSPI_DIV_1);
}
}
/**
* Process the TCS
*
* @brief Process the TCS section.
*/
void SystemInitPost(void)
{
SystemCoreClock = __SYSTEM_CLOCK;
SystemLPClock = LP_CLK_FREQ;
uint32_t tcs_pairs[TCS_SECTION_LENGTH * 2];
uint32_t valid_tcs_pairs = 0;
hw_cpm_start_ldos(); // Make sure all LDOs are as expected
hw_cpm_reset_radio_vdd(); // Set Radio voltage to 1.40V
/*
* Initialize Flash
*/
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED)
{
qspi_automode_init(); // The bootloader may have left the Flash in wrong mode...
}
/*
* Retrieve trim values from OTP.
*/
hw_otpc_init(); // Start clock.
hw_otpc_disable(); // Make sure it is in standby mode.
hw_otpc_init(); // Restart clock.
hw_otpc_manual_read_on(false);
/*
* Apply trim values from OTP.
*/
apply_trim_values_from_otp(tcs_pairs, &valid_tcs_pairs);
if (dg_configIMAGE_SETUP == PRODUCTION_MODE)
{
ASSERT_ERROR(sys_tcs_is_calibrated_chip); // Uncalibrated chip!!!
}
hw_otpc_manual_read_off();
hw_otpc_disable();
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED)
{
hw_cpm_enable_qspi_init(); // Enable QSPI init after wakeup
hw_qspi_set_read_pipe_clock_delay(6); // Set read pipe clock delay to 6 (Last review date: Feb 15, 2016 - 12:25:47)
}
/*
* All trim values have been loaded from TCS or defaults are used.
*/
sys_tcs_sort_array();
sys_tcs_apply(tcs_system);
hw_cpm_set_preferred_values();
#ifdef OS_BAREMETAL
/* perform clock initialization here, as there is no CPM to do it later for us */
nortos_clk_setup();
#endif
configure_cache();
}
uint32_t DA15000_phy_addr(uint32_t addr)
{
static const uint32 remap[] =
{
MEMORY_ROM_BASE,
MEMORY_OTP_BASE,
MEMORY_QSPIF_BASE,
MEMORY_SYSRAM_BASE,
MEMORY_QSPIF_BASE,
MEMORY_OTP_BASE,
MEMORY_CACHERAM_BASE,
0
};
if (addr >= MEMORY_REMAPPED_END)
{
return addr;
}
return addr + remap[REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0)];
}
examples/platforms/da15000/uart.c
+45 -56
View File
@@ -28,99 +28,88 @@
#include <openthread/config.h>
#include <assert.h>
#include <fcntl.h>
#include <stdlib.h>
#include <unistd.h>
#include <openthread/platform/uart.h>
#include "common/code_utils.hpp"
#include "hw_gpio.h"
#include "hw_uart.h"
#include "platform-da15000.h"
static int sInFd;
static int sOutFd;
void UartBuffClear(void);
static bool sUartWriteDone = false;
static bool sUartReadDone = false;
static uint8_t sUartBuf;
static void UartSignalWrite(void *p, uint16_t transferred)
{
if (transferred)
{
sUartWriteDone = true;
}
}
static void UartSignalRead(void *p, uint16_t transferred)
{
if (transferred)
{
sUartReadDone = true;
}
}
otError otPlatUartEnable(void)
{
otError error = OT_ERROR_NONE;
uart_config uart_init =
uart_config_ex uart_init =
{
.baud_rate = HW_UART_BAUDRATE_57600,
.baud_rate = HW_UART_BAUDRATE_115200,
.data = HW_UART_DATABITS_8,
.stop = HW_UART_STOPBITS_1,
.parity = HW_UART_PARITY_NONE,
.use_dma = 0,
.stop = HW_UART_STOPBITS_1,
.auto_flow_control = 0,
.use_fifo = 1,
.rx_dma_channel = HW_DMA_CHANNEL_0,
.tx_dma_channel = HW_DMA_CHANNEL_1,
.use_dma = 1,
.tx_fifo_tr_lvl = 0,
.rx_fifo_tr_lvl = 0,
.tx_dma_channel = HW_DMA_CHANNEL_3,
.rx_dma_channel = HW_DMA_CHANNEL_2,
};
hw_uart_init(CONFIG_RETARGET_UART, &uart_init);
hw_uart_init_ex(HW_UART2, &uart_init);
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_UART_TX);
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_UART2_TX);
hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_UART_RX);
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_UART2_RX);
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_GPIO);
UartBuffClear();
return error;
hw_uart_receive(HW_UART2, &sUartBuf, 1, UartSignalRead, NULL);
return OT_ERROR_NONE;
}
otError otPlatUartDisable(void)
{
otError error = OT_ERROR_NONE;
close(sInFd);
close(sOutFd);
return error;
return OT_ERROR_NONE;
}
void da15000UartProcess(void)
{
uint8_t aBuf;
// Wait until received data are available
if (hw_uart_read_buf_empty(HW_UART1))
if (sUartReadDone)
{
return;
otPlatUartReceived(&sUartBuf, 1);
sUartReadDone = false;
hw_uart_receive(HW_UART2, &sUartBuf, 1, UartSignalRead, NULL);
}
// Read element from the receive FIFO
aBuf = UBA(HW_UART1)->UART2_RBR_THR_DLL_REG;
otPlatUartReceived(&aBuf, 1);
}
void UartBuffClear(void)
{
volatile uint8_t aBuf;
while (hw_uart_read_buf_empty(HW_UART1) == 0)
if (sUartWriteDone)
{
aBuf += UBA(HW_UART1)->UART2_RBR_THR_DLL_REG;
sUartWriteDone = false;
otPlatUartSendDone();
}
}
otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength)
{
otError error = OT_ERROR_NONE;
hw_uart_write_buffer(HW_UART1, aBuf, aBufLength);
hw_uart_send(HW_UART2, aBuf, aBufLength, UartSignalWrite, NULL);
otPlatUartSendDone();
return error;
return OT_ERROR_NONE;
}
examples/platforms/da15000/vector.c
-288
View File
@@ -1,288 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file cpu/dialog/da15000/boot/vector.c
* CpuIrq_da15x -- IRQ driver for ARM Cortex-M series cores.
*
*/
#pragma GCC diagnostic ignored "-Wpedantic"
#pragma location=".isr_vector"
#define __WEAK __attribute__((weak))
#define __USED __attribute__((used))
#define __BOOT_VECTOR __attribute__ ((section(".isr_vector")))
#define __BOOT_STACK &__stack_start__
#define __BOOT_STARTUP __gcc_program_start
typedef void (*irq_handler_t)(void);
extern unsigned int __stack_start__[];
extern void __gcc_program_start(void);
/// Declaration of default interrupt service routine
static void halt_isr(void)
{
__asm("BKPT 255");
while (1);
}
static void default_isr(void)
{
while (1);
}
/* The kernel interrupts - in their CMSIS form.
These must be implemented locally, or compiler will
give conflicting definition for __vector_table.
*/
__WEAK void NMI_Handler() { }
__WEAK void HardFault_Handler()
{
halt_isr();
}
__WEAK void SVC_Handler()
{
halt_isr();
}
__WEAK void PendSV_Handler()
{
halt_isr();
}
__WEAK void SysTick_Handler()
{
halt_isr();
}
__WEAK void MemManage_Handler()
{
halt_isr();
}
__WEAK void DebugMon_Handler()
{
halt_isr();
}
__WEAK void BusFault_Handler()
{
halt_isr();
}
/* Default handlers for other DA15X peripheral interrupts. */
__WEAK void DEBUG_IRQHandler()
{
default_isr();
}
__WEAK void BLE_WAKEUP_LP_Handler()
{
default_isr(); /* 0 */
}
__WEAK void BLE_GEN_Handler()
{
default_isr(); /* 1 */
}
__WEAK void FTDF_WAKEUP_Handler()
{
default_isr(); /* 2 */
}
__WEAK void FTDF_GEN_Handler()
{
default_isr(); /* 3 */
}
__WEAK void RFCAL_Handler()
{
default_isr(); /* 4 */
}
__WEAK void COEX_Handler()
{
default_isr(); /* 5 */
}
__WEAK void CRYPTO_Handler()
{
default_isr(); /* 6 */
}
__WEAK void MRM_Handler()
{
default_isr(); /* 7 */
}
__WEAK void UART_Handler()
{
default_isr(); /* 8 */
}
__WEAK void UART2_Handler()
{
default_isr(); /* 9 */
}
__WEAK void I2C_Handler()
{
default_isr(); /* 10 */
}
__WEAK void I2C2_Handler()
{
default_isr(); /* 11 */
}
__WEAK void SPI_Handler()
{
default_isr(); /* 12 */
}
__WEAK void SPI2_Handler()
{
default_isr(); /* 13 */
}
__WEAK void ADC_Handler()
{
default_isr(); /* 14 */
}
__WEAK void KEYBRD_Handler()
{
default_isr(); /* 15 */
}
__WEAK void IRGEN_Handler()
{
default_isr(); /* 16 */
}
__WEAK void WKUP_GPIO_Handler()
{
default_isr(); /* 17 */
}
__WEAK void SWTIM0_Handler()
{
default_isr(); /* 18 */
}
__WEAK void SWTIM1_Handler()
{
default_isr(); /* 19 */
}
__WEAK void QUADEC_Handler()
{
default_isr(); /* 20 */
}
__WEAK void USB_Handler()
{
default_isr(); /* 21 */
}
__WEAK void PCM_Handler()
{
default_isr(); /* 22 */
}
__WEAK void SRC_IN_Handler()
{
default_isr(); /* 23 */
}
__WEAK void SRC_OUT_Handler()
{
default_isr(); /* 24 */
}
__WEAK void VBUS_Handler()
{
default_isr(); /* 25 */
}
__WEAK void DMA_Handler()
{
default_isr(); /* 26 */
}
__WEAK void RF_DIAG_Handler()
{
default_isr(); /* 27 */
}
__WEAK void TRNG_Handler()
{
default_isr(); /* 28 */
}
__WEAK void DCDC_Handler()
{
default_isr(); /* 29 */
}
__WEAK void XTAL16RDY_Handler()
{
default_isr(); /* 30 */
}
__WEAK void RESERVED31_Handler()
{
default_isr(); /* 31 */
}
__BOOT_VECTOR __USED
const irq_handler_t __vector_table[] =
{
// Cortex-M vector table
(irq_handler_t)__BOOT_STACK, //INT_Initial_Stack_Pointer = 0, // Initial Stack Pointer
(irq_handler_t)__BOOT_STARTUP, //INT_Initial_Program_Counter = 1, // Initial Program Counter
NMI_Handler, //INT_NMI = 2, // Non-maskable Interrupt (NMI)
HardFault_Handler, //INT_Hard_Fault = 3, // Hard Fault
MemManage_Handler, //INT_Mem_Manage_Fault = 4, // MemManage Fault
BusFault_Handler, //INT_Bus_Fault = 5, // Bus Fault
default_isr, //INT_Usage_Fault = 6, // Usage Fault
default_isr, //INT_Reserved7 = 7, // Reserved interrupt 7
default_isr, //INT_Reserved8 = 8, // Reserved interrupt 8
default_isr, //INT_Reserved9 = 9, // Reserved interrupt 9
default_isr, //INT_Reserved10 = 10, // Reserved interrupt 10
SVC_Handler, //INT_SVCall = 11, // Supervisor call (SVCall)
DebugMon_Handler, //INT_DebugMonitor = 12, // Debug Monitor
default_isr, //INT_Reserved13 = 13, // Reserved interrupt 13
PendSV_Handler, //INT_PendableSrvReq = 14, // Pendable request for system service (PendableSrvReq)
SysTick_Handler, //INT_SysTick = 15, // SysTick Interrupt
// Dialog DA15000 vector table
BLE_WAKEUP_LP_Handler, //BLE_WAKEUP_LP_IRQn = 0, // Wakeup from Sleep by BLE Interrupt request.
BLE_GEN_Handler, //BLE_GEN_IRQn = 1, // BLE Interrupt request. Sources:
FTDF_WAKEUP_Handler, //FTDF_WAKEUP_IRQn = 2, // Wakeup from Sleep by FTDF Interrupt request.
FTDF_GEN_Handler, //FTDF_GEN_IRQn = 3, // FTDF Interrupt request. Sources:
RFCAL_Handler, //RFCAL_IRQn = 4, // RF Calibration Interrupt request. Generated by the DPHY.
COEX_Handler, //COEX_IRQn = 5, // Coex Interrupt request.
CRYPTO_Handler, //CRYPTO_IRQn = 6, // Crypto Interrupt request. Sources:
MRM_Handler, //MRM_IRQn = 7, // Cache Miss Rate Monitor Interrupt request.
UART_Handler, //UART_IRQn = 8, // UART Interrupt request.
UART2_Handler, //UART2_IRQn = 9, // UART2 Interrupt request.
I2C_Handler, //I2C_IRQn = 10, // I2C Interrupt request.
I2C2_Handler, //I2C2_IRQn = 11, // I2C2 Interrupt request.
SPI_Handler, //SPI_IRQn = 12, // SPI Interrupt request.
SPI2_Handler, //SPI2_IRQn = 13, // SPI2 Interrupt request.
ADC_Handler, //ADC_IRQn = 14, // Analog-Digital Converter Interrupt request.
KEYBRD_Handler, //KEYBRD_IRQn = 15, // Keyboard scanner Interrupt request.
IRGEN_Handler, //IRGEN_IRQn = 16, // InfraRed Generator Interrupt request.
WKUP_GPIO_Handler, //WKUP_GPIO_IRQn = 17, // Wakeup with/without debouncing Interrupt request (when system
SWTIM0_Handler, //SWTIM0_IRQn = 18, // SW Timer Interrupt request (Timer0).
SWTIM1_Handler, //SWTIM1_IRQn = 19, // SW Timer Interrupt request (Timer1).
QUADEC_Handler, //QUADEC_IRQn = 20, // Quadrature Decoder Interrupt request.
USB_Handler, //USB_IRQn = 21, // USB device FS Interrupt request.
PCM_Handler, //PCM_IRQn = 22, // PCM Interrupt request.
SRC_IN_Handler, //SRC_IN_IRQn = 23, // Sample Rate Converter Input Interrupt request.
SRC_OUT_Handler, //SRC_OUT_IRQn = 24, // Sample Rate Converter Output Interrupt request.
VBUS_Handler, //VBUS_IRQn = 25, // VBUS presence Interrupt request.
DMA_Handler, //DMA_IRQn = 26, // DMA Interrupt request.
RF_DIAG_Handler, //RF_DIAG_IRQn = 27, // Baseband or Radio Diagnostics Interrupt request.
TRNG_Handler, //TRNG_IRQn = 28, // True Random Number Generation Interrupt request.
DCDC_Handler, //DCDC_IRQn = 29, // DCDC Interrupt request. Generated upon time out threshold reach.
XTAL16RDY_Handler, //XTAL16RDY_IRQn = 30, // Indicates that XTAL16 oscillator is trimmed and settled and can
DEBUG_IRQHandler, //RESERVED31_IRQn = 31, // RESERVED31 Interrupt request.
};
examples/platforms/da15000/vector_table.S
+175
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@@ -0,0 +1,175 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file vector_table.S
* Interrupt Vector Table and Patch Table.
*/
.syntax unified
.arch armv6 - m
.section .stack
.align 3
.equ Stack_Size, __STACK_SIZE
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
.equ Heap_Size, __HEAP_SIZE
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long Default_Handler /* replaced by NMI_Handler after the ISR is copied to retRAM*/
.long Default_Handler /* replaced by HardFault_Handler after the ISR is copied to retRAM */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long BLE_WAKEUP_LP_Handler /* 0 */
.long BLE_GEN_Handler /* 1 */
.long FTDF_WAKEUP_Handler /* 2 */
.long FTDF_GEN_Handler /* 3 */
.long RFCAL_Handler /* 4 */
.long COEX_Handler /* 5 */
.long CRYPTO_Handler /* 6 */
.long MRM_Handler /* 7 */
.long UART_Handler /* 8 */
.long UART2_Handler /* 9 */
.long I2C_Handler /* 10 */
.long I2C2_Handler /* 11 */
.long SPI_Handler /* 12 */
.long SPI2_Handler /* 13 */
.long ADC_Handler /* 14 */
.long KEYBRD_Handler /* 15 */
.long IRGEN_Handler /* 16 */
.long WKUP_GPIO_Handler /* 17 */
.long SWTIM0_Handler /* 18 */
.long SWTIM1_Handler /* 19 */
.long QUADEC_Handler /* 20 */
.long USB_Handler /* 21 */
.long PCM_Handler /* 22 */
.long SRC_IN_Handler /* 23 */
.long SRC_OUT_Handler /* 24 */
.long VBUS_Handler /* 25 */
.long DMA_Handler /* 26 */
.long RF_DIAG_Handler /* 27 */
.long TRNG_Handler /* 28 */
.long DCDC_Handler /* 29 */
.long XTAL16RDY_Handler /* 30 */
.long RESERVED31_Handler /* 31 */
.size __isr_vector, . - __isr_vector
/*
* Patch Table
* Notice: it crosses the 0x100 boundary
* in cached mode, the first entries will be copied to
* (and accessed from) RAM and others will only lie on
* QSPI flash or OTP.
*
* In C declare: extern uint32_t __patch_table_start[];
*/
.section .patch_table, "a"
.align 4
.globl __patch_table_start
__patch_table_start:
/*
* 28 32-bit entries, initialized to "pointer to Default_Patch_Code"
*
* NOTE: we assume that SYS_CTRL_REG.REMAP_INTVECT == 1
*/
.long Default_Patch_Code_Handler /* 0, in RAM */
.long Default_Patch_Code_Handler /* 1, in RAM */
.long Default_Patch_Code_Handler /* 2, in RAM */
.long Default_Patch_Code_Handler /* 3, in RAM */
.long Default_Patch_Code_Handler /* 4, in RAM */
.long Default_Patch_Code_Handler /* 5, in RAM */
.long Default_Patch_Code_Handler /* 6, in RAM */
.long Default_Patch_Code_Handler /* 7, in RAM */
.long Default_Patch_Code_Handler /* 8, in RAM */
.long Default_Patch_Code_Handler /* 9, in RAM */
.long Default_Patch_Code_Handler /* 10, in RAM */
.long Default_Patch_Code_Handler /* 11, in RAM */
/*
* Chip version: AD
* Entries 12, 13, 14 and 15 are unusable and skipped in the QSPI image,
* to account for the overhead of the QSPI header (16 bytes).
*
* Chip version: AA, AC, AE
* Entries 14 and 15 are unusable and skipped in the QSPI image,
* to account for the overhead of the QSPI header (8 bytes).
*
* The mkimage tool is responsible for stripping the proper entries from the QSPI image.
*/
.long Default_Patch_Code_Handler /* 12 */
.long Default_Patch_Code_Handler /* 13 */
.long 0xDEADBEEF /* 14 */
.long 0xDEADBEEF /* 15 */
.size __patch_table_start, . - __patch_table_start
__patch_table_end:
.section .default_patch_code_handler_section, "a"
.globl Default_Patch_Code_Handler
.align 1
.thumb
.thumb_func
.type Default_Patch_Code_Handler, % function
Default_Patch_Code_Handler:
bkpt #0
bkpt #0
third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld
Vendored Executable
+234
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@@ -0,0 +1,234 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
MEMORY
{
ROM (rx) : ORIGIN = (0x8000000 + (0)), LENGTH = (512 * 1024)
RetRAM0 (rwx): ORIGIN = (0x7FC0000) + (( 64 * 1024) + ( 0 * 1024)), LENGTH = (( 24 * 1024))
RetRAM1 (rwx): ORIGIN = (0), LENGTH = 0
RAM (rw) : ORIGIN = (0x7FC0000) + ((0x200)), LENGTH = (( 64 * 1024) - (0x200))
}
ENTRY(Reset_Handler)
SECTIONS
{
.init_text :
{
KEEP(*(.isr_vector))
. = 0xC0;
KEEP(*(.patch_table))
. = 0x100;
KEEP(*(.patch_table_flash))
. = 0x130;
KEEP(*(.default_patch_code_handler_section))
. = 0x200;
*(text_reset*)
} > ROM
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext + (__data_end__ - __data_start__))
LONG (__RetRAM0_code_start__)
LONG (__RetRAM0_code_end__ - __RetRAM0_code_start__)
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
__copy_table_end__ = .;
. = ALIGN(16);
} > ROM
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__RetRAM0_data_start)
LONG (__RetRAM0_size)
LONG (__RetRAM1_start__)
LONG (__RetRAM1_end__ - __RetRAM1_start__)
__zero_table_end__ = .;
. = ALIGN(16);
} > ROM
PROVIDE_HIDDEN (__stext = .);
.text :
{
*(EXCLUDE_FILE(*libnosys.a:sbrk.o
*libgcc.a:_aeabi_uldivmod.o
*libgcc.a:_muldi3.o
*libgcc.a:_dvmd_tls.o
*libgcc.a:bpabi.o
*libgcc.a:_udivdi3.o
*libgcc.a:_clzdi2.o
*libgcc.a:_clzsi2.o) .text*)
. = ALIGN(4);
__start_adapter_init_section = .;
*(adapter_init_section)
__stop_adapter_init_section = .;
__start_bus_init_section = .;
*(bus_init_section)
__stop_bus_init_section = .;
__start_device_init_section = .;
*(device_init_section)
__stop_device_init_section = .;
KEEP(*(.init))
KEEP(*(.fini))
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
. = ALIGN(4);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
*(.rodata*)
KEEP(*(.eh_frame*))
} > ROM
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM
__exidx_end = .;
.align_s :
{
. = ALIGN(16);
} > ROM
__etext = .;
.data : AT (__etext)
{
. = ALIGN(16);
__data_start__ = .;
*(vtable)
*(EXCLUDE_FILE(*\libg_nano.a:* *\libnosys.a:*) .data*)
. = ALIGN(4);
KEEP(*(.jcr*))
. = ALIGN(16);
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(32);
__bss_start__ = .;
*(.bss.ecc_buffer)
*(EXCLUDE_FILE(*\libg_nano.a:* *\libnosys.a:*) .bss*)
*(COMMON)
. = ALIGN(32);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
PROVIDE(end = .);
*(.heap*)
__HeapLimit = .;
} > RAM
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
RETENTION_INIT0 : AT (__etext + (__data_end__ - __data_start__))
{
. = ALIGN(16);
__RetRAM0_code_start__ = .;
*(text_retained)
*libgcc.a:_aeabi_uldivmod.o (.text*)
*libgcc.a:_muldi3.o (.text*)
*libgcc.a:_dvmd_tls.o (.text*)
*libgcc.a:bpabi.o (.text*)
*libgcc.a:_udivdi3.o (.text*)
*libgcc.a:_clzdi2.o (.text*)
*libgcc.a:_clzsi2.o (.text*)
. = ALIGN(4);
*(retention_mem_init)
*(retention_mem_const)
*(privileged_data_init)
*(.retention)
*\libg_nano.a:* (.data*)
*\libnosys.a:* (.data*)
. = ALIGN(16);
__RetRAM0_code_end__ = .;
. = ALIGN(4);
} > RetRAM0
RETENTION_RAM0 (COPY) :
{
. = ALIGN(4);
__RetRAM0_start = .;
*(nmi_info)
*(hard_fault_info)
*(retention_mem_uninit)
. = ALIGN(32);
__RetRAM0_data_start = .;
*\libg_nano.a:* (.bss*)
*\libnosys.a:* (.bss*)
*(privileged_data_zi)
*(retention_mem_zi)
*(os_heap)
. = ALIGN(32);
__RetRAM0_data_end__ = .;
} > RetRAM0
RETENTION_RAM1 (COPY) :
{
. = ALIGN(32);
__RetRAM1_start__ = .;
*(privileged_data_1_zi)
*(retention_mem_1_zi)
. = ALIGN(32);
__RetRAM1_end__ = .;
} > RetRAM1
__RetRAM0_size = (__RetRAM0_data_end__ - __RetRAM0_data_start);
__image_size = __etext + (__data_end__ - __data_start__)
+ (__RetRAM0_code_end__ - __RetRAM0_code_start__)
- ORIGIN(ROM);
__mirrored_image_size = __etext + (__data_end__ - __data_start__) - ORIGIN(ROM);
}
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c
Vendored
+275
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@@ -0,0 +1,275 @@
/**
* \addtogroup BSP
* \{
* \addtogroup DEVICES
* \{
* \addtogroup GPADC
* \{
*/
/**
****************************************************************************************
*
* @file hw_gpadc.c
*
* @brief Implementation of the GPADC Low Level Driver.
*
* Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer
* program includes Confidential, Proprietary Information and is a Trade Secret of
* Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited
* unless authorized in writing. All Rights Reserved.
*
* <[email protected]> and contributors.
*
****************************************************************************************
*/
#if dg_configUSE_HW_GPADC
#include <stdio.h>
#include <string.h>
#include <hw_gpadc.h>
#if (dg_configSYSTEMVIEW)
# include "SEGGER_SYSVIEW_FreeRTOS.h"
#else
# define SEGGER_SYSTEMVIEW_ISR_ENTER()
# define SEGGER_SYSTEMVIEW_ISR_EXIT()
#endif
static hw_gpadc_interrupt_cb intr_cb = NULL;
int16_t hw_gpadc_differential_gain_error __RETAINED;
int16_t hw_gpadc_single_ended_gain_error __RETAINED;
void hw_gpadc_init(const gpadc_config *cfg)
{
GPADC->GP_ADC_CTRL_REG = 0;
GPADC->GP_ADC_CTRL2_REG = 0;
GPADC->GP_ADC_CTRL3_REG = 0x40; // default value for GP_ADDC_EN_DEL
NVIC_DisableIRQ(ADC_IRQn);
hw_gpadc_configure(cfg);
}
void hw_gpadc_reset(void)
{
GPADC->GP_ADC_CTRL_REG = REG_MSK(GPADC, GP_ADC_CTRL_REG, GP_ADC_EN);
GPADC->GP_ADC_CTRL2_REG = 0;
GPADC->GP_ADC_CTRL3_REG = 0x40; // default value for GP_ADDC_EN_DEL
NVIC_DisableIRQ(ADC_IRQn);
}
void hw_gpadc_configure(const gpadc_config *cfg)
{
if (cfg) {
hw_gpadc_set_clock(cfg->clock);
hw_gpadc_set_input_mode(cfg->input_mode);
hw_gpadc_set_input(cfg->input);
hw_gpadc_set_sample_time(cfg->sample_time);
hw_gpadc_set_continuous(cfg->continous);
hw_gpadc_set_interval(cfg->interval);
hw_gpadc_set_input_attenuator_state(cfg->input_attenuator);
hw_gpadc_set_chopping(cfg->chopping);
hw_gpadc_set_oversampling(cfg->oversampling);
}
}
void hw_gpadc_register_interrupt(hw_gpadc_interrupt_cb cb)
{
intr_cb = cb;
REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_MINT, 1);
NVIC_EnableIRQ(ADC_IRQn);
}
void hw_gpadc_unregister_interrupt(void)
{
NVIC_DisableIRQ(ADC_IRQn);
REG_SETF(GPADC, GP_ADC_CTRL_REG, GP_ADC_MINT, 0);
intr_cb = NULL;
}
void hw_gpadc_adc_measure(void)
{
hw_gpadc_start();
while (hw_gpadc_in_progress());
hw_gpadc_clear_interrupt();
}
void hw_gpadc_calibrate(void)
{
uint16_t adc_off_p, adc_off_n;
uint32_t diff;
int i;
for (i = 0; i < 5; i++) { // Try up to five times to calibrate correctly.
hw_gpadc_set_offset_positive(0x200);
hw_gpadc_set_offset_negative(0x200);
hw_gpadc_set_mute(true);
if (dg_configUSE_SOC == 1) {
hw_gpadc_set_oversampling(4);
}
hw_gpadc_set_sign_change(false);
hw_gpadc_adc_measure();
if (dg_configUSE_SOC == 1) {
adc_off_p = ((hw_gpadc_get_value_without_gain() >> 6) - 0x200);
} else {
adc_off_p = hw_gpadc_get_value() - 0x200;
}
hw_gpadc_set_sign_change(true);
hw_gpadc_adc_measure();
if (dg_configUSE_SOC == 1) {
adc_off_n = ((hw_gpadc_get_value_without_gain() >> 6) - 0x200);
} else {
adc_off_n = hw_gpadc_get_value() - 0x200;
}
if (hw_gpadc_get_input_mode() == HW_GPADC_INPUT_MODE_SINGLE_ENDED) {
hw_gpadc_set_offset_positive(0x200 - 2 * adc_off_p);
hw_gpadc_set_offset_negative(0x200 - 2 * adc_off_n);
} else {
hw_gpadc_set_offset_positive(0x200 - adc_off_p);
hw_gpadc_set_offset_negative(0x200 - adc_off_n);
}
hw_gpadc_set_sign_change(false);
// Verify calibration result
hw_gpadc_adc_measure();
if (dg_configUSE_SOC == 1) {
adc_off_n = (hw_gpadc_get_value_without_gain() >> 6);
} else {
adc_off_n = hw_gpadc_get_value();
}
if (adc_off_n > 0x200) {
diff = adc_off_n - 0x200;
}
else {
diff = 0x200 - adc_off_n;
}
if (diff < 0x8) {
break;
}
else if (i == 4) {
ASSERT_WARNING(0); // Calibration does not converge.
}
}
hw_gpadc_set_mute(false);
}
void ADC_Handler(void)
{
SEGGER_SYSTEMVIEW_ISR_ENTER();
if (intr_cb) {
intr_cb();
} else {
hw_gpadc_clear_interrupt();
}
SEGGER_SYSTEMVIEW_ISR_EXIT();
}
void hw_gpadc_test_measurements(void)
{
uint32_t val[16];
uint32_t mid = 0, diff_n = 0, diff_p = 0;
volatile bool loop = true;
if (hw_gpadc_get_input_mode() != HW_GPADC_INPUT_MODE_SINGLE_ENDED) {
hw_gpadc_set_input_mode(HW_GPADC_INPUT_MODE_SINGLE_ENDED);
hw_gpadc_set_ldo_constant_current(true);
hw_gpadc_set_ldo_dynamic_current(true);
hw_gpadc_calibrate();
}
hw_gpadc_reset();
hw_gpadc_set_input_mode(HW_GPADC_INPUT_MODE_SINGLE_ENDED);
hw_gpadc_set_ldo_constant_current(true);
hw_gpadc_set_ldo_dynamic_current(true);
hw_gpadc_set_sample_time(15);
hw_gpadc_set_chopping(true);
hw_gpadc_set_input(HW_GPADC_INPUT_SE_VBAT);
// hw_gpadc_set_oversampling(1); // 2 samples
hw_gpadc_set_oversampling(2); // 4 samples
while (loop) {
for (volatile int i = 0; i < 4; i++); // wait ~1.5usec
for (int j = 0; j < 16; j++) {
hw_gpadc_adc_measure();
// val[j] = hw_gpadc_get_raw_value() >> 4; // 2 samples
val[j] = hw_gpadc_get_raw_value() >> 3; // 4 samples
if (j == 0) {
mid = 0;
diff_p = 0;
diff_n = 0;
}
mid += val[j];
if (j == 15) {
mid /= 16;
for (int k = 0; k < 16; k++) {
if ((mid > val[k]) && (diff_p < mid - val[k])) {
diff_p = mid - val[k];
}
if ((mid < val[k]) && (diff_n < val[k] - mid)) {
diff_n = val[k] - mid;
}
}
}
}
}
}
uint16_t hw_gpadc_get_raw_value(void)
{
int32_t adc_raw_res = GPADC->GP_ADC_RESULT_REG;
int16_t gain_error = 0;
uint16_t offset_trim = 0;
if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) {
if (hw_gpadc_pre_check_for_gain_error()) {
const HW_GPADC_INPUT_MODE input_mode = hw_gpadc_get_input_mode();
if (input_mode == HW_GPADC_INPUT_MODE_DIFFERENTIAL) {
gain_error = hw_gpadc_differential_gain_error;
offset_trim = 0x8000;
} else if (input_mode == HW_GPADC_INPUT_MODE_SINGLE_ENDED) {
gain_error = hw_gpadc_single_ended_gain_error;
offset_trim = 0;
}
adc_raw_res = adc_raw_res -
((adc_raw_res - offset_trim ) * gain_error ) / 0x10000;
/* Adjust value for edge cases */
if (adc_raw_res & 0x80000000) { /* negative overflow */
return 0;
}
if (adc_raw_res & 0x7FFF0000) { /* positive overflow */
return UINT16_MAX;
}
}
}
return adc_raw_res;
}
#endif /* dg_configUSE_HW_GPADC */
/**
* \}
* \}
* \}
*/
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c
Vendored
+17 -2
View File
@@ -531,7 +531,7 @@ static void hw_uart_copy_dma_rx_to_user_buffer(HW_UART_ID uart)
UART_Data *ud = &uart_data[UARTIX(uart)];
uint16_t cur_idx;
uint16_t to_copy;
uint16_t to_copy = 0;
hw_uart_rx_callback cb;
ud->rx_dma_active = false;
@@ -1179,12 +1179,19 @@ void hw_uart_init_ex(HW_UART_ID uart, const uart_config_ex *uart_init)
*/
hw_uart_transmit_fifo_empty(uart);
if (uart == HW_UART1)
{
// there is no FIFO for UART0 as yet
ud->rx_fifo_on = 0;
ud->tx_fifo_on = 0;
#if dg_configUART_SOFTWARE_FIFO
ud->rx_soft_fifo = uart1_sw_fifo;
ud->rx_soft_fifo_size = dg_configUART1_SOFTWARE_FIFO_SIZE;
#endif
#if dg_configUART_RX_CIRCULAR_DMA
ud->rx_dma_buf = uart1_rx_dma_buf;
ud->rx_dma_buf_size = dg_configUART1_RX_CIRCULAR_DMA_BUF_SIZE;
#endif
hw_uart_disable_fifo(uart);
}
else
@@ -1193,6 +1200,14 @@ void hw_uart_init_ex(HW_UART_ID uart, const uart_config_ex *uart_init)
{
ud->rx_fifo_on = 1;
ud->tx_fifo_on = 1;
#if dg_configUART_SOFTWARE_FIFO
ud->rx_soft_fifo = uart2_sw_fifo;
ud->rx_soft_fifo_size = dg_configUART2_SOFTWARE_FIFO_SIZE;
#endif
#if dg_configUART_RX_CIRCULAR_DMA
ud->rx_dma_buf = uart2_rx_dma_buf;
ud->rx_dma_buf_size = dg_configUART2_RX_CIRCULAR_DMA_BUF_SIZE;
#endif
hw_uart_enable_fifo(uart);
ud->rx_fifo_level = uart_init->rx_fifo_tr_lvl;
hw_uart_rx_fifo_tr_lvl_setf(uart, uart_init->rx_fifo_tr_lvl);
third_party/dialog/DialogSDK/bsp/startup/config.c
Vendored Executable
+125
View File
@@ -0,0 +1,125 @@
/**
****************************************************************************************
*
* @file config.c
*
* @brief Configure system.
*
* Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer
* program includes Confidential, Proprietary Information and is a Trade Secret of
* Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited
* unless authorized in writing. All Rights Reserved.
*
* <[email protected]> and contributors.
*
****************************************************************************************
*/
/**
\addtogroup BSP
\{
\addtogroup SYSTEM
\{
\addtogroup Start-up
\{
*/
#include <stdbool.h>
#include <stdio.h>
#include "sdk_defs.h"
#include "interrupts.h"
/*
* Dialog default priority configuration table.
*
* Content of this table will be applied at system start.
*
* \note If interrupt priorities provided by Dialog need to be changed, do not modify this file.
* Create similar table with SAME name instead somewhere inside code without week attribute,
* and it will be used instead of table below.
*/
#pragma weak __dialog_interrupt_priorities
INTERRUPT_PRIORITY_CONFIG_START(__dialog_interrupt_priorities)
PRIORITY_0, /* Start interrupts with priority 0 (highest) */
SVCall_IRQn,
PendSV_IRQn,
XTAL16RDY_IRQn,
PRIORITY_1, /* Start interrupts with priority 1 */
BLE_WAKEUP_LP_IRQn,
BLE_GEN_IRQn,
FTDF_WAKEUP_IRQn,
FTDF_GEN_IRQn,
RFCAL_IRQn,
COEX_IRQn,
CRYPTO_IRQn,
RF_DIAG_IRQn,
PRIORITY_2, /* Start interrupts with priority 2 */
DMA_IRQn,
I2C_IRQn,
I2C2_IRQn,
SPI_IRQn,
SPI2_IRQn,
ADC_IRQn,
SRC_IN_IRQn,
SRC_OUT_IRQn,
TRNG_IRQn,
LAST_IRQn,
PRIORITY_3, /* Start interrupts with priority 3 (lowest) */
SysTick_IRQn,
UART_IRQn,
UART2_IRQn,
MRM_IRQn,
KEYBRD_IRQn,
IRGEN_IRQn,
WKUP_GPIO_IRQn,
SWTIM0_IRQn,
SWTIM1_IRQn,
QUADEC_IRQn,
USB_IRQn,
PCM_IRQn,
VBUS_IRQn,
DCDC_IRQn,
INTERRUPT_PRIORITY_CONFIG_END
void set_interrupt_priorities(const int8_t prios[])
{
uint32_t old_primask, iser;
int i = 0;
uint32_t prio = 0;
/*
* We shouldn't change the priority of an enabled interrupt.
* 1. Globally disable interrupts, saving the global interrupts disable state.
* 2. Explicitly disable all interrupts, saving the individual interrupt enable state.
* 3. Set interrupt priorities.
* 4. Restore individual interrupt enables.
* 5. Restore global interrupt enable state.
*/
old_primask = __get_PRIMASK();
__disable_irq();
iser = NVIC->ISER[0];
NVIC->ICER[0] = iser;
for (i = 0; prios[i] != PRIORITY_TABLE_END; ++i) {
switch (prios[i]) {
case PRIORITY_0:
case PRIORITY_1:
case PRIORITY_2:
case PRIORITY_3:
prio = prios[i] - PRIORITY_0;
break;
default:
NVIC_SetPriority(prios[i], prio);
break;
}
}
NVIC->ISER[0] = iser;
__set_PRIMASK(old_primask);
}
/**
\}
\}
\}
*/
third_party/dialog/DialogSDK/bsp/startup/startup_ARMCM0.S
Vendored Executable
+367
View File
@@ -0,0 +1,367 @@
/* File: startup_ARMCM0.S
* Purpose: startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V2.0
* Date: 16 August 2013
*/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv6-m
.section text_reset
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
#if (dg_configSKIP_MAGIC_CHECK_AT_START == 0)
/* If the Magic Word {0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEAD10CC} is found at 0x7fd0000 then the
* execution will block for a while in order to give time to a debugger to attach. */
ldr r4, =0x7fd0000
ldmia r4!, {r0-r3}
ldr r4, =0xDEADBEEF
cmp r0, r4
bne .code_starts
cmp r1, r4
bne .code_starts
cmp r2, r4
bne .code_starts
ldr r4, =0xDEAD10CC
cmp r3, r4
bne .code_starts
/* Enable debugger */
ldr r4, =0x50000012
ldrh r5, [r4]
mov r6, r5
movs r1, #128
orrs r5, r5, r1
strh r5, [r4]
/* Block for 2'' */
ldr r0, =0x150000
.delay_loop:
subs r0, #1
bgt .delay_loop
/* Make sure that this will happen only once! */
ldr r4, =0x7fd0000
movs r0, #0
str r0, [r4]
/* Restore debugger setting */
ldr r4, =0x50000012
strh r6, [r4]
.code_starts:
#endif
/* RAM shuffling configuration should be determined from the image in the QSPI Flash or OTP
* and must be applied at the beginning of the Reset Vector. The interrupt vector table must
* be copied to the RAM base after the shuffling is done.
* NOTE: Even though there is an OTP field specifically for the shuffling configuration
* we must bypass it here since the shuffling might change between different
* QSPI FLASH image versions. For OTP images RAM shuffling configuration will never change,
* but we also apply it to ignore the OTP field in any case. */
ldr r4, =0x50000012
movs r0, #0
ldrh r0, [r4]
movs r1, #0x18
bics r0, r0, r1
movs r1, #dg_configSHUFFLING_MODE<<3
orrs r0, r0, r1
/* Update SYS_CTRL_REG. */
strh r0, [r4]
/* Copy ISR VT from from QSPI Flash/OTP to RAM. This must be done
* after applying shuffling mode. */
# if (dg_configIMAGE_FLASH_OFFSET == 0)
ldr r1, =0x8000008
# else
ldr r1, =(0x8000000 + dg_configIMAGE_FLASH_OFFSET)
# endif
ldr r2, =0x7FC0000
ldr r3, =0x7FC00C0
/* Block should be a multiple of 16 to traverse correctly L_loopIV */
subs r3, r2
ble .L_loopIV_done
.L_loopIV:
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
subs r3, #16
bgt .L_loopIV
.L_loopIV_done:
bl SystemInitPre
bl SystemInit
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#define __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r0, =__copy_table_end__
.L_loop0:
cmp r4, r0
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
push {r4}
.L_loop0_0:
subs r3, #16
blt .L_loop0_0_done
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
b .L_loop0_0
.L_loop0_0_done:
pop {r4}
adds r4, #12
b .L_loop0
.L_loop0_done:
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#define __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r0, =__zero_table_end__
movs r4, 0
movs r5, r4
mov r6, r4
mov r7, r4
.L_loop2:
cmp r3, r0
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
.L_loop2_0:
subs r2, #32 // Requires 32-byte alignment!
blt .L_loop2_0_done
stmia r1!, {r4-r7}
stmia r1!, {r4-r7}
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
/* Copy the address of the retained NMI and HardFault handlers to the vector table. */
ldr r0, =0x7FC0008
ldr r1, =NMI_Handler
str r1, [r0, #0]
ldr r1, =HardFault_Handler
str r1, [r0, #4]
bl SystemInitPost
bl main
.pool
.size Reset_Handler, . - Reset_Handler
.text
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
/*
* enable debugger:
* CRG_TOP->SYS_CTRL_REG_b.DEBUGGER_ENABLE = 1;
*/
movs r1, #0x50
lsls r1, #24
ldrh r2, [r1, #0x12]
movs r3, #0x80
orrs r2, r2, r3
strh r2, [r1, #0x12]
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.thumb
.thumb_func
.align 1
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler BLE_WAKEUP_LP_Handler
def_irq_handler BLE_GEN_Handler
def_irq_handler FTDF_WAKEUP_Handler
def_irq_handler FTDF_GEN_Handler
def_irq_handler RFCAL_Handler
def_irq_handler COEX_Handler
def_irq_handler CRYPTO_Handler
def_irq_handler MRM_Handler
def_irq_handler UART_Handler
def_irq_handler UART2_Handler
def_irq_handler I2C_Handler
def_irq_handler I2C2_Handler
def_irq_handler SPI_Handler
def_irq_handler SPI2_Handler
def_irq_handler ADC_Handler
def_irq_handler KEYBRD_Handler
def_irq_handler IRGEN_Handler
def_irq_handler WKUP_GPIO_Handler
def_irq_handler SWTIM0_Handler
def_irq_handler SWTIM1_Handler
def_irq_handler QUADEC_Handler
def_irq_handler USB_Handler
def_irq_handler PCM_Handler
def_irq_handler SRC_IN_Handler
def_irq_handler SRC_OUT_Handler
def_irq_handler VBUS_Handler
def_irq_handler DMA_Handler
def_irq_handler RF_DIAG_Handler
def_irq_handler TRNG_Handler
def_irq_handler DCDC_Handler
def_irq_handler XTAL16RDY_Handler
def_irq_handler RESERVED31_Handler
.section text_retained
.align 1
.thumb
.thumb_func
.globl NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r1, =NMI_HandlerC
movs r0, #4
mov r2, lr
tst r0, r2
beq NMI_stacking_using_MSP
mrs r0, psp
b stack_check
NMI_stacking_using_MSP:
mrs r0, msp
b stack_check
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb
.thumb_func
.globl HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r1, =HardFault_HandlerC
movs r0, #4
mov r2, lr
tst r0, r2
beq HF_stacking_using_MSP
mrs r0, psp
b stack_check
HF_stacking_using_MSP:
mrs r0, msp
stack_check:
/* 0x7FC0000 is start of RAM */
ldr r2, =0x7FC0000
cmp r0, r2
blt Wrong_SP
/* Check SYS_CTRL_REG:CACHERAM_MUX */
ldr r2, =0x50000012
ldrh r2, [r2]
movs r3, #1
lsls r3, r3, #10
ands r2, r2, r3
bne cache_is_on
/* 0x7FE4000 marks end of RAM (assuming that the CACHE is used as RAM) */
ldr r2, =0x7FE4000-32
b check_end_of_ram
cache_is_on:
/* 0x7FE0000 marks end of RAM */
ldr r2, =0x7FE0000-32
check_end_of_ram:
cmp r0, r2
bgt Wrong_SP
bx r1
Wrong_SP:
/* Freeze WDog at all times */
ldr r0, =0x50003300
ldr r1, =8
strh r1, [r0, #0]
/* Enable debugger at all times */
ldr r4, =0x50000012
ldrh r0, [r4, #0]
movs r1, #0x80
orrs r0, r0, r1
/* Update SYS_CTRL_REG */
strh r0, [r4, #0]
/* Wait for the WDog to hit or a debug session to start */
b .
.size HardFault_Handler, . - HardFault_Handler
.end
third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c
Vendored Executable
+571
View File
@@ -0,0 +1,571 @@
/**************************************************************************//**
* @file system_ARMCM0.c
* @brief CMSIS Device System Source File for
* ARMCM0 Device Series
* @version V2.00
* @date 18. August 2015
******************************************************************************/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <sys/errno.h>
#include "sdk_defs.h"
#include "interrupts.h"
#include "hw_cpm.h"
#include "hw_otpc.h"
#include "hw_qspi.h"
#include "hw_watchdog.h"
#include "sys_tcs.h"
#include "qspi_automode.h"
/*
* This is just so that compilation doesn't break for RAM builds.
* The code that uses it is optimized out in RAM builds.
*/
extern uint32_t NVMS_PARAM_PART_end;
/*
* TCS Offsets
*/
#define OTP_HEADER_BASE_ADDR_IN_OTP (0x7F8E9C0)
#define TCS_SECTION_OFFSET (184) /* 0x7F8EA78 - 0x7F8E9C0 */
#define TCS_SECTION_LENGTH (24) /* 24 entries, 16 bytes each for OTP */
#ifndef __SYSTEM_CLOCK
# define __SYSTEM_CLOCK (16000000UL) /* 16 MHz */
#endif
#if (dg_configUSE_LP_CLK == LP_CLK_32000)
# define LP_CLK_FREQ (32000)
#elif (dg_configUSE_LP_CLK == LP_CLK_32768)
# define LP_CLK_FREQ (32768)
#elif (dg_configUSE_LP_CLK == LP_CLK_RCX)
# define LP_CLK_FREQ (0)
#else
# error "dg_configUSE_LP_CLK is not defined or has an unknown value!"
#endif
/*
* Linker symbols
*
* Note: if any of them is missing, please correct your linker script. Please refer to the linker
* script of pxp_reporter.
*/
extern uint32_t __copy_table_start__;
extern uint32_t __copy_table_end__;
extern uint32_t __zero_table_start__;
extern uint32_t __zero_table_end__;
extern uint8_t end;
extern uint8_t __HeapLimit;
/*
* Global variables
*/
__RETAINED_RW static uint8_t *heapend = &end;
__RETAINED_UNINIT __attribute__((unused)) uint32_t black_orca_chip_version;
uint32_t SystemCoreClock __RETAINED = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
uint32_t SystemLPClock __RETAINED = LP_CLK_FREQ; /*!< System Low Power Clock Frequency (LP Clock)*/
/**
* @brief Memory safe implementation of newlib's _sbrk().
*
*/
__LTO_EXT
void *_sbrk(int incr)
{
uint8_t *newheapstart;
if (heapend + incr > &__HeapLimit) {
/* Hitting this, means that the value of _HEAP_SIZE is too small.
* The value of incr is in stored_incr at this point. By checking the equation
* above, it is straightforward to determine the missing space.
*/
volatile int stored_incr __attribute__((unused));
stored_incr = incr;
ASSERT_ERROR(0);
errno = ENOMEM;
return (void *)-1;
}
newheapstart = heapend;
heapend += incr;
return newheapstart;
}
/**
* Apply trim values from OTP.
*
* @brief Writes the trim values located in the OTP to the corresponding system registers.
*
* @param[out] tcs_array The valid <address, value> pairs are placed in this buffer.
* @param[out] valid_entries The number of valid pairs.
*
* @return True if at least one trim value has been applied, else false.
*
*/
static bool apply_trim_values_from_otp(uint32_t *tcs_array, uint32_t *valid_entries)
{
uint32_t address;
uint32_t inverted_address;
uint32_t value;
uint32_t inverted_value;
uint32_t *p;
int i;
int index = 0;
int vdd = 0;
int retries = 0;
bool forward_reading = true;
bool res = false;
p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET);
for (i = 0; i < TCS_SECTION_LENGTH; i++) {
do {
address = *p;
p++;
inverted_address = *p;
p++;
value = *p;
p++;
inverted_value = *p;
p++;
if ((address == 0) && (value == 0)) {
break;
}
// Check validity
if ((address != ~inverted_address) || (value != ~inverted_value)) {
// Change LDO core voltage level and retry
vdd++;
vdd &= 0x3;
REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, vdd);
// Wait for the voltage to settle...
SysTick->CTRL = 0;
SysTick->LOAD = 500; // 500 * (62.5 * 4) = 125usec
SysTick->VAL = 0;
SysTick->CTRL = 0x5; // Start using system clock
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {}
// Adjust the read pointer
p -= 4;
}
retries++;
if (retries == 32) {
// Unrecoverable problem! Assert in development mode
ASSERT_WARNING(0);
// Unrecoverable problem! Issue a HW reset.
hw_cpm_reset_system();
}
} while ((address != ~inverted_address) || (value != ~inverted_value));
retries = 0;
// Read the complete TCS area but skip empty entries.
if ((address == 0) && (value == 0)) {
if ((BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, E))
|| ((dg_configUSE_AUTO_CHIP_DETECTION == 1)
&& (CHIP_IS_AE || CHIP_IS_BA))) {
if (!forward_reading) {
break;
}
forward_reading = false;
p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET);
p += (TCS_SECTION_LENGTH - 1) * 4;
}
else {
(void)forward_reading;
}
continue;
}
if (!forward_reading) {
p -= 8;
}
sys_tcs_store_pair(address, value);
tcs_array[(index * 2) + 0] = address;
tcs_array[(index * 2) + 1] = value;
*valid_entries = index + 1;
index++;
res = true;
}
return res;
}
/**
* Check whether the code has been compiled for a chip version that is compatible with the chip
* it runs on.
*/
static bool is_compatible_chip_version(void)
{
const uint32_t ver = black_orca_get_chip_version();
/* Oldest supported version is AE. */
if ((ver < BLACK_ORCA_IC_VERSION(A, E)) && (dg_configUSE_AUTO_CHIP_DETECTION == 0)) {
return false;
}
if ((ver == BLACK_ORCA_TARGET_IC) || (dg_configUSE_AUTO_CHIP_DETECTION == 1)) {
return true;
}
return false;
}
#ifdef OS_BAREMETAL
static volatile bool nortos_xtal16m_settled = false;
void XTAL16RDY_Handler(void)
{
nortos_xtal16m_settled = true;
}
/* carry out clock initialization sequence */
static void nortos_clk_setup(void)
{
// Setup DIVN
if (dg_configEXT_CRYSTAL_FREQ == EXT_CRYSTAL_IS_16M) {
hw_cpm_set_divn(false); // External crystal is 16MHz
}
else {
hw_cpm_set_divn(true); // External crystal is 32MHz
}
hw_cpm_enable_rc32k();
hw_cpm_lp_set_rc32k();
NVIC_ClearPendingIRQ(XTAL16RDY_IRQn);
nortos_xtal16m_settled = false;
NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ
hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K);
hw_cpm_enable_xtal16m(); // Enable XTAL16M
hw_watchdog_unfreeze(); // Start watchdog
while(!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
/* Wait for XTAL16M to settle */
while(!nortos_xtal16m_settled);
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M);
}
#endif /* OS_BAREMETAL */
static __RETAINED_CODE void configure_cache(void)
{
bool flush = false;
GLOBAL_INT_DISABLE();
if (dg_configCACHEABLE_QSPI_AREA_LEN != -1) {
uint32_t cache_len;
/* dg_configCACHEABLE_QSPI_AREA_LEN must be 64KB-aligned */
ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0xFFFF) == 0);
/*
* dg_configCACHEABLE_QSPI_AREA_LEN shouldn't set any bits that do not fit in
* CACHE_CTRL2_REG.CACHE_LEN (9 bits wide) after shifting out the lower 16 bits
*/
ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0x1FF0000)
== dg_configCACHEABLE_QSPI_AREA_LEN);
/*
* set cacheable area
*
* setting CACHE_CTRL2_REG.CACHE_LEN to N, actually sets the size of the cacheable
* area to (N + 1) * 64KB
* special cases:
* N == 0 --> no caching
* N == 1 --> 128KB are cached, i.e. no way to cache only 64KB
*/
cache_len = dg_configCACHEABLE_QSPI_AREA_LEN >> 16;
/* cannot cache only 64KB! */
ASSERT_WARNING(cache_len != 1);
if (cache_len > 1) {
cache_len--;
}
REG_SETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN, cache_len);
}
if (dg_configCACHE_ASSOCIATIVITY != CACHE_ASSOC_AS_IS) {
if (CACHE->CACHE_ASSOCCFG_REG != dg_configCACHE_ASSOCIATIVITY) {
/* override the set associativity setting */
CACHE->CACHE_ASSOCCFG_REG = dg_configCACHE_ASSOCIATIVITY;
flush = true;
}
}
if (dg_configCACHE_LINESZ != CACHE_LINESZ_AS_IS) {
if (CACHE->CACHE_LNSIZECFG_REG != dg_configCACHE_LINESZ) {
/* override the cache line setting */
CACHE->CACHE_LNSIZECFG_REG = dg_configCACHE_LINESZ;
flush = true;
}
}
if (flush && (REG_GETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN) > 0)) {
/* flush cache */
REG_SET_BIT(CACHE, CACHE_CTRL1_REG, CACHE_FLUSH);
}
GLOBAL_INT_RESTORE();
}
/**
* Basic system setup
*
* @brief Setup the AMBA clocks. Ensure proper alignment of copy and zero table entries.
*/
void SystemInitPre(void) __attribute__((section("text_reset")));
void SystemInitPre(void)
{
/*
* Enable debugger.
*/
if (dg_configENABLE_DEBUGGER) {
ENABLE_DEBUGGER;
}
/*
* Bandgap has already been set by the bootloader.
* Use fast clocks from now on.
*/
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
/*
* Ensure 16-byte alignment for all elements of each entry in the Copy Table. This is
* a requirement imposed by the fast start-up code! If any of the assertions below hits,
* please correct your linker script file accordingly!
*/
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) {
uint32_t *p;
for (p = &__copy_table_start__; p < &__copy_table_end__; p += 3) {
ASSERT_WARNING_UNINIT( (p[0] & 0xF) == 0 ); // from
ASSERT_WARNING_UNINIT( (p[1] & 0xF) == 0 ); // to
ASSERT_WARNING_UNINIT( (p[2] & 0xF) == 0 ); // size
}
}
/*
* Ensure 32-byte alignment for all elements of each entry in the Data Table. This is
* a requirement imposed by the fast start-up code! If any of the assertions below hits,
* please correct your linker script file accordingly!
*/
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) {
uint32_t *p;
for (p = &__zero_table_start__; p < &__zero_table_end__; p += 2) {
ASSERT_WARNING_UNINIT( (p[0] & 0x1F) == 0 ); // start at
ASSERT_WARNING_UNINIT( (p[1] & 0x1F) == 0 ); // size
}
}
}
/**
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
/*
* Make sure we are running on a chip version that the code has been built for.
*/
ASSERT_WARNING_UNINIT(is_compatible_chip_version());
/*
* Detect chip version (optionally).
*/
if (dg_configUSE_AUTO_CHIP_DETECTION == 1) {
black_orca_chip_version = black_orca_get_chip_version();
if (!CHIP_IS_AE && !CHIP_IS_BA) {
// Oldest supported version is AE.
ASSERT_WARNING_UNINIT(0);
}
}
/*
* Initialize UNINIT variables.
*/
sys_tcs_init();
/*
* BOD protection
*/
if (dg_configUSE_BOD == 1) {
/* BOD has already been enabled at this point but it must be reconfigured */
hw_cpm_configure_bod_protection();
} else {
hw_cpm_deactivate_bod_protection();
}
/*
* Apply default priorities to interrupts.
*/
set_interrupt_priorities(__dialog_interrupt_priorities);
/*
* If we are executing from RAM, make sure that code written in Flash won't have left the
* system in "unknown" state.
*/
if (dg_configCODE_LOCATION == NON_VOLATILE_IS_NONE) {
GLOBAL_INT_DISABLE();
CRG_TOP->PMU_CTRL_REG |= 0xE;
CRG_TOP->PMU_CTRL_REG &= ~1;
GLOBAL_INT_RESTORE();
}
/*
* Switch to RC16.
*/
hw_cpm_set_sysclk(SYS_CLK_IS_RC16); // Use RC16
hw_cpm_disable_xtal16m(); // Disable XTAL16M
/*
* Set highest access speed for QSPI Flash.
*/
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) {
hw_qspi_set_div(HW_QSPI_DIV_1);
}
}
/**
* Process the TCS
*
* @brief Process the TCS section.
*/
void SystemInitPost(void)
{
SystemCoreClock = __SYSTEM_CLOCK;
SystemLPClock = LP_CLK_FREQ;
uint32_t tcs_pairs[TCS_SECTION_LENGTH * 2];
uint32_t valid_tcs_pairs = 0;
hw_cpm_start_ldos(); // Make sure all LDOs are as expected
hw_cpm_reset_radio_vdd(); // Set Radio voltage to 1.40V
/*
* Initialize Flash
*/
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) {
qspi_automode_init(); // The bootloader may have left the Flash in wrong mode...
}
/*
* Retrieve trim values from OTP.
*/
hw_otpc_init(); // Start clock.
hw_otpc_disable(); // Make sure it is in standby mode.
hw_otpc_init(); // Restart clock.
hw_otpc_manual_read_on(false);
/*
* Apply trim values from OTP.
*/
apply_trim_values_from_otp(tcs_pairs, &valid_tcs_pairs);
if (dg_configIMAGE_SETUP == PRODUCTION_MODE) {
ASSERT_ERROR(sys_tcs_is_calibrated_chip); // Uncalibrated chip!!!
}
hw_otpc_manual_read_off();
hw_otpc_disable();
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED) {
hw_cpm_enable_qspi_init(); // Enable QSPI init after wakeup
hw_qspi_set_read_pipe_clock_delay(6); // Set read pipe clock delay to 6 (Last review date: Feb 15, 2016 - 12:25:47)
}
/*
* All trim values have been loaded from TCS or defaults are used.
*/
sys_tcs_sort_array();
sys_tcs_apply(tcs_system);
hw_cpm_set_preferred_values();
#ifdef OS_BAREMETAL
/* perform clock initialization here, as there is no CPM to do it later for us */
nortos_clk_setup();
#endif
configure_cache();
}
uint32_t DA15000_phy_addr(uint32_t addr)
{
static const uint32 remap[] = {
MEMORY_ROM_BASE,
MEMORY_OTP_BASE,
MEMORY_QSPIF_BASE,
MEMORY_SYSRAM_BASE,
MEMORY_QSPIF_BASE,
MEMORY_OTP_BASE,
MEMORY_CACHERAM_BASE,
0
};
if (addr >= MEMORY_REMAPPED_END)
return addr;
return addr + remap[REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0)];
}
__extension__ typedef int __guard __attribute__((mode(__DI__)));
int __cxa_guard_acquire(__guard *g) { return !*(char *)(g); }
void __cxa_guard_release(__guard *g) { *(char *)g = 1; }
void __cxa_guard_abort(__guard *g) { (void)g; }
void __cxa_pure_virtual(void) { while (1); }
third_party/dialog/DialogSDK/bsp/startup/vector_table.S
Vendored Executable
+159
View File
@@ -0,0 +1,159 @@
/**
****************************************************************************************
*
* @file vector_table.S
*
* @brief Interrupt Vector Table and Patch Table
*
* Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer
* program includes Confidential, Proprietary Information and is a Trade Secret of
* Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited
* unless authorized in writing. All Rights Reserved.
*
* <black.orca.support@diasemi.com> and contributors.
*
****************************************************************************************
*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
.equ Stack_Size, __STACK_SIZE
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
.equ Heap_Size, __HEAP_SIZE
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long Default_Handler /* replaced by NMI_Handler after the ISR is copied to retRAM*/
.long Default_Handler /* replaced by HardFault_Handler after the ISR is copied to retRAM */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long BLE_WAKEUP_LP_Handler /* 0 */
.long BLE_GEN_Handler /* 1 */
.long FTDF_WAKEUP_Handler /* 2 */
.long FTDF_GEN_Handler /* 3 */
.long RFCAL_Handler /* 4 */
.long COEX_Handler /* 5 */
.long CRYPTO_Handler /* 6 */
.long MRM_Handler /* 7 */
.long UART_Handler /* 8 */
.long UART2_Handler /* 9 */
.long I2C_Handler /* 10 */
.long I2C2_Handler /* 11 */
.long SPI_Handler /* 12 */
.long SPI2_Handler /* 13 */
.long ADC_Handler /* 14 */
.long KEYBRD_Handler /* 15 */
.long IRGEN_Handler /* 16 */
.long WKUP_GPIO_Handler /* 17 */
.long SWTIM0_Handler /* 18 */
.long SWTIM1_Handler /* 19 */
.long QUADEC_Handler /* 20 */
.long USB_Handler /* 21 */
.long PCM_Handler /* 22 */
.long SRC_IN_Handler /* 23 */
.long SRC_OUT_Handler /* 24 */
.long VBUS_Handler /* 25 */
.long DMA_Handler /* 26 */
.long RF_DIAG_Handler /* 27 */
.long TRNG_Handler /* 28 */
.long DCDC_Handler /* 29 */
.long XTAL16RDY_Handler /* 30 */
.long RESERVED31_Handler /* 31 */
.size __isr_vector, . - __isr_vector
/*
* Patch Table
* Notice: it crosses the 0x100 boundary
* in cached mode, the first entries will be copied to
* (and accessed from) RAM and others will only lie on
* QSPI flash or OTP.
*
* In C declare: extern uint32_t __patch_table_start[];
*/
.section .patch_table, "a"
.align 4
.globl __patch_table_start
__patch_table_start:
/*
* 28 32-bit entries, initialized to "pointer to Default_Patch_Code"
*
* NOTE: we assume that SYS_CTRL_REG.REMAP_INTVECT == 1
*/
.long Default_Patch_Code_Handler /* 0, in RAM */
.long Default_Patch_Code_Handler /* 1, in RAM */
.long Default_Patch_Code_Handler /* 2, in RAM */
.long Default_Patch_Code_Handler /* 3, in RAM */
.long Default_Patch_Code_Handler /* 4, in RAM */
.long Default_Patch_Code_Handler /* 5, in RAM */
.long Default_Patch_Code_Handler /* 6, in RAM */
.long Default_Patch_Code_Handler /* 7, in RAM */
.long Default_Patch_Code_Handler /* 8, in RAM */
.long Default_Patch_Code_Handler /* 9, in RAM */
.long Default_Patch_Code_Handler /* 10, in RAM */
.long Default_Patch_Code_Handler /* 11, in RAM */
/*
* Chip version: AD
* Entries 12, 13, 14 and 15 are unusable and skipped in the QSPI image,
* to account for the overhead of the QSPI header (16 bytes).
*
* Chip version: AA, AC, AE
* Entries 14 and 15 are unusable and skipped in the QSPI image,
* to account for the overhead of the QSPI header (8 bytes).
*
* The mkimage tool is responsible for stripping the proper entries from the QSPI image.
*/
.long Default_Patch_Code_Handler /* 12 */
.long Default_Patch_Code_Handler /* 13 */
.long 0xDEADBEEF /* 14 */
.long 0xDEADBEEF /* 15 */
.size __patch_table_start, . - __patch_table_start
__patch_table_end:
.section .default_patch_code_handler_section, "a"
.globl Default_Patch_Code_Handler
.align 1
.thumb
.thumb_func
.type Default_Patch_Code_Handler, %function
Default_Patch_Code_Handler:
bkpt #0
bkpt #0