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https://github.com/NVIDIA/TensorRT-LLM.git
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112 lines
6.4 KiB
Markdown
112 lines
6.4 KiB
Markdown
(support-matrix)=
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# Support Matrix
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TensorRT-LLM optimizes the performance of a range of well-known models on NVIDIA GPUs. The following sections provide a list of supported GPU architectures as well as important features implemented in TensorRT-LLM.
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(support-matrix-hardware)=
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## Hardware
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The following table shows the supported hardware for TensorRT-LLM.
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If a GPU is not listed, it is important to note that TensorRT-LLM is expected to work on GPUs based on the Volta, Turing, Ampere, Hopper, and Ada Lovelace architectures. Certain limitations may, however, apply.
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```{eval-rst}
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.. list-table::
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:header-rows: 1
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:widths: 20 80
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* -
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- Hardware Compatibility
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* - Operating System
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- TensorRT-LLM requires Linux x86_64 or Windows.
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* - GPU Model Architectures
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-
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- `NVIDIA Hopper H100 GPU <https://www.nvidia.com/en-us/data-center/h100/>`_
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- `NVIDIA L40S GPU <https://www.nvidia.com/en-us/data-center/l40s/>`_
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- `NVIDIA Ada Lovelace GPU <https://www.nvidia.com/en-us/technologies/ada-architecture/>`_
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- `NVIDIA Ampere A100 GPU <https://www.nvidia.com/en-us/data-center/a100/>`_
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- `NVIDIA A30 GPU <https://www.nvidia.com/en-us/data-center/products/a30-gpu/>`_
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- `NVIDIA Turing T4 GPU <https://www.nvidia.com/en-us/data-center/tesla-t4/>`_
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- `NVIDIA Volta V100 GPU <https://www.nvidia.com/en-us/data-center/v100/>`_ (experimental)
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```
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(support-matrix-software)=
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## Software
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The following table shows the supported software for TensorRT-LLM.
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```{eval-rst}
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.. list-table::
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:header-rows: 1
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:widths: 20 80
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* -
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- Software Compatibility
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* - Container
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- [23.10](https://docs.nvidia.com/deeplearning/frameworks/support-matrix/index.html#framework-matrix-2023)
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* - TensorRT
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- [9.2](https://docs.nvidia.com/deeplearning/tensorrt/release-notes/index.html)
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* - Precision
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-
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- Hopper (SM90) - FP32, FP16, BF16, FP8, INT8, INT4
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- Ada Lovelace (SM89) - FP32, FP16, BF16, FP8, INT8, INT4
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- Ampere (SM80, SM86) - FP32, FP16, BF16, INT8, INT4(3)
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- Turing (SM75) - FP32, FP16, INT8(1), INT4(2)
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- Volta (SM70) - FP32, FP16, INT8(1), INT4(2)
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* - Models
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-
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- [Baichuan](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/baichuan)
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- [BART](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [BERT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bert)
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- [Blip2](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [BLOOM](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bloom)
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- [ChatGLM](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/chatglm)
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- [DBRX](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/dbrx)
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- [FairSeq NMT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [Falcon](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/falcon)
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- [Flan-T5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec) (4)
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- [Gemma](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gemma)
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- [GPT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt)
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- [GPT-J](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gptj)
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- [GPT-Nemo](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt)
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- [GPT-NeoX](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gptneox)
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- [InternLM](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/internlm)
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- [LLaMA](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama)
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- [LLaMA-v2](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama)
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- [Mamba](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mamba)
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- [mBART](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [Mistral](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mixtral)
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- [MPT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mpt)
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- [mT5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [OPT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/opt)
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- [Phi-1.5/Phi-2](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/phi)
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- [Qwen](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/qwen)
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- [Qwen-VL](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/qwenvl)
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- [Replit Code](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mpt)
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- [RoBERTa](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bert)
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- [SantaCoder](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt)
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- [Skywork](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/skywork)
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- [Smaug](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/smaug)
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- [StarCoder](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt)
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- [T5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [Whisper](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/whisper)
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* - Multi-Modal Models (5)
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-
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- [BLIP2 w/ OPT-2.7B](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [BLIP2 w/ T5-XL](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [LLaVA-v1.5-7B](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [Nougat family](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal) Nougat-small, Nougat-base
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```
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(1) INT8 SmoothQuant is not supported on SM70 and SM75.<br>
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(2) INT4 AWQ and GPTQ are not supported on SM < 80.<br>
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(3) INT4 AWQ and GPTQ with FP8 activations require SM >= 89.<br>
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(4) [Encoder-Decoder](https://github.com/NVIDIA/TensorRT-LLM/tree/main/main/examples/enc_dec) provides general encoder-decoder functionality that supports many encoder-decoder models such as T5 family, BART family, Whisper family, NMT family, and so on.
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(5) Multi-modal provides general multi-modal functionality that supports many multi-modal architectures such as BLIP family, LLaVA family, and so on.
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```{note}
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Support for FP8 and quantized data types (INT8 or INT4) is not implemented for all the models. Refer to {ref}`precision` and [examples](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples) folder for additional information.
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```
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