mirror of
https://github.com/NVIDIA/TensorRT-LLM.git
synced 2026-01-14 06:27:45 +08:00
131 lines
6.9 KiB
Markdown
131 lines
6.9 KiB
Markdown
(support-matrix)=
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# Support Matrix
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TensorRT-LLM optimizes the performance of a range of well-known models on NVIDIA GPUs. The following sections provide a list of supported GPU architectures as well as important features implemented in TensorRT-LLM.
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## Models
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### LLM Models
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- [Arctic](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/arctic)
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- [Baichuan/Baichuan2](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/baichuan)
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- [BART](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [BERT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bert)
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- [BLOOM](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bloom)
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- [ByT5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [GLM/ChatGLM/ChatGLM2/ChatGLM3/GLM-4](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/chatglm)
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- [Code LLaMA](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama)
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- [DBRX](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/dbrx)
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- [Exaone](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/exaone)
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- [FairSeq NMT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [Falcon](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/falcon)
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- [Flan-T5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec) [^encdec]
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- [Gemma/Gemma2](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gemma)
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- [GPT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt)
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- [GPT-J](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gptj)
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- [GPT-Nemo](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt)
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- [GPT-NeoX](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gptneox)
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- [Grok-1](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/grok)
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- [InternLM](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/internlm)
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- [InternLM2](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/internlm2)
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- [LLaMA/LLaMA 2/LLaMA 3/LLaMA 3.1](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama)
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- [Mamba](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mamba)
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- [mBART](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [Mistral](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama)
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- [Mistral NeMo](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/llama)
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- [Mixtral](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mixtral)
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- [MPT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mpt)
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- [Nemotron](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/nemotron)
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- [mT5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [OPT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/opt)
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- [Phi-1.5/Phi-2/Phi-3](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/phi)
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- [Qwen/Qwen1.5/Qwen2](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/qwen)
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- [Qwen-VL](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/qwenvl)
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- [RecurrentGemma](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/recurrentgemma)
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- [Replit Code](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/mpt)[^ReplitCode]
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- [RoBERTa](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/bert)
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- [SantaCoder](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt)
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- [Skywork](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/skywork)
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- [Smaug](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/smaug)
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- [StarCoder](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/gpt)
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- [T5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/enc_dec)
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- [Whisper](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/whisper)
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### Multi-Modal Models [^multimod]
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- [BLIP2 w/ OPT](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [BLIP2 w/ T5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [CogVLM](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal) [^bf16only]
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- [Deplot](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [Fuyu](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [Kosmos](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [LLaVA-v1.5](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [LLaVa-Next](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [NeVA](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [Nougat](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [Phi-3-vision](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [Video NeVA](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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- [VILA](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples/multimodal)
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(support-matrix-hardware)=
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## Hardware
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The following table shows the supported hardware for TensorRT-LLM.
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If a GPU architecture is not listed, the TensorRT-LLM team does not develop or test the software on the architecture and support is limited to community support.
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In addition, older architectures can have limitations for newer software releases.
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```{list-table}
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:header-rows: 1
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:widths: 20 80
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* -
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- Hardware Compatibility
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* - Operating System
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- TensorRT-LLM requires Linux x86_64 or Windows.
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* - GPU Model Architectures
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-
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- [NVIDIA Hopper Architecture](https://www.nvidia.com/en-us/data-center/technologies/hopper-architecture/)
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- [NVIDIA Ada Lovelace Architecture](https://www.nvidia.com/en-us/technologies/ada-architecture/)
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- [NVIDIA Ampere Architecture](https://www.nvidia.com/en-us/data-center/ampere-architecture/)
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```
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(support-matrix-software)=
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## Software
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The following table shows the supported software for TensorRT-LLM.
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```{list-table}
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:header-rows: 1
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:widths: 20 80
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* -
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- Software Compatibility
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* - Container
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- [24.09](https://docs.nvidia.com/deeplearning/frameworks/support-matrix/index.html)
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* - TensorRT
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- [10.5](https://docs.nvidia.com/deeplearning/tensorrt/release-notes/index.html)
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* - Precision
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-
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- Hopper (SM90) - FP32, FP16, BF16, FP8, INT8, INT4
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- Ada Lovelace (SM89) - FP32, FP16, BF16, FP8, INT8, INT4
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- Ampere (SM80, SM86) - FP32, FP16, BF16, INT8, INT4[^smgte89]
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```
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[^ReplitCode]：Replit Code is not supported with the transformers 4.45+.
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[^smgte89]: INT4 AWQ and GPTQ with FP8 activations require SM >= 89.
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[^encdec]: Encoder-Decoder provides general encoder-decoder functionality that supports many encoder-decoder models such as T5 family, BART family, Whisper family, NMT family, and so on.
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[^multimod]: Multi-modal provides general multi-modal functionality that supports many multi-modal architectures such as BLIP2 family, LLaVA family, and so on.
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[^bf16only]: Only supports bfloat16 precision.
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```{note}
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Support for FP8 and quantized data types (INT8 or INT4) is not implemented for all the models. Refer to {ref}`precision` and [examples](https://github.com/NVIDIA/TensorRT-LLM/tree/main/examples) folder for additional information.
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```
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