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SPIFFS (SPI Flash File System)
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V1.0
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V0.1
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Copyright (c) 2013 Peter Andersson
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For legal stuff, see LICENCE in this directory.
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For legal stuff, see LICENCE in this directory. Basically, you may do whatever
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you want with the source. Use, modify, sell, print it out and smoke it - as
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long as I won't be held responsible.
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Love to hear feedback though!
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* INTRODUCTION
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@@ -11,14 +15,29 @@ For legal stuff, see LICENCE in this directory.
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Spiffs is a file system intended for SPI flash devices on embedded targets.
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Spiffs is designed with following characteristics in mind:
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- Small (embedded) target, sparse RAM
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- Small (embedded) targets, sparse RAM
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- Only big areas of data (blocks) can be erased
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- An erase will reset all bits in block to ones
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- Writing pulls one to zeroes
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- Zeroes can only be pulled to ones by erase
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- Wear leveling
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Spiffs is inspired by YAFFS structurally, but is a clean write from scratch.
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** Features
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What spiffs does:
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- Spiffs presents a posix-like api: open, close, read, write, seek, stat, etc
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- Multiple spiffs configurations can be run on same target - and even on same
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SPI flash device
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- It has built in file system consistency checks
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What spiffs does not:
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- Presently, spiffs does not support directories. It produces a flat
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structure. Creating a file with path "tmp/myfile.txt" will create a file
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called "tmp/myfile.txt" instead of a myfile.txt under directory "tmp".
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- It is not a realtime stack. One write operation might take much longer than
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another.
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- Poor scalability. Spiffs is intended for small memory devices - the normal
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sizes for SPI flashes.
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* INTEGRATING SPIFFS
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@@ -29,19 +48,19 @@ In order to integrate spiffs to your embedded target, you will basically need:
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- Memory (flash or ram) for the code
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- Memory (ram) for the stack
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Threaded systems might need mutexes and so on.
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Other stuff may be needed, threaded systems might need mutexes and so on.
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** Logical structure
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One must decide how to divide up the SPI flash for spiffs. Having the datasheet
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for the actual SPI flash in hand will help. Spiffs can be defined to use all or
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only parts of the SPI flash.
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First and foremost, one must decide how to divide up the SPI flash for spiffs.
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Having the datasheet for the actual SPI flash in hand will help. Spiffs can be
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defined to use all or only parts of the SPI flash.
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If this seems arcane, read the "DESIGN" chapter first.
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If following seems arcane, read the "DESIGN" chapter first.
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- Decide the logical size of blocks. This must be a multiple of the physical
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SPI flash block size. To go safe, use the physical block size - which in
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almost all cases are 65536 bytes.
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- Decide the logical size of blocks. This must be a multiple of the biggest
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physical SPI flash block size. To go safe, use the physical block size -
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which in many cases is 65536 bytes.
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- Decide the logical size of pages. This must be a 2nd logarithm part of the
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logical block size. To go safe, use 256 bytes to start with.
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- Decide how much of the SPI flash memory to be used for spiffs. This must be
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@@ -87,15 +106,15 @@ s32_t SPIFFS_mount(
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- fs Points to a spiffs struct. This may be totally uninitialized.
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- config Points to a spiffs_config struct. This struct must be
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initialized when mounting. See below.
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- work A RAM memory buffer being double the size of the logical page
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- work A ram memory buffer being double the size of the logical page
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size. This buffer is used excessively by the spiffs stack. If
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logical page size is 256, this buffer must be 512 bytes.
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- fd_space A RAM memory buffer used for file descriptors.
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- fd_space A ram memory buffer used for file descriptors.
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- fd_space_size The size of the file descriptor buffer. A file descriptor
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normally is around 32 bytes depending on the build config -
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the bigger the buffer, the more file descriptors are
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available.
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- cache A RAM memory buffer used for cache. Ignored if cache is
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- cache A ram memory buffer used for cache. Ignored if cache is
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disabled in build config.
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- cache_size The size of the cache buffer. Ignored if cache is disabled in
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build config. One cache page will be slightly larger than the
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@@ -265,10 +284,13 @@ TODO
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Below is a small description of how SPI flashes work internally.
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SPI flash devices are physically divided in blocks. On some SPI flash devices,
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blocks are further divided into sectors. Common memory capacaties for SPI
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flashes are 1,2,4 or 8 megabyte of data, with blocks of 64K. Sectors normally
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are 4K, if supported. The entire memory is linear and can be written in random
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access, but erasing can only be done block- or sectorwise; or by mass erase.
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blocks are further divided into sectors. Datasheets sometimes name blocks as
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sectors and vice versa.
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Common memory capacaties for SPI flashes are 512kB up to 8 MB of data, with
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blocks of 64K. Sectors normally are 4K, if supported. The entire memory is
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linear and can be written in random access, but erasing can only be done block-
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or sectorwise; or by mass erase.
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SPI flashes can normally be erased from 100.000 up to 1.000.000 cycles before
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they fail erasing.
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@@ -280,3 +302,4 @@ pulls ones to zeroes. Writing 0xFF to an address is simply a no-op. This way
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of "nand-writing" is used considerably in spiffs.
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** TODO
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