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[da15000] update of Dialog SDK to 1_0_10 version (#2365)

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- New cli_programmer tool
- Use RSSI calculation mechanism from SDK
- Change number of EID-to-RLOC cache entries to 20
- Remove unnecessary files
This commit is contained in:
JakubBrachTieto
2017-11-22 23:30:43 +00:00
committed by Jonathan Hui
parent e1ce2fb35d
commit 448079d16b
69 changed files with 13430 additions and 24738 deletions
Download Patch File Download Diff File Expand all files Collapse all files
examples/platforms/da15000/Makefile.am
+20 -25
View File
@@ -36,21 +36,17 @@ libopenthread_da15000_a_CPPFLAGS
-I$(top_srcdir)/examples/platforms/da15000 \
-I$(top_srcdir)/examples/platforms/da15000/crypto \
-I$(top_srcdir)/src/core \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/peripherals/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/adapters/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/memory/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/interfaces/ftdf/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/config \
-I$(top_srcdir)/third_party/dialog/DialogSDK \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/memory/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/osal \
-I$(top_srcdir)/third_party/dialog/DialogSDK/bsp/peripherals/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/interfaces/ftdf/include \
-I$(top_srcdir)/third_party/dialog/DialogSDK/interfaces/ftdf/src \
-I$(top_srcdir)/third_party/mbedtls/repo.patched/include \
-include$(top_srcdir)/examples/platforms/da15000/custom_config_qspi.h \
-Wno-unknown-pragmas \
-Wno-sign-compare \
-Wno-unused-function \
-Wno-unused-parameter \
-Wno-shadow \
-Wno-type-limits \
-Wno-unused-variable \
-Wno-missing-field-initializers \
@@ -62,42 +58,41 @@ PLATFORM_SOURCES
alarm.c \
flash.c \
logging.c \
misc.c \
platform.c \
radio.c \
random.c \
uart.c \
misc.c \
crypto/aes_alt.c \
$(NULL)
DIALOG_SOURCES = \
@top_builddir@/third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/startup/config.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/startup/startup_ARMCM0.S \
@top_builddir@/third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c \
@top_builddir@/third_party/dialog/DialogSDK/bsp/startup/vector_table.S \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c \
@top_builddir@/third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c \
$(NULL)
libopenthread_da15000_a_SOURCES = \
examples/platforms/da15000/README.md
+2 -2
View File
@@ -7,7 +7,7 @@ This directory contains example platform drivers for the [Dialog Semiconductor D
**NOTE:** Each Thread node requires a unique EUI-64.
Please make sure all Thread nodes in your network have a unique EUI-64 by setting HARDCODED_NODE_ID in radio.c to a unique value.
**NOTE:** Current version works only with DA15000 rev. BA
**NOTE:** Current version works only with DA15000
## Toolchain
@@ -130,7 +130,7 @@ Board will indicate state of device according to LED blink speed.
## Remarks
* Validation
The DA15000 example has been validated by Dialog Semiconductor with commit d250105 included.
The DA15000 example has been validated by Dialog Semiconductor with commit 1f6528e included.
* Build environment
examples/platforms/da15000/alarm.c
+2 -16
View File
@@ -31,17 +31,12 @@
* Platform abstraction for the alarm
*/
#include <openthread/config.h>
#include <stdbool.h>
#include <stdint.h>
#include <openthread/platform/alarm-milli.h>
#include "hw_timer0.h"
#include "hw_gpio.h"
#include "platform-da15000.h"
#include "hw_timer0.h"
static bool sIsRunning = false;
static uint32_t sAlarm = 0;
static uint32_t sCounter;
@@ -88,12 +83,6 @@ void otPlatAlarmMilliStartAt(otInstance *aInstance, uint32_t t0, uint32_t dt)
hw_timer0_enable();
}
if (sIsRunning == false)
{
sIsRunning = true;
}
hw_timer0_unfreeze();
}
@@ -103,6 +92,3 @@ void otPlatAlarmMilliStop(otInstance *aInstance)
sIsRunning = false;
hw_timer0_freeze();
}
examples/platforms/da15000/custom_config_qspi.h
+23 -20
View File
@@ -28,7 +28,7 @@
/**
* @file custom_config_qspi.h
* Custom configuration file for FreeRTOS applications executing from QSPI.
* Board Support Package. User Configuration file for cached QSPI mode.
*/
#ifndef CUSTOM_CONFIG_QSPI_H_
@@ -37,7 +37,7 @@
#include "bsp_definitions.h"
#define dg_configBLACK_ORCA_IC_REV BLACK_ORCA_IC_REV_B
#define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_A
#define dg_configBLACK_ORCA_IC_STEP BLACK_ORCA_IC_STEP_B
#undef CONFIG_USE_BLE
#define CONFIG_USE_FTDF
@@ -45,9 +45,6 @@
#define __HEAP_SIZE 0x0600
#define __STACK_SIZE 0x0100
#define CONFIG_RETARGET
#define CONFIG_RETARGET_UART HW_UART1
#define dg_configUSE_LP_CLK LP_CLK_32768
#define dg_configEXEC_MODE MODE_IS_CACHED
#define dg_configCODE_LOCATION NON_VOLATILE_IS_FLASH
@@ -58,9 +55,6 @@
#define dg_configUSER_CAN_USE_TIMER1 (0)
#define dg_configMEM_RETENTION_MODE (0x1F)
#define dg_configSHUFFLING_MODE (0x3)
#define dg_configUSE_WDOG (0)
#define dg_configFLASH_CONNECTED_TO (FLASH_CONNECTED_TO_1V8)
@@ -82,36 +76,45 @@
#define dg_configUSE_SW_CURSOR (1)
#define dg_configFEM_DLG_REF_BOARD (1)
#define dg_configPOWER_1V8P (1)
#define dg_configDISABLE_BACKGROUND_FLASH_OPS (1)
#define dg_configUSE_HW_TRNG (1)
/*************************************************************************************************\
* Memory layout specific config
*/
#define dg_configQSPI_CODE_SIZE (512 * 1024)
#define dg_configUSE_HW_TIMER0 (1)
/*************************************************************************************************\
* FTDF specific config
*/
#define FTDF_NO_CSL /* Define this to disable CSL mode */
#define FTDF_NO_TSCH /* Define this to disable TSCH mode */
#define FTDF_LITE /* Define this to enable LITE mode (only transparent mode enabled) */
#define FTDF_PHY_API /* Define this to enable PHY API mode (no FTDF adapter;
implies FTDF_LITE) */
#define FTDF_PASS_ACK_FRAME /* Define this to pass ACK frame */
#define dg_configUSE_HW_AES_HASH (1)
/*************************************************************************************************\
* OS specific config
*/
#define OS_BAREMETAL
#define CPU_DA15000 (1)
/*************************************************************************************************\
* Peripheral specific config
*/
#define FTDF_PHY_API
#define dg_configUSE_HW_RF (1)
#define dg_configRF_ENABLE_RECALIBRATION (0)
#define FTDF_NO_CSL
#define FTDF_NO_TSCH
#define FTDF_LITE
#define dg_configUSE_HW_AES_HASH (1)
#define dg_configUSE_HW_TIMER0 (1)
#define dg_configUSE_HW_TRNG (1)
#define dg_configFLASH_ADAPTER (0)
#define dg_configRF_ADAPTER (0)
#define dg_configUART_SOFTWARE_FIFO (1)
#define dg_configUART2_SOFTWARE_FIFO_SIZE (256)
#define dg_configNVMS_ADAPTER (0)
#define dg_configNVMS_VES (0)
#define dg_configUSE_WDOG (0)
/* Include bsp default values */
#include "bsp_defaults.h"
examples/platforms/da15000/flash.c
+1 -3
View File
@@ -26,8 +26,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <openthread/config.h>
#include <openthread/platform/alarm-milli.h>
#include "platform-da15000.h"
#include "qspi_automode.h"
@@ -144,4 +143,3 @@ uint32_t utilsFlashRead(uint32_t aAddress, uint8_t *aData, uint32_t aSize)
{
return qspi_automode_read(aAddress, aData, aSize);;
}
examples/platforms/da15000/logging.c
+2 -4
View File
@@ -31,11 +31,10 @@
* Platform abstraction for the logging
*
*/
#include <openthread/config.h>
#include <openthread-core-config.h>
#include <openthread/platform/logging.h>
#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED)
#if (OPENTHREAD_CONFIG_LOG_OUTPUT == OPENTHREAD_CONFIG_LOG_OUTPUT_PLATFORM_DEFINED)
void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat, ...)
{
(void)aLogLevel;
@@ -43,4 +42,3 @@ void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat
(void)aFormat;
}
#endif
examples/platforms/da15000/misc.c
+2 -3
View File
@@ -26,11 +26,10 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <openthread/config.h>
#include <openthread/openthread.h>
#include <openthread/platform/misc.h>
#include "platform-da15000.h"
#include "hw_cpm.h"
#include "sdk_defs.h"
examples/platforms/da15000/openthread-core-da15000-config.h
+9 -1
View File
@@ -47,7 +47,7 @@
*
* The base address of the pages to be used for non-volatile-settings storage.
*/
#define SETTINGS_CONFIG_BASE_ADDRESS 0x7B000
#define SETTINGS_CONFIG_BASE_ADDRESS 0x7B000
/**
* @def SETTINGS_CONFIG_PAGE_SIZE
@@ -81,6 +81,14 @@
*/
#define OPENTHREAD_CONFIG_ENABLE_SOFTWARE_ENERGY_SCAN 1
/**
* @def OPENTHREAD_CONFIG_ADDRESS_CACHE_ENTRIES
*
* The number of EID-to-RLOC cache entries.
*
*/
#define OPENTHREAD_CONFIG_ADDRESS_CACHE_ENTRIES 20
/**
* @def OPENTHREAD_CONFIG_LOG_OUTPUT
*
examples/platforms/da15000/platform.c
+3 -14
View File
@@ -31,23 +31,18 @@
* This file includes the platform-specific initializers.
*/
#include <openthread/config.h>
#include <openthread/commissioner.h>
#include <openthread/joiner.h>
#include <openthread/openthread.h>
#include <openthread/platform/alarm-milli.h>
#include <openthread/platform/uart.h>
#include "platform-da15000.h"
#include "sdk_defs.h"
#include "ftdf.h"
#include "hw_cpm.h"
#include "hw_gpio.h"
#include "hw_qspi.h"
#include "hw_otpc.h"
#include "hw_watchdog.h"
#include "sdk_defs.h"
static bool sBlink = false;
static int sMsCounterInit;
@@ -67,7 +62,7 @@ static otInstance *sInstance = NULL;
* Router - 2Hz
* Child - 0.5Hz
*/
void ExampleProcess(otInstance *aInstance)
static void ExampleProcess(otInstance *aInstance)
{
static int aliveLEDcounter = 0;
otDeviceRole devRole;
@@ -136,8 +131,6 @@ void PlatformInit(int argc, char *argv[])
da15000AlarmInit();
// Initialize Radio
da15000RadioInit();
// enable interrupts
portENABLE_INTERRUPTS();
(void)argc;
(void)argv;
@@ -214,9 +207,7 @@ static void ClkSet(sys_clk_t clock)
case sysclk_PLL48:
if (hw_cpm_is_pll_locked() == 0)
{
hw_watchdog_unfreeze(); // Start watchdog
hw_cpm_pll_sys_on(); // Turn on PLL
hw_watchdog_freeze(); // Stop watchdog
}
hw_cpm_enable_pll_divider(); // Enable divider (div by 2)
@@ -229,9 +220,7 @@ static void ClkSet(sys_clk_t clock)
case sysclk_PLL96:
if (hw_cpm_is_pll_locked() == 0)
{
hw_watchdog_unfreeze(); // Start watchdog
hw_cpm_pll_sys_on(); // Turn on PLL
hw_watchdog_freeze(); // Stop watchdog
}
hw_cpm_disable_pll_divider(); // Disable divider (div by 1)
@@ -254,7 +243,7 @@ static void ClkChange(sys_clk_t lastClock, sys_clk_t newClock)
}
}
void StateChangedCallback(uint32_t aFlags, void *aContext)
static void StateChangedCallback(uint32_t aFlags, void *aContext)
{
if ((aFlags & OT_CHANGED_COMMISSIONER_STATE) != 0)
{
examples/platforms/da15000/radio.c
+111 -191
View File
@@ -31,8 +31,6 @@
* Platform abstraction for radio communication.
*/
#include <openthread/config.h>
#include <openthread/openthread.h>
#include <openthread/platform/alarm-milli.h>
#include <openthread/platform/radio.h>
@@ -47,27 +45,20 @@
#include "hw_otpc.h"
#include "hw_rf.h"
#include "internal.h"
#include "regmap.h"
#define FACTORY_TEST_TIMESTAMP (0x7F8EA08) // Register holds a timestamp of facotry test of a chip
#define FACTORY_TESTER_ID (0x7F8EA0C) // Register holds test machine ID used for factory test
#define DEFAULT_CHANNEL (11)
#define PRIVILEGED_DATA __attribute__((section("privileged_data_zi")))
#define RSSI_TABLE_SIZE 8
#define EUI64_TABLE_SIZE 8
#define RADIO_FRAMES_BUFFER_SIZE 8
#define RADIO_DEFAULT_CHANNEL (11)
#define RADIO_EUI64_TABLE_SIZE (8)
#define RADIO_FRAMES_BUFFER_SIZE (32)
enum
{
DA15000_RECEIVE_SENSITIVITY = -100, // dBm
};
static void da15000OtpRead(void);
static uint8_t eui64[EUI64_TABLE_SIZE] = {0};
static ftdf_dbm sRssiReal = -100; // Initialize with the worst power
static otInstance *sThreadInstance;
static otRadioState sRadioState = OT_RADIO_STATE_DISABLED;
static otRadioFrame sReceiveFrame[RADIO_FRAMES_BUFFER_SIZE];
@@ -75,22 +66,19 @@ static otRadioFrame *sReceiveFrameAck;
static otRadioFrame sTransmitFrame;
static otError sTransmitStatus;
static bool sAckFrame = false;
static bool sRadioPromiscuous = false;
static bool sRssiInit = true;
static bool sTransmitDoneFrame = false;
static bool sDropFrame = false;
static uint8_t sChannel = DEFAULT_CHANNEL;
static uint8_t sRssiCtr = 0;
static bool sRadioPromiscuous = false;
static bool sTransmitDoneFrame = false;
static uint8_t sChannel = RADIO_DEFAULT_CHANNEL;
static uint8_t sEnableRX = 0;
static uint8_t sReadFrame = 0;
static uint8_t sWriteFrame = 0;
static uint32_t sSleepInitDelay = 0;
static uint8_t sEui64[RADIO_EUI64_TABLE_SIZE];
static uint8_t sReceivePsdu[RADIO_FRAMES_BUFFER_SIZE][OT_RADIO_FRAME_MAX_SIZE];
static uint8_t sRssiTable[RSSI_TABLE_SIZE];
static uint8_t sTransmitPsdu[OT_RADIO_FRAME_MAX_SIZE];
PRIVILEGED_DATA static uint8_t sEnableRX;
static void da15000OtpRead(void)
{
hw_otpc_init(); // Start clock.
@@ -103,14 +91,14 @@ static void da15000OtpRead(void)
uint32_t *factoryTestId = (uint32_t *) FACTORY_TESTER_ID;
__DMB();
eui64[0] = 0x80; //80-EA-CA is for Dialog Semiconductor
eui64[1] = 0xEA;
eui64[2] = 0xCA;
eui64[3] = (*factoryTestId >> 8) & 0xff;
eui64[4] = (*factoryTestTimeStamp >> 24) & 0xff;
eui64[5] = (*factoryTestTimeStamp >> 16) & 0xff;
eui64[6] = (*factoryTestTimeStamp >> 8) & 0xff;
eui64[7] = *factoryTestTimeStamp & 0xff;
sEui64[0] = 0x80; //80-EA-CA is for Dialog Semiconductor
sEui64[1] = 0xEA;
sEui64[2] = 0xCA;
sEui64[3] = (*factoryTestId >> 8) & 0xff;
sEui64[4] = (*factoryTestTimeStamp >> 24) & 0xff;
sEui64[5] = (*factoryTestTimeStamp >> 16) & 0xff;
sEui64[6] = (*factoryTestTimeStamp >> 8) & 0xff;
sEui64[7] = *factoryTestTimeStamp & 0xff;
hw_otpc_manual_read_off();
hw_otpc_disable();
@@ -119,6 +107,7 @@ static void da15000OtpRead(void)
void da15000RadioInit(void)
{
uint16_t ptr;
/* Wake up power domains */
REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP);
@@ -138,7 +127,7 @@ void da15000RadioInit(void)
da15000OtpRead();
sChannel = DEFAULT_CHANNEL;
sChannel = RADIO_DEFAULT_CHANNEL;
sTransmitFrame.mPsdu = sTransmitPsdu;
for (ptr = 0; ptr != RADIO_FRAMES_BUFFER_SIZE; ptr++)
@@ -152,61 +141,59 @@ void da15000RadioInit(void)
void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64)
{
(void)aInstance;
memcpy(aIeeeEui64, eui64, EUI64_TABLE_SIZE);
memcpy(aIeeeEui64, sEui64, RADIO_EUI64_TABLE_SIZE);
}
void otPlatRadioSetPanId(otInstance *aInstance, uint16_t aPanid)
{
(void)aInstance;
otLogInfoPlat(aInstance, "Set PanId: %X", aPanid);
otLogInfoPlat(sInstance, "Set PanId: %X", aPanid);
FTDF_setValue(FTDF_PIB_PAN_ID, &aPanid);
ftdf_set_value(FTDF_PIB_PAN_ID, &aPanid);
}
void otPlatRadioSetExtendedAddress(otInstance *aInstance, const otExtAddress *aAddress)
{
(void)aInstance;
otLogInfoPlat(sInstance, "Set Extended Address: %X%X%X%X%X%X%X%X",
otLogInfoPlat(aInstance, "Set Extended Address: %X%X%X%X%X%X%X%X",
aAddress->m8[7], aAddress->m8[6], aAddress->m8[5], aAddress->m8[4],
aAddress->m8[3], aAddress->m8[2], aAddress->m8[1], aAddress->m8[0]);
FTDF_setValue(FTDF_PIB_EXTENDED_ADDRESS, aAddress->m8);
ftdf_set_value(FTDF_PIB_EXTENDED_ADDRESS, aAddress->m8);
}
void otPlatRadioSetShortAddress(otInstance *aInstance, uint16_t aAddress)
{
(void)aInstance;
otLogInfoPlat(aInstance, "Set Short Address: %X", aAddress);
otLogInfoPlat(sInstance, "Set Short Address: %X", aAddress);
FTDF_setValue(FTDF_PIB_SHORT_ADDRESS, &aAddress);
ftdf_set_value(FTDF_PIB_SHORT_ADDRESS, &aAddress);
}
otError otPlatRadioEnable(otInstance *aInstance)
{
ftdf_bitmap32_t options;
otError error = OT_ERROR_NONE;
uint8_t modeCCA;
otError error = OT_ERROR_NONE;
otEXPECT_ACTION(sRadioState == OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE);
sThreadInstance = aInstance;
sEnableRX = 1;
FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
FTDF_setValue(FTDF_PIB_CURRENT_CHANNEL, &sChannel);
modeCCA = FTDF_CCA_MODE_2;
FTDF_setValue(FTDF_PIB_CCA_MODE, &modeCCA);
ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
FTDF_Bitmap32 options = FTDF_TRANSPARENT_ENABLE_FCS_GENERATION;
ftdf_set_value(FTDF_PIB_CURRENT_CHANNEL, &sChannel);
modeCCA = FTDF_CCA_MODE_2;
ftdf_set_value(FTDF_PIB_CCA_MODE, &modeCCA);
options = FTDF_TRANSPARENT_ENABLE_FCS_GENERATION;
options |= FTDF_TRANSPARENT_WAIT_FOR_ACK;
options |= FTDF_TRANSPARENT_AUTO_ACK;
FTDF_enableTransparentMode(FTDF_TRUE, options);
ftdf_enable_transparent_mode(FTDF_TRUE, options);
otPlatRadioSetPromiscuous(aInstance, false);
otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_SLEEP", NULL);
otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_SLEEP", NULL);
sRadioState = OT_RADIO_STATE_SLEEP;
exit:
@@ -215,14 +202,13 @@ exit:
otError otPlatRadioDisable(otInstance *aInstance)
{
(void)aInstance;
sEnableRX = 0;
FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
ad_ftdf_sleep_when_possible(FTDF_TRUE);
FTDF_fpprReset();
ftdf_fppr_reset();
otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_DISABLED", NULL);
otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_DISABLED", NULL);
sRadioState = OT_RADIO_STATE_DISABLED;
return OT_ERROR_NONE;
@@ -237,7 +223,7 @@ bool otPlatRadioIsEnabled(otInstance *aInstance)
otError otPlatRadioSleep(otInstance *aInstance)
{
(void)aInstance;
otError error = OT_ERROR_NONE;
if (sRadioState == OT_RADIO_STATE_RECEIVE && sSleepInitDelay == 0)
{
@@ -249,14 +235,13 @@ otError otPlatRadioSleep(otInstance *aInstance)
return OT_ERROR_NONE;
}
otError error = OT_ERROR_NONE;
otEXPECT_ACTION(sRadioState == OT_RADIO_STATE_RECEIVE, error = OT_ERROR_INVALID_STATE);
otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_SLEEP", NULL);
otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_SLEEP", NULL);
sRadioState = OT_RADIO_STATE_SLEEP;
sEnableRX = 0;
FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
ad_ftdf_sleep_when_possible(FTDF_TRUE);
exit:
@@ -265,7 +250,6 @@ exit:
otError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel)
{
(void)aInstance;
otError error = OT_ERROR_NONE;
otEXPECT_ACTION(sRadioState != OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE);
@@ -273,15 +257,15 @@ otError otPlatRadioReceive(otInstance *aInstance, uint8_t aChannel)
ad_ftdf_wake_up();
sEnableRX = 0;
FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
sChannel = aChannel;
FTDF_setValue(FTDF_PIB_CURRENT_CHANNEL, &aChannel);
ftdf_set_value(FTDF_PIB_CURRENT_CHANNEL, &aChannel);
sEnableRX = 1;
FTDF_setValue(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
ftdf_set_value(FTDF_PIB_RX_ON_WHEN_IDLE, &sEnableRX);
otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL);
otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL);
sRadioState = OT_RADIO_STATE_RECEIVE;
exit:
@@ -296,21 +280,19 @@ void otPlatRadioEnableSrcMatch(otInstance *aInstance, bool aEnable)
otError otPlatRadioAddSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
(void)aInstance;
otError error = OT_ERROR_NONE;
uint8_t entry;
uint8_t entryIdx;
// check if address already stored
otEXPECT(!ftdf_fppr_lookup_short_address(aShortAddress, &entry, &entryIdx));
otEXPECT(!FTDF_fpprLookupShortAddress(aShortAddress, &entry, &entryIdx));
otEXPECT_ACTION(ftdf_fppr_get_free_short_address(&entry, &entryIdx), error = OT_ERROR_NO_BUFS);
otEXPECT_ACTION(FTDF_fpprGetFreeShortAddress(&entry, &entryIdx), error = OT_ERROR_NO_BUFS);
otLogDebgPlat(aInstance, "Add ShortAddress entry: %d", entry);
otLogDebgPlat(sInstance, "Add ShortAddress entry: %d", entry);
FTDF_fpprSetShortAddress(entry, entryIdx, aShortAddress);
FTDF_fpprSetShortAddressValid(entry, entryIdx, FTDF_TRUE);
ftdf_fppr_set_short_address(entry, entryIdx, aShortAddress);
ftdf_fppr_set_short_address_valid(entry, entryIdx, FTDF_TRUE);
exit:
return error;
@@ -319,10 +301,9 @@ exit:
otError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress)
{
(void)aInstance;
otError error = OT_ERROR_NONE;
uint8_t entry;
FTDF_ExtAddress addr;
ftdf_ext_address_t addr;
uint32_t addrL;
uint64_t addrH;
@@ -333,15 +314,14 @@ otError otPlatRadioAddSrcMatchExtEntry(otInstance *aInstance, const otExtAddress
addr = addrL | (addrH << 32);
// check if address already stored
otError error = OT_ERROR_NONE;
otEXPECT(!FTDF_fpprLookupExtAddress(addr, &entry));
otEXPECT(!ftdf_fppr_lookup_ext_address(addr, &entry));
otEXPECT_ACTION(FTDF_fpprGetFreeExtAddress(&entry), error = OT_ERROR_NO_BUFS);
otEXPECT_ACTION(ftdf_fppr_get_free_ext_address(&entry), error = OT_ERROR_NO_BUFS);
otLogDebgPlat(sInstance, "Add ExtAddress entry: %d", entry);
otLogDebgPlat(aInstance, "Add ExtAddress entry: %d", entry);
FTDF_fpprSetExtAddress(entry, addr);
FTDF_fpprSetExtAddressValid(entry, FTDF_TRUE);
ftdf_fppr_set_ext_address(entry, addr);
ftdf_fppr_set_ext_address_valid(entry, FTDF_TRUE);
exit:
return error;
@@ -349,17 +329,16 @@ exit:
otError otPlatRadioClearSrcMatchShortEntry(otInstance *aInstance, const uint16_t aShortAddress)
{
(void)aInstance;
otError error = OT_ERROR_NONE;
uint8_t entry;
uint8_t entryIdx;
otEXPECT_ACTION(FTDF_fpprLookupShortAddress(aShortAddress, &entry, &entryIdx), error = OT_ERROR_NO_ADDRESS);
otEXPECT_ACTION(ftdf_fppr_lookup_short_address(aShortAddress, &entry, &entryIdx), error = OT_ERROR_NO_ADDRESS);
otLogDebgPlat(sInstance, "Clear ShortAddress entry: %d", entry);
otLogDebgPlat(aInstance, "Clear ShortAddress entry: %d", entry);
FTDF_fpprSetShortAddress(entry, entryIdx, 0);
FTDF_fpprSetShortAddressValid(entry, entryIdx, FTDF_FALSE);
ftdf_fppr_set_short_address(entry, entryIdx, 0);
ftdf_fppr_set_short_address_valid(entry, entryIdx, FTDF_FALSE);
exit:
return error;
@@ -367,10 +346,9 @@ exit:
otError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const otExtAddress *aExtAddress)
{
(void)aInstance;
otError error = OT_ERROR_NONE;
uint8_t entry;
FTDF_ExtAddress addr;
ftdf_ext_address_t addr;
uint32_t addrL;
uint64_t addrH;
@@ -380,13 +358,12 @@ otError otPlatRadioClearSrcMatchExtEntry(otInstance *aInstance, const otExtAddre
(aExtAddress->m8[5] << 8) | (aExtAddress->m8[4] << 0);
addr = addrL | (addrH << 32);
otError error = OT_ERROR_NONE;
otEXPECT_ACTION(FTDF_fpprLookupExtAddress(addr, &entry), error = OT_ERROR_NO_ADDRESS);
otEXPECT_ACTION(ftdf_fppr_lookup_ext_address(addr, &entry), error = OT_ERROR_NO_ADDRESS);
otLogDebgPlat(sInstance, "Clear ExtAddress entry: %d", entry);
otLogDebgPlat(aInstance, "Clear ExtAddress entry: %d", entry);
FTDF_fpprSetExtAddress(entry, 0);
FTDF_fpprSetExtAddressValid(entry, FTDF_FALSE);
ftdf_fppr_set_ext_address(entry, 0);
ftdf_fppr_set_ext_address_valid(entry, FTDF_FALSE);
exit:
return error;
@@ -394,19 +371,17 @@ exit:
void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance)
{
(void)aInstance;
uint8_t i, j;
otLogDebgPlat(sInstance, "Clear ShortAddress entries", NULL);
otLogDebgPlat(aInstance, "Clear ShortAddress entries", NULL);
for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++)
{
for (j = 0; j < 4; j++)
{
if (FTDF_fpprGetShortAddressValid(i, j))
if (ftdf_fppr_get_short_address_valid(i, j))
{
FTDF_fpprSetShortAddressValid(i, j, FTDF_FALSE);
ftdf_fppr_set_short_address_valid(i, j, FTDF_FALSE);
}
}
}
@@ -414,17 +389,15 @@ void otPlatRadioClearSrcMatchShortEntries(otInstance *aInstance)
void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance)
{
(void)aInstance;
uint8_t i;
otLogDebgPlat(sInstance, "Clear ExtAddress entries", NULL);
otLogDebgPlat(aInstance, "Clear ExtAddress entries", NULL);
for (i = 0; i < FTDF_FPPR_TABLE_ENTRIES; i++)
{
if (FTDF_fpprGetExtAddressValid(i))
if (ftdf_fppr_get_ext_address_valid(i))
{
FTDF_fpprSetExtAddressValid(i, FTDF_FALSE);
ftdf_fppr_set_ext_address_valid(i, FTDF_FALSE);
}
}
}
@@ -438,19 +411,15 @@ otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance)
otError otPlatRadioTransmit(otInstance *aInstance, otRadioFrame *aFrame)
{
(void)aInstance;
uint8_t csmaSuppress;
otError error = OT_ERROR_NONE;
otEXPECT_ACTION(sRadioState != OT_RADIO_STATE_DISABLED, error = OT_ERROR_INVALID_STATE);
otLogDebgPlat(sInstance, "Radio start transmit: %d bytes on channel: %d", aFrame->mLength, aFrame->mChannel);
otLogDebgPlat(aInstance, "Radio start transmit: %d bytes on channel: %d", aFrame->mLength, aFrame->mChannel);
csmaSuppress = 0;
ad_ftdf_send_frame_simple(aFrame->mLength, aFrame->mPsdu, aFrame->mChannel, 0, csmaSuppress); //Prio 0 for all.
ad_ftdf_send_frame_simple(aFrame->mLength, aFrame->mPsdu, aFrame->mChannel, 0, FTDF_TRUE);
otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_TRANSMIT", NULL);
otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_TRANSMIT", NULL);
sRadioState = OT_RADIO_STATE_TRANSMIT;
otPlatRadioTxStarted(aInstance, aFrame);
@@ -462,47 +431,15 @@ exit:
int8_t otPlatRadioGetRssi(otInstance *aInstance)
{
(void)aInstance;
uint16_t result = 0;
// fill table with same value for init
if (sRssiInit)
{
for (uint8_t i = 0; i < RSSI_TABLE_SIZE; i++)
{
sRssiTable[i] = sReceiveFrame[sWriteFrame].mLqi;
}
sRssiInit = false;
}
else
{
ASSERT_ERROR(sRssiCtr < RSSI_TABLE_SIZE);
sRssiTable[sRssiCtr] = sReceiveFrame[sWriteFrame].mLqi;
sRssiCtr++;
if (sRssiCtr >= RSSI_TABLE_SIZE)
{
sRssiCtr = 0;
}
}
// average of 8 last lqi
for (uint8_t i = 0; i < RSSI_TABLE_SIZE; i++)
{
result += sRssiTable[i];
}
result = result / RSSI_TABLE_SIZE;
// Approximation to dB scale by divide by 9
return result / 9;
return sRssiReal;
}
otRadioCaps otPlatRadioGetCaps(otInstance *aInstance)
{
(void)aInstance;
return OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_TRANSMIT_RETRIES;
return OT_RADIO_CAPS_ACK_TIMEOUT | OT_RADIO_CAPS_TRANSMIT_RETRIES | OT_RADIO_CAPS_CSMA_BACKOFF;
}
bool otPlatRadioGetPromiscuous(otInstance *aInstance)
@@ -514,11 +451,9 @@ bool otPlatRadioGetPromiscuous(otInstance *aInstance)
void otPlatRadioSetPromiscuous(otInstance *aInstance, bool aEnable)
{
(void)aInstance;
otLogInfoPlat(aInstance, "Set Promiscuous: %d", aEnable ? 1 : 0);
otLogInfoPlat(sInstance, "Set Promiscuous: %d", aEnable ? 1 : 0);
FTDF_setValue(FTDF_PIB_PROMISCUOUS_MODE, &aEnable);
ftdf_set_value(FTDF_PIB_PROMISCUOUS_MODE, &aEnable);
sRadioPromiscuous = aEnable;
}
@@ -533,26 +468,22 @@ otError otPlatRadioEnergyScan(otInstance *aInstance, uint8_t aScanChannel, uint1
void otPlatRadioSetDefaultTxPower(otInstance *aInstance, int8_t aPower)
{
(void)aInstance;
otLogInfoPlat(aInstance, "Set DefaultTxPower: %d", aPower);
otLogInfoPlat(sInstance, "Set DefaultTxPower: %d", aPower);
FTDF_setValue(FTDF_PIB_TX_POWER, &aPower);
ftdf_set_value(FTDF_PIB_TX_POWER, &aPower);
}
void da15000RadioProcess(otInstance *aInstance)
{
(void)aInstance;
FTDF_FrameHeader frameHeader;
ftdf_frame_header_t frameHeader;
if (sReadFrame != sWriteFrame)
{
FTDF_getFrameHeader(sReceiveFrame[sReadFrame].mPsdu, &frameHeader);
ftdf_get_frame_header(sReceiveFrame[sReadFrame].mPsdu, &frameHeader);
otLogDebgPlat(sInstance, "Radio received: %d bytes", sReceiveFrame[sReadFrame].mLength);
otLogDebgPlat(aInstance, "Radio received: %d bytes", sReceiveFrame[sReadFrame].mLength);
if (frameHeader.frameType == FTDF_ACKNOWLEDGEMENT_FRAME)
if (frameHeader.frame_type == FTDF_ACKNOWLEDGEMENT_FRAME)
{
sReceiveFrameAck = &sReceiveFrame[sReadFrame];
sAckFrame = true;
@@ -566,26 +497,9 @@ void da15000RadioProcess(otInstance *aInstance)
if (sTransmitDoneFrame)
{
switch (sTransmitStatus)
{
case OT_ERROR_NONE:
otLogDebgPlat(sInstance, "Radio transmit SUCCESSFUL", NULL);
break;
otLogDebgPlat(aInstance, "Radio transmit status: %s", otThreadErrorToString(sTransmitStatus));
case OT_ERROR_CHANNEL_ACCESS_FAILURE:
otLogDebgPlat(sInstance, "Radio transmit CHANNEL_ACCESS_FAILURE", NULL);
break;
case OT_ERROR_NO_ACK:
otLogDebgPlat(sInstance, "Radio transmit NO_ACK", NULL);
break;
default:
otLogDebgPlat(sInstance, "Radio transmit ABORT", NULL);
break;
}
FTDF_getFrameHeader(sTransmitFrame.mPsdu, &frameHeader);
ftdf_get_frame_header(sTransmitFrame.mPsdu, &frameHeader);
if ((frameHeader.options & FTDF_OPT_ACK_REQUESTED) == 0 || sTransmitStatus != OT_ERROR_NONE)
{
@@ -602,14 +516,14 @@ void da15000RadioProcess(otInstance *aInstance)
sTransmitDoneFrame = false;
otLogDebgPlat(sInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL);
otLogDebgPlat(aInstance, "Radio state: OT_RADIO_STATE_RECEIVE", NULL);
}
exit:
return;
}
void FTDF_sendFrameTransparentConfirm(void *handle, FTDF_Bitmap32 status)
void ftdf_send_frame_transparent_confirm(void *handle, ftdf_bitmap32_t status)
{
(void)handle;
@@ -635,12 +549,17 @@ void FTDF_sendFrameTransparentConfirm(void *handle, FTDF_Bitmap32 status)
sTransmitDoneFrame = true;
}
void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength,
FTDF_Octet *frame,
FTDF_Bitmap32 status,
FTDF_LinkQuality lqi)
static void radioRssiCalc(ftdf_link_quality_t link_quality)
{
otEXPECT(frameLength <= OT_RADIO_FRAME_MAX_SIZE);
sRssiReal = (ftdf_dbm)((0.5239 * (float)link_quality) - 114.8604);
}
void ftdf_rcv_frame_transparent(ftdf_data_length_t frame_length,
ftdf_octet_t *frame,
ftdf_bitmap32_t status,
ftdf_link_quality_t link_quality)
{
otEXPECT(frame_length <= OT_RADIO_FRAME_MAX_SIZE);
otEXPECT(sRadioState != OT_RADIO_STATE_DISABLED);
@@ -648,16 +567,18 @@ void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength,
if (status == FTDF_TRANSPARENT_RCV_SUCCESSFUL)
{
radioRssiCalc(link_quality);
#if OPENTHREAD_ENABLE_RAW_LINK_API
// Timestamp
sReceiveFrameAck.mMsec = otPlatAlarmMilliGetNow();
sReceiveFrameAck.mUsec = 0; // Don't support microsecond timer for now.
sReceiveFrame[sWriteFrame].mMsec = otPlatAlarmMilliGetNow();
sReceiveFrame[sWriteFrame].mUsec = 0; // Don't support microsecond timer for now.
#endif
sReceiveFrame[sWriteFrame].mChannel = sChannel;
sReceiveFrame[sWriteFrame].mLength = frameLength;
sReceiveFrame[sWriteFrame].mLqi = lqi;
sReceiveFrame[sWriteFrame].mLength = frame_length;
sReceiveFrame[sWriteFrame].mLqi = OT_RADIO_LQI_NONE;
sReceiveFrame[sWriteFrame].mPower = otPlatRadioGetRssi(sThreadInstance);
memcpy(sReceiveFrame[sWriteFrame].mPsdu, frame, frameLength);
memcpy(sReceiveFrame[sWriteFrame].mPsdu, frame, frame_length);
sWriteFrame = (sWriteFrame + 1) % RADIO_FRAMES_BUFFER_SIZE;
@@ -676,4 +597,3 @@ int8_t otPlatRadioGetReceiveSensitivity(otInstance *aInstance)
(void)aInstance;
return DA15000_RECEIVE_SENSITIVITY;
}
examples/platforms/da15000/random.c
+1 -1
View File
@@ -36,6 +36,7 @@
#include <openthread/platform/random.h>
#include "platform-da15000.h"
#include "hw_trng.h"
#include "sdk_defs.h"
@@ -125,4 +126,3 @@ otError otPlatRandomGetTrue(uint8_t *aOutput, uint16_t aOutputLength)
return OT_ERROR_NONE;
}
examples/platforms/da15000/startup_ARMCM0.S
-370
View File
@@ -1,370 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file startup_ARMCM0.S
* Startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V2.0
* Date: 16 August 2013
*/
.syntax unified
.arch armv6-m
.section text_reset
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
#if (dg_configSKIP_MAGIC_CHECK_AT_START == 0)
/* If the Magic Word {0xDEADBEEF, 0xDEADBEEF, 0xDEADBEEF, 0xDEAD10CC} is found at 0x7fd0000 then the
* execution will block for a while in order to give time to a debugger to attach. */
ldr r4, =0x7fd0000
ldmia r4!, {r0-r3}
ldr r4, =0xDEADBEEF
cmp r0, r4
bne .code_starts
cmp r1, r4
bne .code_starts
cmp r2, r4
bne .code_starts
ldr r4, =0xDEAD10CC
cmp r3, r4
bne .code_starts
/* Enable debugger */
ldr r4, =0x50000012
ldrh r5, [r4]
mov r6, r5
movs r1, #128
orrs r5, r5, r1
strh r5, [r4]
/* Block for 2'' */
ldr r0, =0x150000
.delay_loop:
subs r0, #1
bgt .delay_loop
/* Make sure that this will happen only once! */
ldr r4, =0x7fd0000
movs r0, #0
str r0, [r4]
/* Restore debugger setting */
ldr r4, =0x50000012
strh r6, [r4]
.code_starts:
#endif
/* RAM shuffling configuration should be determined from the image in the QSPI Flash or OTP
* and must be applied at the beginning of the Reset Vector. The interrupt vector table must
* be copied to the RAM base after the shuffling is done.
* NOTE: Even though there is an OTP field specifically for the shuffling configuration
* we must bypass it here since the shuffling might change between different
* QSPI FLASH image versions. For OTP images RAM shuffling configuration will never change,
* but we also apply it to ignore the OTP field in any case. */
ldr r4, =0x50000012
movs r0, #0
ldrh r0, [r4]
movs r1, #0x18
bics r0, r0, r1
movs r1, #dg_configSHUFFLING_MODE<<3
orrs r0, r0, r1
/* Update SYS_CTRL_REG. */
strh r0, [r4]
/* Copy ISR VT from from QSPI Flash/OTP to RAM. This must be done
* after applying shuffling mode. */
# if (dg_configIMAGE_FLASH_OFFSET == 0)
ldr r1, =0x8000008
# else
ldr r1, =(0x8000000 + dg_configIMAGE_FLASH_OFFSET)
# endif
ldr r2, =0x7FC0000
ldr r3, =0x7FC00C0
/* Block should be a multiple of 16 to traverse correctly L_loopIV */
subs r3, r2
ble .L_loopIV_done
.L_loopIV:
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
subs r3, #16
bgt .L_loopIV
.L_loopIV_done:
bl SystemInitPre
bl SystemInit
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#define __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r0, =__copy_table_end__
.L_loop0:
cmp r4, r0
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
push {r4}
.L_loop0_0:
subs r3, #16
blt .L_loop0_0_done
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
b .L_loop0_0
.L_loop0_0_done:
pop {r4}
adds r4, #12
b .L_loop0
.L_loop0_done:
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#define __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r0, =__zero_table_end__
movs r4, 0
movs r5, r4
mov r6, r4
mov r7, r4
.L_loop2:
cmp r3, r0
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
.L_loop2_0:
subs r2, #32 // Requires 32-byte alignment!
blt .L_loop2_0_done
stmia r1!, {r4-r7}
stmia r1!, {r4-r7}
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
/* Copy the address of the retained NMI and HardFault handlers to the vector table. */
ldr r0, =0x7FC0008
ldr r1, =NMI_Handler
str r1, [r0, #0]
ldr r1, =HardFault_Handler
str r1, [r0, #4]
bl SystemInitPost
bl main
.pool
.size Reset_Handler, . - Reset_Handler
.text
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
/*
* enable debugger:
* CRG_TOP->SYS_CTRL_REG_b.DEBUGGER_ENABLE = 1;
*/
movs r1, #0x50
lsls r1, #24
ldrh r2, [r1, #0x12]
movs r3, #0x80
orrs r2, r2, r3
strh r2, [r1, #0x12]
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
.thumb
.thumb_func
.align 1
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler BLE_WAKEUP_LP_Handler
def_irq_handler BLE_GEN_Handler
def_irq_handler FTDF_WAKEUP_Handler
def_irq_handler FTDF_GEN_Handler
def_irq_handler RFCAL_Handler
def_irq_handler COEX_Handler
def_irq_handler CRYPTO_Handler
def_irq_handler MRM_Handler
def_irq_handler UART_Handler
def_irq_handler UART2_Handler
def_irq_handler I2C_Handler
def_irq_handler I2C2_Handler
def_irq_handler SPI_Handler
def_irq_handler SPI2_Handler
def_irq_handler ADC_Handler
def_irq_handler KEYBRD_Handler
def_irq_handler IRGEN_Handler
def_irq_handler WKUP_GPIO_Handler
def_irq_handler SWTIM0_Handler
def_irq_handler SWTIM1_Handler
def_irq_handler QUADEC_Handler
def_irq_handler USB_Handler
def_irq_handler PCM_Handler
def_irq_handler SRC_IN_Handler
def_irq_handler SRC_OUT_Handler
def_irq_handler VBUS_Handler
def_irq_handler DMA_Handler
def_irq_handler RF_DIAG_Handler
def_irq_handler TRNG_Handler
def_irq_handler DCDC_Handler
def_irq_handler XTAL16RDY_Handler
def_irq_handler RESERVED31_Handler
.section text_retained
.align 1
.thumb
.thumb_func
.globl NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r1, =NMI_HandlerC
movs r0, #4
mov r2, lr
tst r0, r2
beq NMI_stacking_using_MSP
mrs r0, psp
b stack_check
NMI_stacking_using_MSP:
mrs r0, msp
b stack_check
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb
.thumb_func
.globl HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r1, =HardFault_HandlerC
movs r0, #4
mov r2, lr
tst r0, r2
beq HF_stacking_using_MSP
mrs r0, psp
b stack_check
HF_stacking_using_MSP:
mrs r0, msp
stack_check:
/* 0x7FC0000 is start of RAM */
ldr r2, =0x7FC0000
cmp r0, r2
blt Wrong_SP
/* Check SYS_CTRL_REG:CACHERAM_MUX */
ldr r2, =0x50000012
ldrh r2, [r2]
movs r3, #1
lsls r3, r3, #10
ands r2, r2, r3
bne cache_is_on
/* 0x7FE4000 marks end of RAM (assuming that the CACHE is used as RAM) */
ldr r2, =0x7FE4000-32
b check_end_of_ram
cache_is_on:
/* 0x7FE0000 marks end of RAM */
ldr r2, =0x7FE0000-32
check_end_of_ram:
cmp r0, r2
bgt Wrong_SP
bx r1
Wrong_SP:
/* Freeze WDog at all times */
ldr r0, =0x50003300
ldr r1, =8
strh r1, [r0, #0]
/* Enable debugger at all times */
ldr r4, =0x50000012
ldrh r0, [r4, #0]
movs r1, #0x80
orrs r0, r0, r1
/* Update SYS_CTRL_REG */
strh r0, [r4, #0]
/* Wait for the WDog to hit or a debug session to start */
b .
.size HardFault_Handler, . - HardFault_Handler
.end
examples/platforms/da15000/system_ARMCM0.c
-609
View File
@@ -1,609 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file system_ARMCM0.c
* CMSIS Device System Source File for ARMCM0 Device Series.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <sys/errno.h>
#include "sdk_defs.h"
#include "interrupts.h"
#include "hw_cpm.h"
#include "hw_otpc.h"
#include "hw_qspi.h"
#include "hw_watchdog.h"
#include "sys_tcs.h"
#include "qspi_automode.h"
/*
* This is just so that compilation doesn't break for RAM builds.
* The code that uses it is optimized out in RAM builds.
*/
extern uint32_t NVMS_PARAM_PART_end;
/*
* TCS Offsets
*/
#define OTP_HEADER_BASE_ADDR_IN_OTP (0x7F8E9C0)
#define TCS_SECTION_OFFSET (184) /* 0x7F8EA78 - 0x7F8E9C0 */
#define TCS_SECTION_LENGTH (24) /* 24 entries, 16 bytes each for OTP */
#ifndef __SYSTEM_CLOCK
# define __SYSTEM_CLOCK (16000000UL) /* 16 MHz */
#endif
#if (dg_configUSE_LP_CLK == LP_CLK_32000)
# define LP_CLK_FREQ (32000)
#elif (dg_configUSE_LP_CLK == LP_CLK_32768)
# define LP_CLK_FREQ (32768)
#elif (dg_configUSE_LP_CLK == LP_CLK_RCX)
# define LP_CLK_FREQ (0)
#else
# error "dg_configUSE_LP_CLK is not defined or has an unknown value!"
#endif
/*
* Linker symbols
*
* Note: if any of them is missing, please correct your linker script. Please refer to the linker
* script of pxp_reporter.
*/
extern uint32_t __copy_table_start__;
extern uint32_t __copy_table_end__;
extern uint32_t __zero_table_start__;
extern uint32_t __zero_table_end__;
extern uint8_t end;
extern uint8_t __HeapLimit;
/*
* Global variables
*/
__RETAINED_RW static uint8_t *heapend = &end;
__RETAINED_UNINIT __attribute__((unused)) uint32_t black_orca_chip_version;
uint32_t SystemCoreClock __RETAINED = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
uint32_t SystemLPClock __RETAINED = LP_CLK_FREQ; /*!< System Low Power Clock Frequency (LP Clock)*/
/**
* @brief Memory safe implementation of newlib's _sbrk().
*
*/
__LTO_EXT
void *_sbrk(int incr)
{
uint8_t *newheapstart;
if (heapend + incr > &__HeapLimit)
{
/* Hitting this, means that the value of _HEAP_SIZE is too small.
* The value of incr is in stored_incr at this point. By checking the equation
* above, it is straightforward to determine the missing space.
*/
volatile int stored_incr __attribute__((unused));
stored_incr = incr;
ASSERT_ERROR(0);
errno = ENOMEM;
return (void *) - 1;
}
newheapstart = heapend;
heapend += incr;
return newheapstart;
}
/**
* Apply trim values from OTP.
*
* @brief Writes the trim values located in the OTP to the corresponding system registers.
*
* @param[out] tcs_array The valid <address, value> pairs are placed in this buffer.
* @param[out] valid_entries The number of valid pairs.
*
* @return True if at least one trim value has been applied, else false.
*
*/
static bool apply_trim_values_from_otp(uint32_t *tcs_array, uint32_t *valid_entries)
{
uint32_t address;
uint32_t inverted_address;
uint32_t value;
uint32_t inverted_value;
uint32_t *p;
int i;
int index = 0;
int vdd = 0;
int retries = 0;
bool forward_reading = true;
bool res = false;
p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET);
for (i = 0; i < TCS_SECTION_LENGTH; i++)
{
do
{
address = *p;
p++;
inverted_address = *p;
p++;
value = *p;
p++;
inverted_value = *p;
p++;
if ((address == 0) && (value == 0))
{
break;
}
// Check validity
if ((address != ~inverted_address) || (value != ~inverted_value))
{
// Change LDO core voltage level and retry
vdd++;
vdd &= 0x3;
REG_SETF(CRG_TOP, LDO_CTRL1_REG, LDO_CORE_SETVDD, vdd);
// Wait for the voltage to settle...
SysTick->CTRL = 0;
SysTick->LOAD = 500; // 500 * (62.5 * 4) = 125usec
SysTick->VAL = 0;
SysTick->CTRL = 0x5; // Start using system clock
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) {}
// Adjust the read pointer
p -= 4;
}
retries++;
if (retries == 32)
{
// Unrecoverable problem! Assert in development mode
ASSERT_WARNING(0);
// Unrecoverable problem! Issue a HW reset.
hw_cpm_reset_system();
}
}
while ((address != ~inverted_address) || (value != ~inverted_value));
retries = 0;
// Read the complete TCS area but skip empty entries.
if ((address == 0) && (value == 0))
{
if ((BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, E))
|| ((dg_configUSE_AUTO_CHIP_DETECTION == 1)
&& (CHIP_IS_AE || CHIP_IS_BA)))
{
if (!forward_reading)
{
break;
}
forward_reading = false;
p = (uint32_t *)(OTP_HEADER_BASE_ADDR_IN_OTP + TCS_SECTION_OFFSET);
p += (TCS_SECTION_LENGTH - 1) * 4;
}
else
{
(void)forward_reading;
}
continue;
}
if (!forward_reading)
{
p -= 8;
}
sys_tcs_store_pair(address, value);
tcs_array[(index * 2) + 0] = address;
tcs_array[(index * 2) + 1] = value;
*valid_entries = index + 1;
index++;
res = true;
}
return res;
}
/**
* Check whether the code has been compiled for a chip version that is compatible with the chip
* it runs on.
*/
static bool is_compatible_chip_version(void)
{
const uint32_t ver = black_orca_get_chip_version();
/* Oldest supported version is AE. */
if ((ver < BLACK_ORCA_IC_VERSION(A, E)) && (dg_configUSE_AUTO_CHIP_DETECTION == 0))
{
return false;
}
if ((ver == BLACK_ORCA_TARGET_IC) || (dg_configUSE_AUTO_CHIP_DETECTION == 1))
{
return true;
}
return false;
}
#ifdef OS_BAREMETAL
static volatile bool nortos_xtal16m_settled = false;
void XTAL16RDY_Handler(void)
{
nortos_xtal16m_settled = true;
}
/* carry out clock initialization sequence */
static void nortos_clk_setup(void)
{
// Setup DIVN
if (dg_configEXT_CRYSTAL_FREQ == EXT_CRYSTAL_IS_16M)
{
hw_cpm_set_divn(false); // External crystal is 16MHz
}
else
{
hw_cpm_set_divn(true); // External crystal is 32MHz
}
hw_cpm_enable_rc32k();
hw_cpm_lp_set_rc32k();
NVIC_ClearPendingIRQ(XTAL16RDY_IRQn);
nortos_xtal16m_settled = false;
NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ
hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K);
hw_cpm_enable_xtal16m(); // Enable XTAL16M
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
/* Wait for XTAL16M to settle */
while (!nortos_xtal16m_settled);
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M);
}
#endif /* OS_BAREMETAL */
static __RETAINED_CODE void configure_cache(void)
{
bool flush = false;
GLOBAL_INT_DISABLE();
if (dg_configCACHEABLE_QSPI_AREA_LEN != -1)
{
uint32_t cache_len;
/* dg_configCACHEABLE_QSPI_AREA_LEN must be 64KB-aligned */
ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0xFFFF) == 0);
/*
* dg_configCACHEABLE_QSPI_AREA_LEN shouldn't set any bits that do not fit in
* CACHE_CTRL2_REG.CACHE_LEN (9 bits wide) after shifting out the lower 16 bits
*/
ASSERT_WARNING((dg_configCACHEABLE_QSPI_AREA_LEN & 0x1FF0000)
== dg_configCACHEABLE_QSPI_AREA_LEN);
/*
* set cacheable area
*
* setting CACHE_CTRL2_REG.CACHE_LEN to N, actually sets the size of the cacheable
* area to (N + 1) * 64KB
* special cases:
* N == 0 --> no caching
* N == 1 --> 128KB are cached, i.e. no way to cache only 64KB
*/
cache_len = dg_configCACHEABLE_QSPI_AREA_LEN >> 16;
/* cannot cache only 64KB! */
ASSERT_WARNING(cache_len != 1);
if (cache_len > 1)
{
cache_len--;
}
REG_SETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN, cache_len);
}
if (dg_configCACHE_ASSOCIATIVITY != CACHE_ASSOC_AS_IS)
{
if (CACHE->CACHE_ASSOCCFG_REG != dg_configCACHE_ASSOCIATIVITY)
{
/* override the set associativity setting */
CACHE->CACHE_ASSOCCFG_REG = dg_configCACHE_ASSOCIATIVITY;
flush = true;
}
}
if (dg_configCACHE_LINESZ != CACHE_LINESZ_AS_IS)
{
if (CACHE->CACHE_LNSIZECFG_REG != dg_configCACHE_LINESZ)
{
/* override the cache line setting */
CACHE->CACHE_LNSIZECFG_REG = dg_configCACHE_LINESZ;
flush = true;
}
}
if (flush && (REG_GETF(CACHE, CACHE_CTRL2_REG, CACHE_LEN) > 0))
{
/* flush cache */
REG_SET_BIT(CACHE, CACHE_CTRL1_REG, CACHE_FLUSH);
}
GLOBAL_INT_RESTORE();
}
/**
* Basic system setup
*
* @brief Setup the AMBA clocks. Ensure proper alignment of copy and zero table entries.
*/
void SystemInitPre(void) __attribute__((section("text_reset")));
void SystemInitPre(void)
{
/*
* Enable debugger.
*/
if (dg_configENABLE_DEBUGGER)
{
ENABLE_DEBUGGER;
}
/*
* Bandgap has already been set by the bootloader.
* Use fast clocks from now on.
*/
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
/*
* Ensure 16-byte alignment for all elements of each entry in the Copy Table. This is
* a requirement imposed by the fast start-up code! If any of the assertions below hits,
* please correct your linker script file accordingly!
*/
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
{
uint32_t *p;
for (p = &__copy_table_start__; p < &__copy_table_end__; p += 3)
{
ASSERT_WARNING_UNINIT((p[0] & 0xF) == 0); // from
ASSERT_WARNING_UNINIT((p[1] & 0xF) == 0); // to
ASSERT_WARNING_UNINIT((p[2] & 0xF) == 0); // size
}
}
/*
* Ensure 32-byte alignment for all elements of each entry in the Data Table. This is
* a requirement imposed by the fast start-up code! If any of the assertions below hits,
* please correct your linker script file accordingly!
*/
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
{
uint32_t *p;
for (p = &__zero_table_start__; p < &__zero_table_end__; p += 2)
{
ASSERT_WARNING_UNINIT((p[0] & 0x1F) == 0); // start at
ASSERT_WARNING_UNINIT((p[1] & 0x1F) == 0); // size
}
}
}
/**
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
/*
* Make sure we are running on a chip version that the code has been built for.
*/
ASSERT_WARNING_UNINIT(is_compatible_chip_version());
/*
* Detect chip version (optionally).
*/
if (dg_configUSE_AUTO_CHIP_DETECTION == 1)
{
black_orca_chip_version = black_orca_get_chip_version();
if (!CHIP_IS_AE && !CHIP_IS_BA)
{
// Oldest supported version is AE.
ASSERT_WARNING_UNINIT(0);
}
}
/*
* Initialize UNINIT variables.
*/
sys_tcs_init();
/*
* BOD protection
*/
if (dg_configUSE_BOD == 1)
{
/* BOD has already been enabled at this point but it must be reconfigured */
hw_cpm_configure_bod_protection();
}
else
{
hw_cpm_deactivate_bod_protection();
}
/*
* Apply default priorities to interrupts.
*/
set_interrupt_priorities(__dialog_interrupt_priorities);
/*
* If we are executing from RAM, make sure that code written in Flash won't have left the
* system in "unknown" state.
*/
if (dg_configCODE_LOCATION == NON_VOLATILE_IS_NONE)
{
GLOBAL_INT_DISABLE();
CRG_TOP->PMU_CTRL_REG |= 0xE;
CRG_TOP->PMU_CTRL_REG &= ~1;
GLOBAL_INT_RESTORE();
}
/*
* Switch to RC16.
*/
hw_cpm_set_sysclk(SYS_CLK_IS_RC16); // Use RC16
hw_cpm_disable_xtal16m(); // Disable XTAL16M
/*
* Set highest access speed for QSPI Flash.
*/
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED)
{
hw_qspi_set_div(HW_QSPI_DIV_1);
}
}
/**
* Process the TCS
*
* @brief Process the TCS section.
*/
void SystemInitPost(void)
{
SystemCoreClock = __SYSTEM_CLOCK;
SystemLPClock = LP_CLK_FREQ;
uint32_t tcs_pairs[TCS_SECTION_LENGTH * 2];
uint32_t valid_tcs_pairs = 0;
hw_cpm_start_ldos(); // Make sure all LDOs are as expected
hw_cpm_reset_radio_vdd(); // Set Radio voltage to 1.40V
/*
* Initialize Flash
*/
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED)
{
qspi_automode_init(); // The bootloader may have left the Flash in wrong mode...
}
/*
* Retrieve trim values from OTP.
*/
hw_otpc_init(); // Start clock.
hw_otpc_disable(); // Make sure it is in standby mode.
hw_otpc_init(); // Restart clock.
hw_otpc_manual_read_on(false);
/*
* Apply trim values from OTP.
*/
apply_trim_values_from_otp(tcs_pairs, &valid_tcs_pairs);
if (dg_configIMAGE_SETUP == PRODUCTION_MODE)
{
ASSERT_ERROR(sys_tcs_is_calibrated_chip); // Uncalibrated chip!!!
}
hw_otpc_manual_read_off();
hw_otpc_disable();
if (dg_configFLASH_CONNECTED_TO != FLASH_IS_NOT_CONNECTED)
{
hw_cpm_enable_qspi_init(); // Enable QSPI init after wakeup
hw_qspi_set_read_pipe_clock_delay(6); // Set read pipe clock delay to 6 (Last review date: Feb 15, 2016 - 12:25:47)
}
/*
* All trim values have been loaded from TCS or defaults are used.
*/
sys_tcs_sort_array();
sys_tcs_apply(tcs_system);
hw_cpm_set_preferred_values();
#ifdef OS_BAREMETAL
/* perform clock initialization here, as there is no CPM to do it later for us */
nortos_clk_setup();
#endif
configure_cache();
}
uint32_t DA15000_phy_addr(uint32_t addr)
{
static const uint32 remap[] =
{
MEMORY_ROM_BASE,
MEMORY_OTP_BASE,
MEMORY_QSPIF_BASE,
MEMORY_SYSRAM_BASE,
MEMORY_QSPIF_BASE,
MEMORY_OTP_BASE,
MEMORY_CACHERAM_BASE,
0
};
if (addr >= MEMORY_REMAPPED_END)
{
return addr;
}
return addr + remap[REG_GETF(CRG_TOP, SYS_CTRL_REG, REMAP_ADR0)];
}
examples/platforms/da15000/uart.c
+9 -4
View File
@@ -26,16 +26,16 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <openthread/config.h>
#include <openthread/platform/uart.h>
#include "platform-da15000.h"
#include "hw_gpio.h"
#include "hw_uart.h"
#include "platform-da15000.h"
static bool sUartWriteDone = false;
static bool sUartReadDone = false;
static char *sInitBuf = NULL;
static uint8_t sUartBuf;
static void UartSignalWrite(void *p, uint16_t transferred)
@@ -104,6 +104,12 @@ void da15000UartProcess(void)
sUartWriteDone = false;
otPlatUartSendDone();
}
if (sInitBuf == NULL)
{
sInitBuf = "\n";
otPlatUartReceived((uint8_t *)sInitBuf, 1);
}
}
otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength)
@@ -112,4 +118,3 @@ otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength)
return OT_ERROR_NONE;
}
examples/platforms/da15000/vector_table.S
-175
View File
@@ -1,175 +0,0 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file vector_table.S
* Interrupt Vector Table and Patch Table.
*/
.syntax unified
.arch armv6 - m
.section .stack
.align 3
.equ Stack_Size, __STACK_SIZE
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
.equ Heap_Size, __HEAP_SIZE
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long Default_Handler /* replaced by NMI_Handler after the ISR is copied to retRAM*/
.long Default_Handler /* replaced by HardFault_Handler after the ISR is copied to retRAM */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long BLE_WAKEUP_LP_Handler /* 0 */
.long BLE_GEN_Handler /* 1 */
.long FTDF_WAKEUP_Handler /* 2 */
.long FTDF_GEN_Handler /* 3 */
.long RFCAL_Handler /* 4 */
.long COEX_Handler /* 5 */
.long CRYPTO_Handler /* 6 */
.long MRM_Handler /* 7 */
.long UART_Handler /* 8 */
.long UART2_Handler /* 9 */
.long I2C_Handler /* 10 */
.long I2C2_Handler /* 11 */
.long SPI_Handler /* 12 */
.long SPI2_Handler /* 13 */
.long ADC_Handler /* 14 */
.long KEYBRD_Handler /* 15 */
.long IRGEN_Handler /* 16 */
.long WKUP_GPIO_Handler /* 17 */
.long SWTIM0_Handler /* 18 */
.long SWTIM1_Handler /* 19 */
.long QUADEC_Handler /* 20 */
.long USB_Handler /* 21 */
.long PCM_Handler /* 22 */
.long SRC_IN_Handler /* 23 */
.long SRC_OUT_Handler /* 24 */
.long VBUS_Handler /* 25 */
.long DMA_Handler /* 26 */
.long RF_DIAG_Handler /* 27 */
.long TRNG_Handler /* 28 */
.long DCDC_Handler /* 29 */
.long XTAL16RDY_Handler /* 30 */
.long RESERVED31_Handler /* 31 */
.size __isr_vector, . - __isr_vector
/*
* Patch Table
* Notice: it crosses the 0x100 boundary
* in cached mode, the first entries will be copied to
* (and accessed from) RAM and others will only lie on
* QSPI flash or OTP.
*
* In C declare: extern uint32_t __patch_table_start[];
*/
.section .patch_table, "a"
.align 4
.globl __patch_table_start
__patch_table_start:
/*
* 28 32-bit entries, initialized to "pointer to Default_Patch_Code"
*
* NOTE: we assume that SYS_CTRL_REG.REMAP_INTVECT == 1
*/
.long Default_Patch_Code_Handler /* 0, in RAM */
.long Default_Patch_Code_Handler /* 1, in RAM */
.long Default_Patch_Code_Handler /* 2, in RAM */
.long Default_Patch_Code_Handler /* 3, in RAM */
.long Default_Patch_Code_Handler /* 4, in RAM */
.long Default_Patch_Code_Handler /* 5, in RAM */
.long Default_Patch_Code_Handler /* 6, in RAM */
.long Default_Patch_Code_Handler /* 7, in RAM */
.long Default_Patch_Code_Handler /* 8, in RAM */
.long Default_Patch_Code_Handler /* 9, in RAM */
.long Default_Patch_Code_Handler /* 10, in RAM */
.long Default_Patch_Code_Handler /* 11, in RAM */
/*
* Chip version: AD
* Entries 12, 13, 14 and 15 are unusable and skipped in the QSPI image,
* to account for the overhead of the QSPI header (16 bytes).
*
* Chip version: AA, AC, AE
* Entries 14 and 15 are unusable and skipped in the QSPI image,
* to account for the overhead of the QSPI header (8 bytes).
*
* The mkimage tool is responsible for stripping the proper entries from the QSPI image.
*/
.long Default_Patch_Code_Handler /* 12 */
.long Default_Patch_Code_Handler /* 13 */
.long 0xDEADBEEF /* 14 */
.long 0xDEADBEEF /* 15 */
.size __patch_table_start, . - __patch_table_start
__patch_table_end:
.section .default_patch_code_handler_section, "a"
.globl Default_Patch_Code_Handler
.align 1
.thumb
.thumb_func
.type Default_Patch_Code_Handler, % function
Default_Patch_Code_Handler:
bkpt #0
bkpt #0
third_party/dialog/DialogSDK/bsp/adapters/include/ad_rf.h
Vendored
-166
View File
@@ -1,166 +0,0 @@
/**
* \addtogroup BSP
* \{
* \addtogroup ADAPTERS
* \{
* \addtogroup RF_ADAPTER
*
* \brief RF adapter
*
* \{
*/
/**
*****************************************************************************************
*
* @file
*
* @brief Radio module access API.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*****************************************************************************************
*/
#ifndef AD_RF_H_
#define AD_RF_H_
#if dg_configRF_ADAPTER
#include <stdbool.h>
#include <stdint.h>
#include "hw_rf.h"
/**
* @brief Performs RF adapter initialization
*/
void ad_rf_init(void);
/**
* \brief Retry a failed calibration
*
* This will power-cycle RF, reapply tcs and recommended settings, and
* retry calibration. If calibration fails again, it will reset the system
* (using the wdog)
*/
void ad_rf_retry_calibration();
/**
* \brief Start Calibration procedure and check if it succeeds
*
* This will start the calibration procedure, and check if the calibration initial
* part (the iff calibration) succeeds. If not, it will reset the RF block and retry.
* If the calibration still fails after the second attempt, it will trigger a
* watchdog reset
*
*/
static inline void ad_rf_start_and_check_calibration()
{
if (!hw_rf_start_calibration())
ad_rf_retry_calibration();
}
/**
* \brief Perform RF system initialization.
*
* This will preform a full RF system init, and check if the
* calibration initial part (the iff calibration) succeeds. If not, it will
* reset the RF block and retry.
* If the calibration still fails after the second attempt, it will trigger a
* watchdog reset
*
*/
static inline void ad_rf_system_init()
{
if (!hw_rf_system_init())
ad_rf_retry_calibration();
}
/**
* \brief Start Calibration procedure and return.
*
* This will block for some time (with interrupts disabled) in order to perform
* The first part of calibration (IFF, DC offset and the start of gain calib).
*
*/
static inline void ad_rf_start_calibration()
{
ad_rf_start_and_check_calibration();
}
/**
* \brief Sets parameters according to their recommended values, taking RF state into account.
*
* Acts like \ref hw_rf_set_recommended_settings but makes sure that the RF power domain is on and
* unconfigured. Disables interrupts.
*
*/
static inline void ad_rf_request_recommended_settings(void)
{
hw_rf_request_recommended_settings();
}
/**
* \brief Requests that the RF is turned on
*
* Requests that the RF is turned on, if not already on. Disables interrupts.
*
* \param [in] mode_ble True, if the rf is needed for ble
*
*/
static inline void ad_rf_request_on(bool mode_ble)
{
hw_rf_request_on(mode_ble);
}
/**
* \brief Requests that the RF is turned off
*
* Requests that the RF is turned off, if not already off.
* The RF will be turned off only if there are no more
* requests (ie. all requesters have called ad_rf_request_off())
* Disables interrupts
*
* \param [in] mode_ble True, if the rf was needed for ble
*/
static inline void ad_rf_request_off(bool mode_ble)
{
hw_rf_request_off(mode_ble);
}
#endif /* dg_configRF_ADAPTER */
#endif /* AD_RF_H_ */
/**
* \}
* \}
* \}
*/
third_party/dialog/DialogSDK/bsp/config/bsp_debug.h
Vendored
+19 -3
View File
@@ -597,9 +597,10 @@
/**
* \brief Enables BLE diagnostic signals.
*
* There are 4 diagnostic signal configurations that user can choose from. To enable a specific
* configuration, simply define dg_configBLE_DIAGN_CONFIG with the perspective configuration ID.
* Configuration ID 0 disables BLE diagnostics.
* There are 5 (4 plus the COEX mode, see next table) diagnostic signal configurations that
* user can choose from. To enable a specific configuration, simply define
* dg_configBLE_DIAGN_CONFIG with the perspective configuration ID. Configuration ID 0 disables
* BLE diagnostics.
*
* ------------------------------------------------------------------------------------------------------
* | Signal | Pin | Config 1 | Config 2 | Config 3 | Config 4 |
@@ -620,6 +621,21 @@
* ------------------------------------------------------------------------------------------------------
* | ble_diag7 | P2_3 | ble_event_irq | rf_rx_data | rf_tx_data_valid | ble_event_irq |
* ------------------------------------------------------------------------------------------------------
*
* Coex Mode Diagnostics: The COEX interface multiplexes its diagnostic pins on top of BLE
* diagnostics when option dg_configCOEX_ENABLE_DIAGS is set to 1. However, diagnostic signals
* ble_diag0 and ble_diag1 are unused by the COEX diagnostics and can be used for BLE. More
* specifically, Config 5 enables the following configuration, that can be used simultaneously
* with COEX diagnostics (dg_configCOEX_ENABLE_DIAGS == 1):
*
* ----------------------------------------------
* | Signal | Pin | Config 5 |
* ----------------------------------------------
* | ble_diag0 | P3_0 | radcntl_txen |
* ----------------------------------------------
* | ble_diag1 | P3_1 | radcntl_rxen |
* ----------------------------------------------
*
*/
#ifndef dg_configBLE_DIAGN_CONFIG
#define dg_configBLE_DIAGN_CONFIG (0)
third_party/dialog/DialogSDK/bsp/config/bsp_defaults.h
Vendored
+687 -6
View File
@@ -174,7 +174,7 @@
#endif
/**
* \brief When set to 1, the chip version (DA14680/1-01 or DA14682/3-BA ) will be detected\n
* \brief When set to 1, the chip version (DA14680/1-01 or DA14682/3-00, DA15XXX-00 ) will be detected\n
* automatically.
* \note It cannot be used in BLE applications because of the different linker scripts\n
* that are used.
@@ -617,7 +617,7 @@
#endif
/**
* \brief Watchdog Service
* \brief Watchdog Service
*
* - 1: enabled
* - 0: disabled
@@ -782,7 +782,7 @@
#endif
/**
* \brief When set to 1, the USB interface is used.
* \brief When set to 1, the USB interface is used for data transfers.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
@@ -1056,7 +1056,7 @@
* This is a deprecated configuration hence not to be defined by an application.
* When entering hibernation mode then:
* A DA14680/1-01 system reboots only via an interrupt from the WKUP Ctrl or VBUS.
* A DA14682/3-BA system reboots only via an interrupt from the WKUP Ctrl.
* A DA14682/3-00, DA15XXX-00 system reboots only via an interrupt from the WKUP Ctrl.
*/
#ifdef dg_configLOW_VBAT_HANDLING
#error "Configuration option dg_configLOW_VBAT_HANDLING is no longer supported."
@@ -1471,6 +1471,16 @@
(SW_CURSOR_PORT == 2 ? &(GPIO->P2_RESET_DATA_REG) : \
(SW_CURSOR_PORT == 3 ? &(GPIO->P3_RESET_DATA_REG) : \
&(GPIO->P4_RESET_DATA_REG)))))
/**
* \brief Enable task monitoring.
*
* \note Task monitoring can only be enabled if RTT or RETARGET is enabled
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configENABLE_TASK_MONITORING
#define dg_configENABLE_TASK_MONITORING (0)
#endif
/* ---------------------------------------------------------------------------------------------- */
/**
@@ -1548,7 +1558,13 @@
/* ------------------------------- Arbiter configuration settings ------------------------------- */
/**
* \brief Custom arbiter configuration support.
* \brief Custom arbiter configuration support
* When defined, coex is configurable and priorities can be set:
* -either manually, per mac, using coex api
* -or automatically, by the PTIs provided by each mac
*
* When not defined, coex operates with the default/fixed priority scheme:
* BLE traffic has always higher priority than FTDF.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
@@ -1564,6 +1580,32 @@
#ifndef dg_configCOEX_ENABLE_STATS
#define dg_configCOEX_ENABLE_STATS (0)
#endif
/**
* \brief Arbiter diagnostics enable
*
* This automatically enables arbiter diagnostic signals (when RF PD is on)
*
* See hw_coex.h for more information.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configCOEX_ENABLE_DIAGS
#define dg_configCOEX_ENABLE_DIAGS (0)
#endif
/**
* \brief Arbiter diagnostics mode
*
* This is the default mode for arbiter diagnostics.
*
* See hw_coex.h for more information.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configCOEX_DIAGS_MODE
#define dg_configCOEX_DIAGS_MODE (HW_COEX_DIAG_MODE_3)
#endif
/* ---------------------------------------------------------------------------------------------- */
/**
@@ -1716,12 +1758,85 @@
#ifndef dg_configUSE_IF_PDM
#define dg_configUSE_IF_PDM (0)
#endif
/* ---------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------- */
/**
* \}
*/
/* ------------------------------- USB settings ------------------------------------------------ */
/**
* \addtogroup USB_SETTINGS
*
* \brief USB DMA enable configuration settings
*
* The macros in this section are used to enable the DMA with USB and to define the two possible end point to use the DMA for data transfers.
* \{
*/
/**
* \brief Enable the DMA for reading/writing data to USB EP.\n
* By default the USB DMA is not enabled.\n
* To enable the DMA for the USB, set this the macro to value (1) in the custom_config_xxx.h file.\n
* When the USB DMA is enabled, the default end points with DMA are EP1 and EP2. \n
* It is possible only one TX and one RX end point to use DMA.\n
* User can choose a different pair of end points to use the DMA as needed according to app requirements.\n
* To change the end points using DMA, set in the the custom_config_xxx.h file the desired values for the macros:
* \par \c dg_configUSB_TX_DMA_EP
* valid values: 1,3,5\n
* default value: 1
* \par \c dg_configUSB_RX_DMA_EP
* valid values: 2,4,6\n
* default value: 2
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configUSB_DMA_SUPPORT
#define dg_configUSB_DMA_SUPPORT (0)
#endif
/**
* \brief The USB TX end point (D-->H) to enable the DMA.\n
* User can choose a different pair of end points to use the DMA as needed according to app requirements.\n
* To change the TX end point using DMA, set in the the custom_config_xxx.h file the desired value for this macros.
* \par \c dg_configUSB_TX_DMA_EP
* valid values: 1,3,5\n
* default value: 1
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configUSB_TX_DMA_EP
#define dg_configUSB_TX_DMA_EP (1)
#endif
/**
* \brief The USB RX end point (D-->H) to enable the DMA.\n
* User can choose a different pair of end points to use the DMA as needed according to app requirements.\n
* To change the RX end point using DMA, set in the the custom_config_xxx.h file the desired value for this macros.
* \par \c dg_configUSB_RX_DMA_EP
* valid values: 2,4,6\n
* default value: 2
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configUSB_RX_DMA_EP
#define dg_configUSB_RX_DMA_EP (2)
#endif
/* ---------------------------------------------------------------------------------------------- */
/**
* \}
*/
/* ------------------------------- WKUP settings ------------------------------------------------ */
/**
@@ -1744,7 +1859,7 @@
* \brief WKUP latch wakeup (io) source support
*
* \note In chip revision DA14680/1-01, this feature is implemented in s/w
* \note In chip revision DA14682/3-BA, this feature is implemented in h/w
* \note In chip revision DA14682/3-00, DA15XXX-00, this feature is implemented in h/w
*
* \bsp_default_note{\bsp_config_option_app,}
*/
@@ -2464,7 +2579,573 @@
/* ---------------------------------------------------------------------------------------------- */
/* ---------------------------------- MEMORY LAYOUT CONFIGURATION ------------------------------- */
/**
* \addtogroup MEMORY_LAYOUT_SETTINGS
*
* \brief Memory layout configuration settings.
* \{
*/
/**
* \brief Controls the retention RAM optimization.
*
* - 0 : All RAM is retained.
* - 1 : Retention memory size is optimal.
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configOPTIMAL_RETRAM
#define dg_configOPTIMAL_RETRAM (0)
#endif
/**
* \addtogroup OTP_PROJECT_MEMORY_LAYOUT_SETTINGS
*
* \brief Memory layout configuration settings for a OTP project.
* \{
*/
/**
* \brief Code size in OTP projects, no product specific.
*
* \note Code size cannot be more than 58K.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CODE_SIZE
#define dg_configOTP_CODE_SIZE ( 58 * 1024)
#endif
/**
* \brief RAM-block size in cached mode, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RAM_SIZE
#define dg_configOTP_CACHED_RAM_SIZE (64 * 1024)
#endif
/**
* \brief Retained-RAM-0-block size in cached mode, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE
#define dg_configOTP_CACHED_RETRAM_0_SIZE ( 64 * 1024)
#endif
/**
* \brief Retained-RAM-1-block size in cached mode, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE
#define dg_configOTP_CACHED_RETRAM_1_SIZE ( 0 * 1024)
#endif
/**
* \brief Retained-RAM-0-block size in mirror mode, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_MIRROR_RETRAM_0_SIZE
#define dg_configOTP_MIRROR_RETRAM_0_SIZE ( 48 * 1024)
#endif
/**
* \brief Retained-RAM-1-block size in mirror mode, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE
#define dg_configOTP_MIRROR_RETRAM_1_SIZE ( 0 * 1024)
#endif
/**
* \brief Retained-RAM-0-block size for optimal retention memory in cached mode, no product specific.
*
* \see dg_configOPTIMAL_RETRAM option
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE
#define dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE ( 32 * 1024)
#endif
/**
* \brief Retained-RAM-1-block size for optimal retention memory in cached mode, no product specific.
*
* \see dg_configOPTIMAL_RETRAM option
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE
#define dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE ( 32 * 1024)
#endif
/**
* \brief RAM-block size in mirror mode, no product specific.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_MIRROR_RAM_SIZE
#define dg_configOTP_MIRROR_RAM_SIZE ( 16 * 1024)
#endif
/**
* \brief Code size in OTP projects for DA14680/1-01.
*
* \note Code size cannot be more than 58K.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CODE_SIZE_AE
#define dg_configOTP_CODE_SIZE_AE dg_configOTP_CODE_SIZE
#endif
/**
* \brief Code size in OTP projects for DA14682/3-00, DA15XXX-00.
*
* \note Code size cannot be more than 58K.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CODE_SIZE_BB
#define dg_configOTP_CODE_SIZE_BB dg_configOTP_CODE_SIZE
#endif
/**
* \brief RAM-block size in cached mode for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RAM_SIZE_AE
#define dg_configOTP_CACHED_RAM_SIZE_AE dg_configOTP_CACHED_RAM_SIZE
#endif
/**
* \brief Retained-RAM-0-block size in cached mode for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE_AE
#define dg_configOTP_CACHED_RETRAM_0_SIZE_AE dg_configOTP_CACHED_RETRAM_0_SIZE
#endif
/**
* \brief Retained-RAM-1-block size in cached mode for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE_AE
#define dg_configOTP_CACHED_RETRAM_1_SIZE_AE dg_configOTP_CACHED_RETRAM_1_SIZE
#endif
/**
* \brief Retained-RAM-0-block size for optimal retention memory in cached mode for DA14680/1-01.
*
* \see dg_configOPTIMAL_RETRAM option
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE_AE
#define dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE_AE dg_configOTP_CACHED_OPTIMAL_RETRAM_0_SIZE
#endif
/**
* \brief Retained-RAM-1-block size for optimal retention memory in cached mode for DA14680/1-01.
*
* \see dg_configOPTIMAL_RETRAM option
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE_AE
#define dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE_AE dg_configOTP_CACHED_OPTIMAL_RETRAM_1_SIZE
#endif
/**
* \brief RAM-block size in cached mode for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RAM_SIZE_BB
#define dg_configOTP_CACHED_RAM_SIZE_BB dg_configOTP_CACHED_RAM_SIZE
#endif
/**
* \brief Retained-RAM-0-block size in cached mode for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RETRAM_0_SIZE_BB
#define dg_configOTP_CACHED_RETRAM_0_SIZE_BB dg_configOTP_CACHED_RETRAM_0_SIZE
#endif
/**
* \brief Retained-RAM-1-block size in cached mode for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_CACHED_RETRAM_1_SIZE_BB
#define dg_configOTP_CACHED_RETRAM_1_SIZE_BB dg_configOTP_CACHED_RETRAM_1_SIZE
#endif
/**
* \brief RAM-block size in mirror mode for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_MIRROR_RAM_SIZE_AE
#define dg_configOTP_MIRROR_RAM_SIZE_AE dg_configOTP_MIRROR_RAM_SIZE
#endif
/**
* \brief Retained-RAM-1-block size in mirror mode for DA14680/1-01
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE_AE
#define dg_configOTP_MIRROR_RETRAM_1_SIZE_AE dg_configOTP_MIRROR_RETRAM_1_SIZE
#endif
/**
* \brief RAM-block size in mirror mode for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_MIRROR_RAM_SIZE_BB
#define dg_configOTP_MIRROR_RAM_SIZE_BB dg_configOTP_MIRROR_RAM_SIZE
#endif
/**
* \brief Retained-RAM-0-block size in mirror mode for DA14682/3-00, DA15XXX-00
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_MIRROR_RETRAM_0_SIZE_BB
#define dg_configOTP_MIRROR_RETRAM_0_SIZE_BB dg_configOTP_MIRROR_RETRAM_0_SIZE
#endif
/**
* \brief Retained-RAM-0-block size in mirror mode for DA14682/3-00, DA15XXX-00
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configOTP_MIRROR_RETRAM_1_SIZE_BB
#define dg_configOTP_MIRROR_RETRAM_1_SIZE_BB dg_configOTP_MIRROR_RETRAM_1_SIZE
#endif
/* ---------------------------------------------------------------------------------------------- */
/**
* \}
*/
/**
* \addtogroup QSPI_PROJECT_MEMORY_LAYOUT_SETTINGS
*
* \brief Memory layout configuration settings for a QSPI project
* \{
*/
/**
* \brief Code size in QSPI projects, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CODE_SIZE
#define dg_configQSPI_CODE_SIZE (128 * 1024)
#endif
/**
* \brief RAM-block size in cached mode, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RAM_SIZE
#define dg_configQSPI_CACHED_RAM_SIZE ( 64 * 1024)
#endif
/**
* \brief Retained-RAM-0-block size in cached mode, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE
#define dg_configQSPI_CACHED_RETRAM_0_SIZE ( 64 * 1024)
#endif
/**
* \brief Retained-RAM-1-block size in cached mode, no product specific.
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE
#define dg_configQSPI_CACHED_RETRAM_1_SIZE ( 0 * 1024)
#endif
/**
* \brief Retained-RAM-0-block size for optimal retention memory in cached mode, no product specific.
*
* \see dg_configOPTIMAL_RETRAM option
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE
#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE ( 32 * 1024)
#endif
/**
* \brief Retained-RAM-1-block size for optimal retention memory in cached mode, no product specific.
*
* \see dg_configOPTIMAL_RETRAM option
*
* \note Defining the corresponding product-specific configuration macro will override
* this one.
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE
#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE ( 32 * 1024)
#endif
/**
* \brief Code size in QSPI projects for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CODE_SIZE_AE
#define dg_configQSPI_CODE_SIZE_AE dg_configQSPI_CODE_SIZE
#endif
/**
* \brief Code size in QSPI projects for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CODE_SIZE_BB
#define dg_configQSPI_CODE_SIZE_BB dg_configQSPI_CODE_SIZE
#endif
/**
* \brief RAM-block size in cached mode for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RAM_SIZE_AE
#define dg_configQSPI_CACHED_RAM_SIZE_AE dg_configQSPI_CACHED_RAM_SIZE
#endif
/**
* \brief Retained-RAM-0-block size in cached mode for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE_AE
#define dg_configQSPI_CACHED_RETRAM_0_SIZE_AE dg_configQSPI_CACHED_RETRAM_0_SIZE
#endif
/**
* \brief Retained-RAM-1-block size in cached mode for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE_AE
#define dg_configQSPI_CACHED_RETRAM_1_SIZE_AE dg_configQSPI_CACHED_RETRAM_1_SIZE
#endif
/**
* \brief Retained-RAM-0-block size for optimal retention memory in cached mode for DA14680/1-01.
*
* \see dg_configOPTIMAL_RETRAM option
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE_AE
#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE_AE dg_configQSPI_CACHED_OPTIMAL_RETRAM_0_SIZE
#endif
/**
* \brief Retained-RAM-1-block size for optimal retention memory in cached mode for DA14680/1-01.
*
* \see dg_configOPTIMAL_RETRAM option
*
* \bsp_default_note{\bsp_config_option_app, \bsp_config_option_expert_only}
*/
#ifndef dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE_AE
#define dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE_AE dg_configQSPI_CACHED_OPTIMAL_RETRAM_1_SIZE
#endif
/**
* \brief RAM-block size in cached mode for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RAM_SIZE_BB
#define dg_configQSPI_CACHED_RAM_SIZE_BB dg_configQSPI_CACHED_RAM_SIZE
#endif
/**
* \brief Retained-RAM-0-block size in cached mode for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RETRAM_0_SIZE_BB
#define dg_configQSPI_CACHED_RETRAM_0_SIZE_BB dg_configQSPI_CACHED_RETRAM_0_SIZE
#endif
/**
* \brief Retained-RAM-1-block size in cached mode for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configQSPI_CACHED_RETRAM_1_SIZE_BB
#define dg_configQSPI_CACHED_RETRAM_1_SIZE_BB dg_configQSPI_CACHED_RETRAM_1_SIZE
#endif
/* ---------------------------------------------------------------------------------------------- */
/**
* \}
*/
/**
* \addtogroup RAM_PROJECT_MEMORY_LAYOUT_SETTINGS
*
* \brief Memory layout configuration settings for a RAM project
* \{
*/
/**
* \brief Code size in RAM projects for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configRAM_CODE_SIZE_AE
#define dg_configRAM_CODE_SIZE_AE ( 79 * 1024)
#endif
/**
* \brief RAM-block size for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configRAM_RAM_SIZE_AE
#define dg_configRAM_RAM_SIZE_AE ( 16 * 1024)
#endif
/**
* \brief Retained-RAM-0-block size for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configRAM_RETRAM_0_SIZE_AE
#define dg_configRAM_RETRAM_0_SIZE_AE (128 * 1024 - dg_configRAM_CODE_SIZE_AE)
#endif
/**
* \brief Retained-RAM-1-block size for DA14680/1-01.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configRAM_RETRAM_1_SIZE_AE
#define dg_configRAM_RETRAM_1_SIZE_AE ( 0 * 1024)
#endif
/**
* \brief Code size in RAM projects for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configRAM_CODE_SIZE_BB
#define dg_configRAM_CODE_SIZE_BB (144 * 1024)
#endif
/**
* \brief RAM-block size for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configRAM_RAM_SIZE_BB
#define dg_configRAM_RAM_SIZE_BB ( 15 * 1024)
#endif
/**
* \brief Retained-RAM-0-block size for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configRAM_RETRAM_0_SIZE_BB
#define dg_configRAM_RETRAM_0_SIZE_BB ( 49 * 1024)
#endif
/**
* \brief Retained-RAM-0-block size for DA14682/3-00, DA15XXX-00.
*
* \bsp_default_note{\bsp_config_option_app,}
*/
#ifndef dg_configRAM_RETRAM_1_SIZE_BB
#define dg_configRAM_RETRAM_1_SIZE_BB ( 0 * 1024)
#endif
/* ---------------------------------------------------------------------------------------------- */
/**
* \}
*/
/* ---------------------------------------------------------------------------------------------- */
/**
* \}
*/
/**
* \}
*/
#endif /* BSP_DEFAULTS_H_ */
third_party/dialog/DialogSDK/bsp/config/bsp_definitions.h
Vendored
+1 -1
View File
@@ -126,7 +126,7 @@
#define BLACK_ORCA_MB_REV_D 2
/*
* The cache associtivity options.
* The cache associativity options.
*/
#define CACHE_ASSOC_AS_IS (-1) /// leave as set by the ROM booter
#define CACHE_ASSOC_DIRECT_MAP 0 /// direct-mapped
third_party/dialog/DialogSDK/bsp/config/bsp_fem.h
Vendored
+1 -1
View File
@@ -43,7 +43,7 @@
*
*
***************************************************************************************
*/
*/
#ifndef BSP_FEM_H_
#define BSP_FEM_H_
third_party/dialog/DialogSDK/bsp/include/DA14680BA.h → third_party/dialog/DialogSDK/bsp/include/DA14680BB.h
Vendored Regular → Executable
+55 -26
View File
@@ -1,4 +1,6 @@
/*
/**
****************************************************************************************
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
@@ -23,13 +25,18 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* @file DA14680BA.h
* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for DA14680BA from Dialog.
* @file DA14680BB.h
*
* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
* DA14680BB from Dialog.
*
* @version V1.2
* @date 9. August 2016
* @note Generated with SVDConv V2.87g
* from CMSIS SVD File 'DA14680BA.xml'
* Version 1.2
* @date 14. June 2017
*
* @note Generated with SVDConv V2.87l
* from CMSIS SVD File 'DA14680BB.xml' Version 1.2,
*
*****************************************************************************************
*/
@@ -38,13 +45,12 @@
* @{
*/
/** @addtogroup DA14680BA
/** @addtogroup DA14680BB
* @{
*/
#ifndef DA14680BA_H
#define DA14680BA_H
#ifndef DA14680BB_H
#define DA14680BB_H
#ifdef __cplusplus
extern "C" {
@@ -65,7 +71,7 @@ typedef enum {
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
/* -------------------- DA14680BA Specific Interrupt Numbers -------------------- */
/* -------------------- DA14680BB Specific Interrupt Numbers -------------------- */
BLE_WAKEUP_LP_IRQn = 0, /*!< 0 BLE_WAKEUP_LP */
BLE_GEN_IRQn = 1, /*!< 1 BLE_GEN */
FTDF_WAKEUP_IRQn = 2, /*!< 2 FTDF_WAKEUP */
@@ -101,7 +107,7 @@ typedef enum {
} IRQn_Type;
/** @addtogroup Configuration_of_CMSIS_DA14680BA
/** @addtogroup Configuration_of_CMSIS_DA14680BB
* @{
*/
@@ -118,7 +124,7 @@ typedef enum {
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
#include "system_DA14680.h" /*!< DA14680BA System */
#include "system_DA14680.h" /*!< DA14680BB System */
/* ================================================================================ */
@@ -126,7 +132,7 @@ typedef enum {
/* ================================================================================ */
/** @addtogroup Device_Peripheral_Registers_DA14680BA
/** @addtogroup Device_Peripheral_Registers_DA14680BB
* @{
*/
@@ -469,7 +475,7 @@ typedef struct { /*!< (@ 0x50000000) CRG_TOP
__I uint32_t RESERVED2[2];
__IO uint16_t CLK_32K_REG; /*!< (@ 0x50000020) 32 kHz oscillator register */
__IO uint16_t CLK_16M_REG; /*!< (@ 0x50000022) 16 MHz RC and xtal oscillator register */
__IO uint16_t CLK_RCX20K_REG; /*!< (@ 0x50000024) 20KHz RXC-oscillator control register */
__IO uint16_t CLK_RCX20K_REG; /*!< (@ 0x50000024) RCX-oscillator control register */
__I uint16_t RESERVED3;
__IO uint16_t BANDGAP_REG; /*!< (@ 0x50000028) bandgap trimming */
__IO uint16_t ANA_STATUS_REG; /*!< (@ 0x5000002A) status bit of analog (power management) circuits */
@@ -490,7 +496,7 @@ typedef struct { /*!< (@ 0x50000000) CRG_TOP
__IO uint16_t XTALRDY_STAT_REG; /*!< (@ 0x50000052) Difference between XTAL_OK and XTALRDY_IRQ in
LP clock cycles */
__IO uint16_t LDO_CTRL3_REG; /*!< (@ 0x50000054) Retention LDO control register */
__I uint16_t RESERVED6;
__IO uint16_t XTAL16M_CTRL_REG; /*!< (@ 0x50000056) Control register for XTAL16M */
__IO uint16_t XTAL16M_START_REG; /*!< (@ 0x50000058) Xtal frequency trimming register during startup */
__IO uint16_t XTAL16M_RAMP_REG; /*!< (@ 0x5000005A) Xtal frequency trimming register during ramping */
__IO uint16_t XTAL16M_TRSTAT_REG; /*!< (@ 0x5000005C) Read back value of current XTAL trimming */
@@ -1901,11 +1907,13 @@ typedef struct { /*!< (@ 0x50005000) TRNG Str
*/
typedef struct { /*!< (@ 0x50001000) UART Structure */
__IO uint16_t UART_RBR_THR_DLL_REG; /*!< (@ 0x50001000) Receive Buffer Register */
__IO uint16_t UART_RBR_THR_DLL_REG; /*!< (@ 0x50001000) Receive Buffer Register/Transmit Holding Register/Divisor
Latch Low */
__I uint16_t RESERVED;
__IO uint16_t UART_IER_DLH_REG; /*!< (@ 0x50001004) Interrupt Enable Register */
__IO uint16_t UART_IER_DLH_REG; /*!< (@ 0x50001004) Interrupt Enable Register/Divisor Latch High */
__I uint16_t RESERVED1;
__IO uint16_t UART_IIR_FCR_REG; /*!< (@ 0x50001008) Interrupt Identification Register */
__IO uint16_t UART_IIR_FCR_REG; /*!< (@ 0x50001008) Interrupt Identification Register/FIFO Control
Register */
__I uint16_t RESERVED2;
__IO uint16_t UART_LCR_REG; /*!< (@ 0x5000100C) Line Control Register */
__I uint16_t RESERVED3;
@@ -1943,9 +1951,10 @@ typedef struct { /*!< (@ 0x50001000) UART Str
*/
typedef struct { /*!< (@ 0x50001100) UART2 Structure */
__IO uint16_t UART2_RBR_THR_DLL_REG; /*!< (@ 0x50001100) Receive Buffer Register */
__IO uint16_t UART2_RBR_THR_DLL_REG; /*!< (@ 0x50001100) Receive Buffer Register/Transmit Holding Register/Divisor
Latch Low */
__I uint16_t RESERVED;
__IO uint16_t UART2_IER_DLH_REG; /*!< (@ 0x50001104) Interrupt Enable Register */
__IO uint16_t UART2_IER_DLH_REG; /*!< (@ 0x50001104) Interrupt Enable Register/Divisor Latch High */
__I uint16_t RESERVED1;
__IO uint16_t UART2_IIR_FCR_REG; /*!< (@ 0x50001108) Interrupt Identification Register/FIFO Control
Register */
@@ -1994,11 +2003,11 @@ typedef struct { /*!< (@ 0x50001100) UART2 St
__I uint16_t RESERVED23;
__IO uint16_t UART2_FAR_REG; /*!< (@ 0x50001170) FIFO Access Register */
__I uint16_t RESERVED24[5];
__IO uint16_t UART2_USR_REG; /*!< (@ 0x5000117C) UART Status register. */
__IO uint16_t UART2_USR_REG; /*!< (@ 0x5000117C) UART Status Register */
__I uint16_t RESERVED25;
__IO uint16_t UART2_TFL_REG; /*!< (@ 0x50001180) Transmit FIFO Level */
__I uint16_t RESERVED26;
__IO uint16_t UART2_RFL_REG; /*!< (@ 0x50001184) Receive FIFO Level. */
__IO uint16_t UART2_RFL_REG; /*!< (@ 0x50001184) Receive FIFO Level */
__I uint16_t RESERVED27;
__IO uint16_t UART2_SRR_REG; /*!< (@ 0x50001188) Software Reset Register. */
__I uint16_t RESERVED28;
@@ -4329,6 +4338,18 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Pos (5UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bit 5) */
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Msk (0x20UL) /*!< CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bitfield-Mask: 0x01) */
/* -------------------------- CRG_TOP_XTAL16M_CTRL_REG -------------------------- */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_FREQ_TRIM_SW2_AMP_Pos (0UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_FREQ_TRIM_SW2_AMP (Bit 0) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_FREQ_TRIM_SW2_AMP_Msk (0x7UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_FREQ_TRIM_SW2_AMP (Bitfield-Mask: 0x07) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_AMP_REG_SIG_SEL_Pos (3UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_AMP_REG_SIG_SEL (Bit 3) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_AMP_REG_SIG_SEL_Msk (0x8UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_AMP_REG_SIG_SEL (Bitfield-Mask: 0x01) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_TST_AON_Pos (4UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_TST_AON (Bit 4) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_TST_AON_Msk (0x30UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_TST_AON (Bitfield-Mask: 0x03) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_SH_OVERRULE_Pos (6UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_SH_OVERRULE (Bit 6) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_SH_OVERRULE_Msk (0xc0UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_SH_OVERRULE (Bitfield-Mask: 0x03) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_ENABLE_ZERO_Pos (8UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_ENABLE_ZERO (Bit 8) */
#define CRG_TOP_XTAL16M_CTRL_REG_XTAL16M_ENABLE_ZERO_Msk (0x100UL) /*!< CRG_TOP XTAL16M_CTRL_REG: XTAL16M_ENABLE_ZERO (Bitfield-Mask: 0x01) */
/* -------------------------- CRG_TOP_XTAL16M_START_REG ------------------------- */
#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Pos (0UL) /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bit 0) */
#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Msk (0xffUL) /*!< CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bitfield-Mask: 0xff) */
@@ -11048,6 +11069,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str
#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Msk (0x2UL) /*!< UART UART_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01) */
#define UART_UART_IER_DLH_REG_ELSI_dhl2_Pos (2UL) /*!< UART UART_IER_DLH_REG: ELSI_dhl2 (Bit 2) */
#define UART_UART_IER_DLH_REG_ELSI_dhl2_Msk (0x4UL) /*!< UART UART_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01) */
#define UART_UART_IER_DLH_REG_EDSSI_dlh3_Pos (3UL) /*!< UART UART_IER_DLH_REG: EDSSI_dlh3 (Bit 3) */
#define UART_UART_IER_DLH_REG_EDSSI_dlh3_Msk (0x8UL) /*!< UART UART_IER_DLH_REG: EDSSI_dlh3 (Bitfield-Mask: 0x01) */
#define UART_UART_IER_DLH_REG_dlh6_4_Pos (4UL) /*!< UART UART_IER_DLH_REG: dlh6_4 (Bit 4) */
#define UART_UART_IER_DLH_REG_dlh6_4_Msk (0x70UL) /*!< UART UART_IER_DLH_REG: dlh6_4 (Bitfield-Mask: 0x07) */
#define UART_UART_IER_DLH_REG_PTIME_dlh7_Pos (7UL) /*!< UART UART_IER_DLH_REG: PTIME_dlh7 (Bit 7) */
#define UART_UART_IER_DLH_REG_PTIME_dlh7_Msk (0x80UL) /*!< UART UART_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01) */
@@ -11148,6 +11173,10 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str
#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Msk (0x2UL) /*!< UART2 UART2_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01) */
#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Pos (2UL) /*!< UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bit 2) */
#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Msk (0x4UL) /*!< UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01) */
#define UART2_UART2_IER_DLH_REG_EDSSI_dlh3_Pos (3UL) /*!< UART2 UART2_IER_DLH_REG: EDSSI_dlh3 (Bit 3) */
#define UART2_UART2_IER_DLH_REG_EDSSI_dlh3_Msk (0x8UL) /*!< UART2 UART2_IER_DLH_REG: EDSSI_dlh3 (Bitfield-Mask: 0x01) */
#define UART2_UART2_IER_DLH_REG_dlh6_4_Pos (4UL) /*!< UART2 UART2_IER_DLH_REG: dlh6_4 (Bit 4) */
#define UART2_UART2_IER_DLH_REG_dlh6_4_Msk (0x70UL) /*!< UART2 UART2_IER_DLH_REG: dlh6_4 (Bitfield-Mask: 0x07) */
#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Pos (7UL) /*!< UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bit 7) */
#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Msk (0x80UL) /*!< UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01) */
@@ -12112,7 +12141,7 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group DA14680BA */
/** @} */ /* End of group DA14680BB */
/** @} */ /* End of group Dialog */
#ifdef __cplusplus
@@ -12120,5 +12149,5 @@ typedef struct { /*!< (@ 0x50003100) WDOG Str
#endif
#endif /* DA14680BA_H */
#endif /* DA14680BB_H */
third_party/dialog/DialogSDK/bsp/include/sdk_defs.h
Vendored
+42 -7
View File
@@ -78,8 +78,8 @@
# error "Unknown chip stepping for revision A -- check the value of dg_configBLACK_ORCA_IC_STEP"
# endif
#elif dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B
# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_A
# include "DA14680BA.h"
# if dg_configBLACK_ORCA_IC_STEP == BLACK_ORCA_IC_STEP_B
# include "DA14680BB.h"
# else
# error "Unknown chip stepping for revision B -- check the value of dg_configBLACK_ORCA_IC_STEP"
# endif
@@ -287,7 +287,7 @@
extern uint32_t black_orca_chip_version;
#define CHIP_IS_AE (black_orca_chip_version == BLACK_ORCA_IC_VERSION(A, E))
#define CHIP_IS_BA (black_orca_chip_version == BLACK_ORCA_IC_VERSION(B, A))
#define CHIP_IS_BB (black_orca_chip_version == BLACK_ORCA_IC_VERSION(B, B))
/**
* \brief Get the chip version of the system, at runtime.
@@ -310,8 +310,8 @@ __RETAINED_CODE void hw_cpm_assert_trigger_gpio(void);
*/
#define ASSERT_WARNING(a) \
{ \
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \
if (!(a)) { \
if (!(a)) { \
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \
__asm volatile ( " cpsid i " ); \
GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \
hw_cpm_assert_trigger_gpio(); \
@@ -349,8 +349,8 @@ __RETAINED_CODE void hw_cpm_assert_trigger_gpio(void);
*/
#define ASSERT_WARNING_UNINIT(a) \
{ \
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \
if (!(a)) { \
if (!(a)) { \
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) { \
__asm volatile ( " cpsid i " ); \
GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk; \
do {} while(1); \
@@ -583,6 +583,41 @@ void __aeabi_memset(void *dest, size_t n, int c);
#define REG_CLR_FIELD(base, reg, field, var) \
var &= ~(base ## _ ## reg ## _ ## field ## _Msk)
/**
* \brief Get the address of a register value by index (provided a register interval)
*
* \note The register interval should be an exact multiple of the register's base size. For example,
* if the register size is 32-bit, then the interval should be 0x4, 0x8, etc. Otherwise, the result
* will be undefined. The interval value must be in bytes. The index value (0,1,2...) is multiplied by
* the interval value (in bytes) to find the actual offset of the register.
*
* Returns a register address value by index
*/
#define REG_GET_ADDR_INDEXED(base, reg, interval, index) \
((&base->reg) + (((intptr_t) index) * ((interval) / sizeof(base->reg))))
/**
* \brief Return the value of a register field by index (provided a register interval).
*
* e.g.
* \code
* uint16_t val;
* uint16_t index = 2
*
* val = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, REG_EXP_SA_L, 0x10, index)
*
* ...
* \endcode
*
* \note The register interval should be an exact multiple of the register's base size. For example,
* if the register size is 32-bit, then the interval should be 0x4, 0x8, etc. Otherwise, the result
* will be undefined. The interval value must be in bytes. The index value (0,1,2...) is multiplied by
* the interval value (in bytes) to find the actual offset of the register.
*
*/
#define REG_GETF_INDEXED(base, reg, field, interval, index) \
(((*REG_GET_ADDR_INDEXED(base, reg, interval, index)) & \
(base ## _ ## reg ## _ ## field ## _Msk)) >> (base ## _ ## reg ## _ ## field ## _Pos))
/**
* \brief Return the value of a register field.
third_party/dialog/DialogSDK/bsp/ldfile/da15000.ld
Vendored
+27 -24
View File
@@ -1,29 +1,32 @@
/*
* Copyright (c) 2016, The OpenThread Authors.
* All rights reserved.
/**
****************************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
MEMORY
third_party/dialog/DialogSDK/bsp/memory/include/qspi_automode.h
Vendored
+2 -14
View File
@@ -15,14 +15,6 @@
*
* @brief Access QSPI flash when running in auto mode
*
* The QSPI controller allows to execute code directly from QSPI flash.
* When code is executing from flash, it is not possible to reprogram the flash.
* To be able to modify the flash when it is used for code execution, it must me assured that
* for the time needed to erase/write, no code is running from flash.
* To achieve this, the code in this module is executed from the RAM.
* Code in this module will not access any other functions or constant variables that could reside
* in flash.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
@@ -70,15 +62,11 @@
#define __DBG_QSPI_VOLATILE__
#endif
/*
* Defines (generic)
*/
/* Macros to put functions that need to be copied to ram in one section (retained) */
#define QSPI_SECTION __attribute__((section ("text_retained"), optimize ("no-tree-switch-conversion")))
#define QSPI_SECTION_NO_INLINE __attribute__ ((section ("text_retained"))) __attribute__ ((noinline))
typedef struct qspi_ucode_s {
const uint32_t *code;
uint8_t size;
@@ -182,12 +170,12 @@ static inline const void *qspi_automode_addr(uint32_t addr)
/**
* \brief Power up flash
*/
QSPI_SECTION void qspi_automode_flash_power_up(void);
__RETAINED_CODE void qspi_automode_flash_power_up(void);
/**
* \brief Set QSPI Flash into power down mode
*/
QSPI_SECTION void qspi_automode_flash_power_down(void);
__RETAINED_CODE void qspi_automode_flash_power_down(void);
/**
* \brief Init QSPI controller
third_party/dialog/DialogSDK/bsp/memory/include/qspi_common.h
Vendored
+3 -2
View File
@@ -43,6 +43,7 @@
*
****************************************************************************************
*/
#ifndef _QSPI_COMMON_H_
#define _QSPI_COMMON_H_
@@ -162,8 +163,8 @@ static uint8_t flash_read_status_register(void);
static void flash_write_status_register(uint8_t value);
static void flash_write_enable(void);
static void qspi_automode_set_dummy_bytes_count(uint8_t count);
static bool flash_is_busy(void);
static inline bool flash_erase_program_in_progress(void);
static inline bool flash_erase_program_in_progress(void) __attribute__((always_inline));
static inline bool flash_is_busy(void) __attribute__((always_inline));
#endif /* _QSPI_COMMON_H_ */
/**
third_party/dialog/DialogSDK/bsp/memory/include/qspi_w25q80ew.h
Vendored
+3 -2
View File
@@ -41,6 +41,7 @@
*
****************************************************************************************
*/
#ifndef _QSPI_W32Q80EW_H_
#define _QSPI_W32Q80EW_H_
@@ -95,12 +96,12 @@ static const qspi_flash_config_t flash_w25q80ew_config = {
const qspi_flash_config_t* const flash_config = &flash_w25q80ew_config;
#endif
QSPI_SECTION static void flash_w25q80ew_sys_clock_cfg(sys_clk_t sys_clk)
__RETAINED_CODE static void flash_w25q80ew_sys_clock_cfg(sys_clk_t sys_clk)
{
}
QSPI_SECTION static uint8_t flash_w25q80ew_get_dummy_bytes(void)
__RETAINED_CODE static uint8_t flash_w25q80ew_get_dummy_bytes(void)
{
return 2;
}
third_party/dialog/DialogSDK/bsp/memory/include/qspi_winbond.h
Vendored
+12 -7
View File
@@ -42,6 +42,7 @@
*
****************************************************************************************
*/
#ifndef _QSPI_WINBOND_H_
#define _QSPI_WINBOND_H_
@@ -155,7 +156,8 @@ static void flash_w25q_deactivate_command_entry_mode(void);
*
* \note This function blocks until the Flash has processed the command.
*/
QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_wre_volatile(void)
static inline void flash_w25q_wre_volatile(void) __attribute__((always_inline)) __attribute__((unused));
static inline void flash_w25q_wre_volatile(void)
{
uint8_t cmd[] = { W25Q_WRITE_ENABLE_NON_VOL };
@@ -165,7 +167,8 @@ QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_wre_volatile(
while (flash_is_busy());
}
QSPI_SECTION __attribute__((unused)) static inline uint8_t flash_w25q_read_status_register_2(void)
static inline uint8_t flash_w25q_read_status_register_2(void) __attribute__((always_inline));
static inline uint8_t flash_w25q_read_status_register_2(void)
{
__DBG_QSPI_VOLATILE__ uint8_t status;
uint8_t cmd[] = { W25Q_READ_STATUS_REGISTER2 };
@@ -184,7 +187,8 @@ QSPI_SECTION __attribute__((unused)) static inline uint8_t flash_w25q_read_statu
* value has been actually written is done though. It is up to the caller to decide whether
* such verification is needed or not and execute it on its own.
*/
QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_write_status_register_2(uint8_t value)
static inline void flash_w25q_write_status_register_2(uint8_t value) __attribute__((always_inline));
static inline void flash_w25q_write_status_register_2(uint8_t value)
{
uint8_t cmd[] = { W25Q_WRITE_STATUS_REGISTER2, value };
@@ -194,7 +198,8 @@ QSPI_SECTION __attribute__((unused)) static inline void flash_w25q_write_status_
while (flash_is_busy());
}
QSPI_SECTION static inline void flash_w25q_enable_quad_mode(void)
static inline void flash_w25q_enable_quad_mode(void) __attribute__((always_inline));
static inline void flash_w25q_enable_quad_mode(void)
{
uint8_t status;
@@ -205,7 +210,7 @@ QSPI_SECTION static inline void flash_w25q_enable_quad_mode(void)
}
}
QSPI_SECTION static bool flash_w25q_is_suspended(void)
__RETAINED_CODE static bool flash_w25q_is_suspended(void)
{
__DBG_QSPI_VOLATILE__ uint8_t status;
@@ -213,7 +218,7 @@ QSPI_SECTION static bool flash_w25q_is_suspended(void)
return (status & W25Q_STATUS2_SUS_MASK) != 0;
}
QSPI_SECTION static void flash_w25q_initialize(uint8_t device_type, uint8_t device_density)
__RETAINED_CODE static void flash_w25q_initialize(uint8_t device_type, uint8_t device_density)
{
flash_activate_command_entry_mode();
@@ -222,7 +227,7 @@ QSPI_SECTION static void flash_w25q_initialize(uint8_t device_type, uint8_t devi
flash_deactivate_command_entry_mode();
}
QSPI_SECTION static void flash_w25q_deactivate_command_entry_mode(void)
__RETAINED_CODE static void flash_w25q_deactivate_command_entry_mode(void)
{
}
third_party/dialog/DialogSDK/bsp/memory/src/qspi_automode.c
Vendored
+578 -619
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/bsp/osal/osal.h
Vendored
+95
View File
@@ -0,0 +1,95 @@
/**
* \addtogroup BSP
* \{
* \addtogroup OSAL
*
* \brief OS Abstraction Layer
*
* \{
*/
/**
****************************************************************************************
*
* @file osal.h
*
* @brief OS abstraction layer API
*
* @brief Access QSPI flash when running in auto mode
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
#ifndef OSAL_H_
#define OSAL_H_
#if defined OS_BAREMETAL
#include <sdk_defs.h>
/*
* Basic set of macros that can be used in non OS environment.
*/
# define PRIVILEGED_DATA
# define OS_MALLOC malloc
# define OS_FREE free
# ifndef RELEASE_BUILD
# define OS_ASSERT(a) do { if (!(a)) {__BKPT(0);} } while (0)
# else
# define OS_ASSERT(a) ((void) (a))
# endif
#endif
/**
* \brief Cast any pointer to unsigned int value
*/
#define OS_PTR_TO_UINT(p) ((unsigned) (void *) (p))
/**
* \brief Cast any pointer to signed int value
*/
#define OS_PTR_TO_INT(p) ((int) (void *) (p))
/**
* \brief Cast any unsigned int value to pointer
*/
#define OS_UINT_TO_PTR(u) ((void *) (unsigned) (u))
/**
* \brief Cast any signed int value to pointer
*/
#define OS_INT_TO_PTR(i) ((void *) (int) (i))
#endif /* OSAL_H_ */
/**
* \}
* \}
* \}
*/
third_party/dialog/DialogSDK/bsp/peripherals/include/hw_aes_hash.h
Vendored
+34 -35
View File
@@ -9,39 +9,39 @@
*/
/**
****************************************************************************************
*
* @file hw_cpm.c
*
* @brief Clock and Power Manager Driver
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
****************************************************************************************
*
* @file hw_aes_hash.h
*
* @brief Definition of API for the AES/HASH Engine Low Level Driver.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
#ifndef HW_AES_HASH_H_
#define HW_AES_HASH_H_
@@ -49,8 +49,7 @@
#if dg_configUSE_HW_AES_HASH
#include <stdbool.h>
#include <stdint.h>
#include <sdk_defs.h>
#include "sdk_defs.h"
/**
* \brief AES/Hash callback
third_party/dialog/DialogSDK/bsp/peripherals/include/hw_cpm.h
Vendored
+44 -9
View File
@@ -9,7 +9,7 @@
*/
/**
****************************************************************************************
****************************************************************************************
*
* @file hw_cpm.h
*
@@ -40,8 +40,8 @@
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
****************************************************************************************
*/
#ifndef CPM_H_
#define CPM_H_
@@ -50,15 +50,49 @@
#include "sdk_defs.h"
#define SYS_CLK_IS_XTAL16M (0)
#define SYS_CLK_IS_RC16 (1)
#define SYS_CLK_IS_LP (2)
#define SYS_CLK_IS_PLL (3)
/**
* \addtogroup CLOCK_TYPES
* \brief Clock types
* \note These macros must only be used with hw_cpm_set_sysclk().
* \{
*/
/**
* \brief System crystal oscillator 16 MHz
*/
#define SYS_CLK_IS_XTAL16M (0)
/**
* \brief System RC oscillator 16 MHz
*/
#define SYS_CLK_IS_RC16 (1)
/**
* \brief System Low Power clock
*/
#define SYS_CLK_IS_LP (2)
/**
* \brief System PLL
*/
#define SYS_CLK_IS_PLL (3)
/**
* \brief Low Power RC oscillator 32 kHz
*/
#define LP_CLK_IS_RC32K (0)
/**
* \brief Low Power RC oscillator 11.7 kHz
*/
#define LP_CLK_IS_RCX (1)
/**
* \brief Low Power crystal oscillator 32 kHz
*/
#define LP_CLK_IS_XTAL32K (2)
/**
* \brief Low Power external clock
*/
#define LP_CLK_IS_EXTERNAL (3)
/**
* \}
*/
#define DCDC_IS_READY \
(REG_MSK(DCDC, DCDC_STATUS_1_REG, DCDC_VDD_AVAILABLE))
@@ -75,6 +109,7 @@ typedef enum cal_clk_cel_type {
/**
* \brief The system clock type
* \note Must only be used with functions cm_sys_clk_init/set()
*
*/
typedef enum sysclk_type {
@@ -282,7 +317,7 @@ __STATIC_INLINE void hw_cpm_deactivate_bod_protection(void)
}
/**
* \brief Activate BOD protection for 1V4 rail (only for DA14682/3-BA chips!).
* \brief Activate BOD protection for 1V4 rail (only for DA14682/3-00, DA15XXX-00 chips!).
*
*/
__STATIC_INLINE void hw_cpm_activate_1v4_bod_protection(void) __attribute__((always_inline));
@@ -295,7 +330,7 @@ __STATIC_INLINE void hw_cpm_activate_1v4_bod_protection(void)
}
/**
* \brief Deactivate BOD protection for 1V4 rail (only for DA14682/3-BA chips!).
* \brief Deactivate BOD protection for 1V4 rail (only for DA14682/3-00, DA15XXX-00 chips!).
*
*/
__STATIC_INLINE void hw_cpm_deactivate_1v4_bod_protection(void) __attribute__((always_inline));
third_party/dialog/DialogSDK/bsp/peripherals/include/hw_crypto.h
Vendored
+35 -35
View File
@@ -9,43 +9,43 @@
*/
/**
****************************************************************************************
*
* @file hw_cpm.c
*
* @brief Clock and Power Manager Driver
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
****************************************************************************************
*
* @file hw_crypto.h
*
* @brief Interrupt handling API for the AES/Hash and ECC Engines.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
#if (dg_configUSE_HW_AES_HASH || dg_configUSE_HW_ECC)
#include <sdk_defs.h>
#include "sdk_defs.h"
/**
* \brief Crypto engines callback
@@ -65,7 +65,7 @@ typedef void (*hw_crypto_cb)(unsigned int status);
*
* \note AES/HASH engine and ECC engine are common sources of CRYPTO system interrupt. This
* function only enables CRYPTO interrupt itself and registers a callback for AES/HASH
* related CRYPTO interrupts. In order to fully enable AES/HASH interrupts
* related CRYPTO interrupts. In order to fully enable AES/HASH interrupts
* hw_aes_hash_enable_interrupt_source() must also be called
*/
void hw_crypto_enable_aes_hash_interrupt(hw_crypto_cb cb);
third_party/dialog/DialogSDK/bsp/peripherals/include/hw_fem_sky66112-11.h
Vendored
-374
View File
@@ -1,374 +0,0 @@
/**
* \addtogroup BSP
* \{
* \addtogroup DEVICES
* \{
* \addtogroup FEM
* \{
* \brief Front End Module for SKYWORKS SKY66112-11
*/
/**
*****************************************************************************************
*
* @file
*
* @brief FEM Driver for SKYWORKS SKY66112-11 Low Level Driver API.
*
* GPIOs used for controlling the FEM are configured using the following macros, that should be placed
* in custom_config.h:
*
* CSD : dg_configFEM_SKY66112_11_CSD_PORT/PIN
* CPS : dg_configFEM_SKY66112_11_CPS_PORT/PIN
* CRX : dg_configFEM_SKY66112_11_CRX_PORT/PIN
* CTX : dg_configFEM_SKY66112_11_CTX_PORT/PIN
* CHL : dg_configFEM_SKY66112_11_CHL_PORT/PIN
* ANTSEL: dg_configFEM_SKY66112_11_ANTSEL_PORT/PIN
*
* In order to control an external PA, three GPIOs can be used. These are called RF_ANT_TRIMx, x=0,1,2. Each one of
* these bits is enabled if the corresponding PORT/PIN macros are set:
*
* RF_ANT_TRIM0 : dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT/PIN
* RF_ANT_TRIM1 : dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT/PIN
* RF_ANT_TRIM2 : dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT/PIN
*
* The actual GPIO values for RF_ANT_TRIMx are set by the corresponding MAC, whenever it gains access by the arbiter
* to the RF. This driver only handles the GPIO initialization.
*
* FEM BIAS Voltage control is enabled by the following macros:
*
* V18 : dg_configFEM_SKY66112_11_FEM_BIAS_V18
* V18P : dg_configFEM_SKY66112_11_FEM_BIAS_V18P
*
* If none of them is set, FEM BIAS will not be controlled by this driver.
*
***************************************************************************************
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*****************************************************************************************
*/
#ifndef HW_FEM_H_
#define HW_FEM_H_
#if dg_configFEM == FEM_SKY66112_11
#include <stdbool.h>
#if defined(dg_configFEM_SKY66112_11_FEM_BIAS_V18) && defined(dg_configFEM_SKY66112_11_FEM_BIAS_V18P)
#error Only one of dg_configFEM_SKY66112_11_FEM_BIAS_V18 and dg_configFEM_SKY66112_11_FEM_BIAS_V18P can be set at a time
#endif
/* Configuration/state structure (actually just a byte) */
typedef struct __attribute__ ((__packed__)) {
#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A
uint8_t tx_power: 1;
uint8_t tx_bypass: 1;
uint8_t rx_bypass: 1;
#else
uint8_t tx_power_ble: 1;
uint8_t tx_bypass_ble: 1;
uint8_t rx_bypass_ble: 1;
uint8_t tx_power_ftdf: 1;
uint8_t tx_bypass_ftdf: 1;
uint8_t rx_bypass_ftdf: 1;
#endif
uint8_t antsel: 1;
uint8_t started: 1;
} hw_fem_config;
#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A
/**
* \brief Configures FEM TX Power
*
* \param [in] high Set true to enable high TX power
*
*/
void hw_fem_set_txpower(bool high);
/**
* \brief Configures FEM TX bypass mode
*
* \param [in] enable false: Use PA, true: bypass
*
*/
void hw_fem_set_tx_bypass(bool enable);
/**
* \brief Configures FEM RX bypass mode
*
* \param [in] enable false: Use LNA, true: bypass
*
*/
void hw_fem_set_rx_bypass(bool enable);
/**
* \brief Gets the TX Power setting
*
* \return true, if TX Power is high, false if low
*
*/
bool hw_fem_get_txpower(void);
/**
* \brief Gets the TX bypass mode
*
* \return false: No TX bypass, true: TX bypass
*
*/
bool hw_fem_get_tx_bypass(void);
/**
* \brief Gets the RX bypass mode
*
* \return false: No RX bypass, true: RX bypass
*
*/
bool hw_fem_get_rx_bypass(void);
#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */
#ifdef CONFIG_USE_BLE
/**
* \brief Configures FEM TX Power for BLE
*
* \param [in] high Set true to enable high TX power
*
*/
void hw_fem_set_txpower_ble(bool high);
/**
* \brief Configures FEM TX bypass mode for BLE
*
* \param [in] enable false: Use PA, true: bypass
*
*/
void hw_fem_set_tx_bypass_ble(bool enable);
/**
* \brief Configures FEM RX bypass mode for BLE
*
* \param [in] enable false: Use LNA, true: bypass
*
*/
void hw_fem_set_rx_bypass_ble(bool enable);
/**
* \brief Gets the TX Power setting for BLE
*
* \return true, if TX Power is high, false if low
*
*/
bool hw_fem_get_txpower_ble(void);
/**
* \brief Gets the TX bypass mode for BLE
*
* \return false: No TX bypass, true: TX bypass
*
*/
bool hw_fem_get_tx_bypass_ble(void);
/**
* \brief Gets the RX bypass mode for BLE
*
* \return false: No RX bypass, true: RX bypass
*
*/
bool hw_fem_get_rx_bypass_ble(void);
#endif /* CONFIG_USE_BLE */
#ifdef CONFIG_USE_FTDF
/**
* \brief Configures FEM TX Power for FTDF
*
* \param [in] high Set true to enable high TX power
*
*/
void hw_fem_set_txpower_ftdf(bool high);
/**
* \brief Configures FEM TX bypass mode for FTDF
*
* \param [in] enable false: Use PA, true: bypass
*
*/
void hw_fem_set_tx_bypass_ftdf(bool enable);
/**
* \brief Configures FEM RX bypass mode for FTDF
*
* \param [in] enable false: Use LNA, true: bypass
*
*/
void hw_fem_set_rx_bypass_ftdf(bool enable);
/**
* \brief Gets the TX Power setting for FTDF
*
* \return true, if TX Power is high, false if low
*
*/
bool hw_fem_get_txpower_ftdf(void);
/**
* \brief Gets the TX bypass mode for FTDF
*
* \return false: No TX bypass, true: TX bypass
*
*/
bool hw_fem_get_tx_bypass_ftdf(void);
/**
* \brief Gets the RX bypass mode for FTDF
*
* \return false: No RX bypass, true: RX bypass
*
*/
bool hw_fem_get_rx_bypass_ftdf(void);
#endif /* CONFIG_USE_FTDF */
/**
* \brief Configures FEM TX Power
*
* \param [in] high Set true to enable high TX power
*
* \deprecated Use the BLE/FTDF specific functions instead
*/
void hw_fem_set_txpower(bool high) DEPRECATED;
/**
* \brief Configures FEM TX bypass mode
*
* \param [in] enable false: Use PA, true: bypass
*
* \deprecated Use the BLE/FTDF specific functions instead
*/
void hw_fem_set_tx_bypass(bool enable) DEPRECATED;
/**
* \brief Configures FEM RX bypass mode
*
* \param [in] enable false: Use LNA, true: bypass
*
* \deprecated Use the BLE/FTDF specific functions instead
*/
void hw_fem_set_rx_bypass(bool enable) DEPRECATED;
/**
* \brief Gets the TX Power setting
*
* \return true, if TX Power is high, false if low
*
* \deprecated Use the BLE/FTDF specific functions instead
*/
bool hw_fem_get_txpower(void) DEPRECATED;
/**
* \brief Gets the TX bypass mode
*
* \return false: No TX bypass, true: TX bypass
*
* \deprecated Use the BLE/FTDF specific functions instead
*/
bool hw_fem_get_tx_bypass(void) DEPRECATED;
/**
* \brief Gets the RX bypass mode
*
* \return false: No RX bypass, true: RX bypass
*
* \deprecated Use the BLE/FTDF specific functions instead
*/
bool hw_fem_get_rx_bypass(void) DEPRECATED;
#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */
/**
* \brief Configures FEM Antenna to use
*
* \param [in] one false: antenna 0, true: antenna 1
*
*/
void hw_fem_set_antenna(bool one);
/**
* \brief Gets the selected antenna
*
* \return false: antenna 1, true: antenna 2
*
*/
bool hw_fem_get_antenna(void);
/**
* \brief Sets the FEM Bias
*
* \param [in] voltage The voltage to set the FEM Bias to (mV)
*
* \return 0: success, -1: Out of range value entered, -2: FEM BIAS not supported on this board
*
*/
int hw_fem_set_bias(uint16_t voltage);
/**
* \brief Sets the 2nd FEM Bias
*
* \param [in] voltage The voltage to set the 2nd FEM Bias to (mV)
*
* \return 0: success, -1: Out of range value entered, -2: 2nd FEM BIAS not supported on this board
*
*/
int hw_fem_set_bias2(uint16_t voltage);
/**
* \brief Starts and configures FEM.
*
* Configures and sets GPIOs according to configuration set by hw_fem_set_config(). Also configures
* DCF Timers.
*
*
* \note To be called by the RF driver when RF is powered on
*
*/
void hw_fem_start(void);
/**
* \brief Stops FEM.
*
* Stops DCF timers and sets all FEM control signals to 0 to achieve the lowest possible power
*
* \note To be called by the RF driver when RF is powered off
*
*/
void hw_fem_stop(void);
#endif /* dg_configFEM == FEM_SKY66112_11 */
#endif /* HW_FEM_H_ */
/**
* \}
* \}
* \}
*/
third_party/dialog/DialogSDK/bsp/peripherals/include/hw_rf.h
Vendored
+14 -60
View File
@@ -15,66 +15,6 @@
*
* @brief Radio module (RF) Low Level Driver API.
*
* @note The following recalibration-related weak functions can be overridden, if needed,
* to provide additional functionality
*
* @note
* ~~~{.c}
* bool hw_rf_preoff_cb(void)
* ~~~
*
* @note Called before actually shutting down the RF PD. If this returns true, the PD
* will NOT be shutdown, but will stay on. This function can be used to decide
* whether an RF recalibration is needed and to start the respective operation.
* The default implementation (if an explicit implementation is omitted) returns
* false (i.e. the RF PD shuts off immediately).
*
* @note
* ~~~{.c}
* void hw_rf_postconf_cb(void)
* ~~~
*
* @note Called after the RF recommended settings are applied, or after the
* recalibration procedure is completed. Can be used to start/reset a
* recalibration timer, in case periodic recalibration is enabled using
* dg_configRF_RECALIBRATION_TIMER_TIMEOUT
*
* @note
* ~~~{.c}
* void hw_rf_precalib_cb(void)
* void hw_rf_postcalib_cb(void):
* ~~~
*
* @note Called when the re-calibration (not the initial calibration) procedure
* starts/ends. Can be used to instruct the system not to go to sleep during
* this time.
*
* @note
* ~~~{.c}
* void hw_rf_apply_tcs_cb(void)
* ~~~
*
* @note Called before applying the rf recommended settings. The implementation should
* apply the TCS values
*
* @note
* ~~~{.c}
* uint64_t hw_rf_get_start_iff_time(void)
* ~~~
*
* @note Called to get the time when IFF calibration starts
*
* @note
* ~~~{.c}
* bool hw_rf_check_iff_timeout(uint64_t start_time)
* ~~~
*
* @note Called to check if IFF calibration has timed-out (i.e. took too long). It takes argument the
* IFF calib start_time, as return by hw_rf_get_start_iff_time(). It should normally check against
* config macro dg_configRF_IFF_CALIBRATION_TIMEOUT.
*
* @warning All the above functions are called in a critical section. They should not block.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
@@ -102,6 +42,7 @@
*
*****************************************************************************************
*/
#ifndef HW_RF_H_
#define HW_RF_H_
@@ -360,6 +301,19 @@ void hw_rf_request_off(bool mode_ble);
*/
void hw_rf_start_continuous_wave(uint8_t mode, uint8_t ch);
/**
* \brief Start reception of a continuous wave (unmodulated reception)
*
* \param [in] mode is the mode to use. 1: BLE, 2 or 3: FTDF (0: Normal, use hw_rf_stop_*)
*
* \param [in] ch is the Channel to receive on, calculated as:
* (mode is BLE) ch = (F – 2402) / 2, where F ranges from 2402 MHz to 2480 MHz.
* Range: 0x00 – 0x27.
* (mode is FTDF) ch = (F – 2405) / 5, where F ranges from 2405 MHz to 2480 MHz.
* Range: 0x00 – 0xf.
*/
void hw_rf_start_continuous_wave_rx(uint8_t mode, uint8_t ch);
/**
* \brief Stop transmitting a continuous wave (unmodulated transmission)
*
third_party/dialog/DialogSDK/bsp/peripherals/include/sys_tcs.h
Vendored
+33 -33
View File
@@ -11,39 +11,39 @@
*/
/**
****************************************************************************************
*
* @file sys_tcs.h
*
* @brief TCS Handler header file.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
****************************************************************************************
*
* @file sys_tcs.h
*
* @brief TCS Handler header file.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
#ifndef SYS_TCS_H_
#define SYS_TCS_H_
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_aes_hash.c
Vendored
+35 -35
View File
@@ -8,44 +8,44 @@
*/
/**
****************************************************************************************
*
* @file hw_cpm.c
*
* @brief Clock and Power Manager Driver
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
****************************************************************************************
*
* @file hw_aes_hash.c
*
* @brief Implementation of the AES/Hash Engine Low Level Driver.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
#if dg_configUSE_HW_AES_HASH
#include "hw_aes_hash.h"
#include "hw_crypto.h"
#include <hw_aes_hash.h>
#include <hw_crypto.h>
#define MODE_IS_AES(m) (m <= HW_AES_CTR)
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_cpm.c
Vendored
+556 -594
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_crypto.c
Vendored
+33 -33
View File
@@ -8,39 +8,39 @@
*/
/**
****************************************************************************************
*
* @file hw_cpm.c
*
* @brief Clock and Power Manager Driver
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
****************************************************************************************
*
* @file hw_crypto.c
*
* @brief Implementation of interrupt handling for the AES/Hash and ECC Engines.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
#if (dg_configUSE_HW_AES_HASH || dg_configUSE_HW_ECC)
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_dma.c
Vendored
+244 -285
View File
@@ -54,10 +54,9 @@
# define SEGGER_SYSTEMVIEW_ISR_EXIT()
#endif
static struct hw_dma_callback_data
{
hw_dma_transfer_cb callback;
void *user_data;
static struct hw_dma_callback_data {
hw_dma_transfer_cb callback;
void *user_data;
} dma_callbacks_user_data[8];
#define DMA_CHN_REG(reg, chan) ((volatile uint16 *)(&(reg)) + ((chan) * 8))
@@ -70,251 +69,224 @@ static struct hw_dma_callback_data
*/
void hw_dma_channel_initialization(DMA_setup *channel_setup)
{
volatile uint16 *dma_x_ctrl_reg;
volatile uint16 *dma_x_a_start_low_reg;
volatile uint16 *dma_x_a_start_high_reg;
volatile uint16 *dma_x_b_start_low_reg;
volatile uint16 *dma_x_b_start_high_reg;
volatile uint16 *dma_x_len_reg;
volatile uint16 *dma_x_int_reg;
uint32 src_address;
uint32 dest_address;
volatile uint16 *dma_x_ctrl_reg;
volatile uint16 *dma_x_a_start_low_reg;
volatile uint16 *dma_x_a_start_high_reg;
volatile uint16 *dma_x_b_start_low_reg;
volatile uint16 *dma_x_b_start_high_reg;
volatile uint16 *dma_x_len_reg;
volatile uint16 *dma_x_int_reg;
uint32 src_address;
uint32 dest_address;
/* Make sure the DMA channel length is not zero */
ASSERT_WARNING(channel_setup->length > 0);
/* Make sure the DMA channel length is not zero */
ASSERT_WARNING(channel_setup->length > 0);
// Look up DMAx_CTRL_REG address
dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_setup->channel_number);
// Look up DMAx_CTRL_REG address
dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_setup->channel_number);
// Look up DMAx_A_STARTL_REG address
dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel_setup->channel_number);
// Look up DMAx_A_STARTL_REG address
dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel_setup->channel_number);
// Look up DMAx_A_STARTH_REG address
dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel_setup->channel_number);
// Look up DMAx_A_STARTH_REG address
dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel_setup->channel_number);
// Look up DMAx_B_STARTL_REG address
dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel_setup->channel_number);
// Look up DMAx_B_STARTL_REG address
dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel_setup->channel_number);
// Look up DMAx_B_STARTH_REG address
dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel_setup->channel_number);
// Look up DMAx_B_STARTH_REG address
dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel_setup->channel_number);
// Look up DMAX_LEN_REG address
dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel_setup->channel_number);
// Look up DMAX_LEN_REG address
dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel_setup->channel_number);
// Look up DMAX_INT
dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel_setup->channel_number);
// Look up DMAX_INT
dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel_setup->channel_number);
// Make sure DMA channel is disabled first
REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, HW_DMA_STATE_DISABLED);
// Make sure DMA channel is disabled first
REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, HW_DMA_STATE_DISABLED);
// Set DMAx_CTRL_REG width provided settings, but do not start the channel.
// Start the channel with the "dma_channel_enable" function separately.
*dma_x_ctrl_reg =
channel_setup->bus_width |
channel_setup->irq_enable |
channel_setup->dreq_mode |
channel_setup->b_inc |
channel_setup->a_inc |
channel_setup->circular |
channel_setup->dma_prio |
channel_setup->dma_idle |
channel_setup->dma_init;
// Set DMA_REQ_MUX_REG for the requested channel / trigger combination
if (channel_setup->dma_req_mux != HW_DMA_TRIG_NONE)
{
switch (channel_setup->channel_number)
{
case HW_DMA_CHANNEL_0:
case HW_DMA_CHANNEL_1:
GLOBAL_INT_DISABLE();
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, channel_setup->dma_req_mux);
GLOBAL_INT_RESTORE();
break;
case HW_DMA_CHANNEL_2:
case HW_DMA_CHANNEL_3:
GLOBAL_INT_DISABLE();
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, channel_setup->dma_req_mux);
GLOBAL_INT_RESTORE();
break;
case HW_DMA_CHANNEL_4:
case HW_DMA_CHANNEL_5:
GLOBAL_INT_DISABLE();
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, channel_setup->dma_req_mux);
GLOBAL_INT_RESTORE();
break;
case HW_DMA_CHANNEL_6:
case HW_DMA_CHANNEL_7:
GLOBAL_INT_DISABLE();
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA67_SEL, channel_setup->dma_req_mux);
GLOBAL_INT_RESTORE();
break;
default:
break;
}
// Set DMAx_CTRL_REG width provided settings, but do not start the channel.
// Start the channel with the "dma_channel_enable" function separately.
*dma_x_ctrl_reg =
channel_setup->bus_width |
channel_setup->irq_enable |
channel_setup->dreq_mode |
channel_setup->b_inc |
channel_setup->a_inc |
channel_setup->circular |
channel_setup->dma_prio |
channel_setup->dma_idle |
channel_setup->dma_init;
// Set DMA_REQ_MUX_REG for the requested channel / trigger combination
if (channel_setup->dma_req_mux != HW_DMA_TRIG_NONE) {
switch (channel_setup->channel_number) {
case HW_DMA_CHANNEL_0:
case HW_DMA_CHANNEL_1:
GLOBAL_INT_DISABLE();
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, channel_setup->dma_req_mux);
GLOBAL_INT_RESTORE();
break;
case HW_DMA_CHANNEL_2:
case HW_DMA_CHANNEL_3:
GLOBAL_INT_DISABLE();
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, channel_setup->dma_req_mux);
GLOBAL_INT_RESTORE();
break;
case HW_DMA_CHANNEL_4:
case HW_DMA_CHANNEL_5:
GLOBAL_INT_DISABLE();
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, channel_setup->dma_req_mux);
GLOBAL_INT_RESTORE();
break;
case HW_DMA_CHANNEL_6:
case HW_DMA_CHANNEL_7:
GLOBAL_INT_DISABLE();
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA67_SEL, channel_setup->dma_req_mux);
GLOBAL_INT_RESTORE();
break;
default:
break;
}
#if dg_configDMA_DYNAMIC_MUX || (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A)
/*
* When different DMA channels are used for same device it is important
* that only one trigger is set for specific device at a time.
* Having same trigger for different channels can cause unpredictable results.
* Following code also should help when SPI1 is assigned to non 0 channel.
*/
GLOBAL_INT_DISABLE();
switch (channel_setup->channel_number)
{
case HW_DMA_CHANNEL_6:
case HW_DMA_CHANNEL_7:
if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL) == channel_setup->dma_req_mux)
{
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, HW_DMA_TRIG_NONE);
}
/* no break */
case HW_DMA_CHANNEL_4:
case HW_DMA_CHANNEL_5:
if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL) == channel_setup->dma_req_mux)
{
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, HW_DMA_TRIG_NONE);
}
/* no break */
case HW_DMA_CHANNEL_2:
case HW_DMA_CHANNEL_3:
if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL) == channel_setup->dma_req_mux)
{
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, HW_DMA_TRIG_NONE);
}
break;
case HW_DMA_CHANNEL_0:
case HW_DMA_CHANNEL_1:
default:
break;
}
GLOBAL_INT_RESTORE();
/*
* When different DMA channels are used for same device it is important
* that only one trigger is set for specific device at a time.
* Having same trigger for different channels can cause unpredictable results.
* Following code also should help when SPI1 is assigned to non 0 channel.
*/
GLOBAL_INT_DISABLE();
switch (channel_setup->channel_number) {
case HW_DMA_CHANNEL_6:
case HW_DMA_CHANNEL_7:
if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL) == channel_setup->dma_req_mux) {
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA45_SEL, HW_DMA_TRIG_NONE);
}
/* no break */
case HW_DMA_CHANNEL_4:
case HW_DMA_CHANNEL_5:
if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL) == channel_setup->dma_req_mux) {
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA23_SEL, HW_DMA_TRIG_NONE);
}
/* no break */
case HW_DMA_CHANNEL_2:
case HW_DMA_CHANNEL_3:
if (REG_GETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL) == channel_setup->dma_req_mux) {
REG_SETF(DMA, DMA_REQ_MUX_REG, DMA01_SEL, HW_DMA_TRIG_NONE);
}
break;
case HW_DMA_CHANNEL_0:
case HW_DMA_CHANNEL_1:
default:
break;
}
GLOBAL_INT_RESTORE();
#endif
}
}
#if (dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B)
//Set REQ_SENSE bit of i2c and Uart peripherals TX path
if (((channel_setup->dma_req_mux == HW_DMA_TRIG_UART_RXTX) ||
(channel_setup->dma_req_mux == HW_DMA_TRIG_UART2_RXTX) ||
(channel_setup->dma_req_mux == HW_DMA_TRIG_I2C_RXTX) ||
(channel_setup->dma_req_mux == HW_DMA_TRIG_I2C2_RXTX)) &&
(channel_setup->channel_number & 1)) //odd channels used for TX
{
REG_SET_FIELD(DMA, DMA0_CTRL_REG, REQ_SENSE, *dma_x_ctrl_reg, 1);
}
//Set REQ_SENSE bit of i2c, USB and Uart peripherals TX path
if (((channel_setup->dma_req_mux == HW_DMA_TRIG_UART_RXTX) ||
(channel_setup->dma_req_mux == HW_DMA_TRIG_UART2_RXTX) ||
(channel_setup->dma_req_mux == HW_DMA_TRIG_I2C_RXTX) ||
(channel_setup->dma_req_mux == HW_DMA_TRIG_I2C2_RXTX) ||
(channel_setup->dma_req_mux == HW_DMA_TRIG_USB_RXTX)) &&
(channel_setup->channel_number & 1)) {//odd channels used for TX
REG_SET_FIELD(DMA, DMA0_CTRL_REG, REQ_SENSE, *dma_x_ctrl_reg, 1);
}
#endif
src_address = DA15000_phy_addr(channel_setup->src_address);
dest_address = DA15000_phy_addr(channel_setup->dest_address);
src_address = DA15000_phy_addr(channel_setup->src_address);
dest_address = DA15000_phy_addr(channel_setup->dest_address);
// Set source address registers
*dma_x_a_start_low_reg = (src_address & 0xffff);
*dma_x_a_start_high_reg = (src_address >> 16);
// Set source address registers
*dma_x_a_start_low_reg = (src_address & 0xffff);
*dma_x_a_start_high_reg = (src_address >> 16);
// Set destination address registers
*dma_x_b_start_low_reg = (dest_address & 0xffff);
*dma_x_b_start_high_reg = (dest_address >> 16);
// Set destination address registers
*dma_x_b_start_low_reg = (dest_address & 0xffff);
*dma_x_b_start_high_reg = (dest_address >> 16);
// Set IRQ number of transfers
if (channel_setup->irq_nr_of_trans > 0)
{
// If user explicitly set this number use it
*dma_x_int_reg = channel_setup->irq_nr_of_trans - 1;
}
else
{
// If user passed 0, use transfer length to fire interrupt after transfer ends
*dma_x_int_reg = channel_setup->length - 1;
}
// Set IRQ number of transfers
if (channel_setup->irq_nr_of_trans > 0) {
// If user explicitly set this number use it
*dma_x_int_reg = channel_setup->irq_nr_of_trans - 1;
} else {
// If user passed 0, use transfer length to fire interrupt after transfer ends
*dma_x_int_reg = channel_setup->length - 1;
}
// Set the transfer length
*dma_x_len_reg = (channel_setup->length) - 1;
// Set the transfer length
*dma_x_len_reg = (channel_setup->length) - 1;
if (channel_setup->irq_enable)
{
dma_callbacks_user_data[channel_setup->channel_number].callback = channel_setup->callback;
}
else
{
dma_callbacks_user_data[channel_setup->channel_number].callback = NULL;
}
dma_callbacks_user_data[channel_setup->channel_number].user_data = channel_setup->user_data;
if (channel_setup->irq_enable)
dma_callbacks_user_data[channel_setup->channel_number].callback = channel_setup->callback;
else
dma_callbacks_user_data[channel_setup->channel_number].callback = NULL;
dma_callbacks_user_data[channel_setup->channel_number].user_data = channel_setup->user_data;
}
void hw_dma_channel_update_source(HW_DMA_CHANNEL channel, void *addr, uint16_t length,
hw_dma_transfer_cb cb)
hw_dma_transfer_cb cb)
{
uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr);
uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr);
dma_callbacks_user_data[channel].callback = cb;
dma_callbacks_user_data[channel].callback = cb;
// Look up DMAx_A_STARTL_REG address
volatile uint16 *dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel);
// Look up DMAx_A_STARTL_REG address
volatile uint16 *dma_x_a_start_low_reg = DMA_CHN_REG(DMA->DMA0_A_STARTL_REG, channel);
// Look up DMAx_A_STARTH_REG address
volatile uint16 *dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel);
// Look up DMAx_A_STARTH_REG address
volatile uint16 *dma_x_a_start_high_reg = DMA_CHN_REG(DMA->DMA0_A_STARTH_REG, channel);
// Look up DMAX_LEN_REG address
volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel);
// Look up DMAX_LEN_REG address
volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel);
volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel);
volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel);
// Set source address registers
*dma_x_a_start_low_reg = (phy_addr & 0xffff);
*dma_x_a_start_high_reg = (phy_addr >> 16);
// Set source address registers
*dma_x_a_start_low_reg = (phy_addr & 0xffff);
*dma_x_a_start_high_reg = (phy_addr >> 16);
*dma_x_int_reg = length - 1;
*dma_x_int_reg = length - 1;
// Set the transfer length
*dma_x_len_reg = length - 1;
// Set the transfer length
*dma_x_len_reg = length - 1;
}
void hw_dma_channel_update_destination(HW_DMA_CHANNEL channel, void *addr, uint16_t length,
hw_dma_transfer_cb cb)
hw_dma_transfer_cb cb)
{
uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr);
uint32_t phy_addr = DA15000_phy_addr((uint32_t) addr);
dma_callbacks_user_data[channel].callback = cb;
dma_callbacks_user_data[channel].callback = cb;
// Look up DMAx_B_STARTL_REG address
volatile uint16 *dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel);
// Look up DMAx_B_STARTL_REG address
volatile uint16 *dma_x_b_start_low_reg = DMA_CHN_REG(DMA->DMA0_B_STARTL_REG, channel);
// Look up DMAx_B_STARTH_REG address
volatile uint16 *dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel);
// Look up DMAx_B_STARTH_REG address
volatile uint16 *dma_x_b_start_high_reg = DMA_CHN_REG(DMA->DMA0_B_STARTH_REG, channel);
// Look up DMAX_LEN_REG address
volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel);
volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel);
// Look up DMAX_LEN_REG address
volatile uint16 *dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, channel);
volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel);
// Set destination address registers
*dma_x_b_start_low_reg = (phy_addr & 0xffff);
*dma_x_b_start_high_reg = (phy_addr >> 16);
// Set destination address registers
*dma_x_b_start_low_reg = (phy_addr & 0xffff);
*dma_x_b_start_high_reg = (phy_addr >> 16);
*dma_x_int_reg = length - 1;
*dma_x_int_reg = length - 1;
// Set the transfer length
*dma_x_len_reg = length - 1;
// Set the transfer length
*dma_x_len_reg = length - 1;
}
void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix)
{
volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel);
volatile uint16 *dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, channel);
*dma_x_int_reg = int_ix;
*dma_x_int_reg = int_ix;
}
/**
@@ -326,70 +298,59 @@ void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix)
*/
void hw_dma_channel_enable(HW_DMA_CHANNEL channel_number, HW_DMA_STATE dma_on)
{
volatile uint16 *dma_x_ctrl_reg;
volatile uint16 *dma_x_ctrl_reg;
// Look up DMAx_CTRL_REG address
dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_number);
// Look up DMAx_CTRL_REG address
dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, channel_number);
if (dma_on == HW_DMA_STATE_ENABLED)
{
uint16_t dma_ctrl = *dma_x_ctrl_reg;
if (dma_on == HW_DMA_STATE_ENABLED) {
uint16_t dma_ctrl = *dma_x_ctrl_reg;
REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, dma_ctrl, 1);
if (dma_callbacks_user_data[channel_number].callback)
{
REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, dma_ctrl, 1);
REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, dma_ctrl, 1);
if (dma_callbacks_user_data[channel_number].callback) {
REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, dma_ctrl, 1);
}
// Start the chosen DMA channel
*dma_x_ctrl_reg = dma_ctrl;
NVIC_EnableIRQ(DMA_IRQn);
} else {
// Stop the chosen DMA channel
REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, 0);
REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, *dma_x_ctrl_reg, 0);
}
// Start the chosen DMA channel
*dma_x_ctrl_reg = dma_ctrl;
NVIC_EnableIRQ(DMA_IRQn);
}
else
{
// Stop the chosen DMA channel
REG_SET_FIELD(DMA, DMA0_CTRL_REG, DMA_ON, *dma_x_ctrl_reg, 0);
REG_SET_FIELD(DMA, DMA0_CTRL_REG, IRQ_ENABLE, *dma_x_ctrl_reg, 0);
}
}
static inline void dma_helper(HW_DMA_CHANNEL channel_number, uint16_t len, bool stop_dma)
{
hw_dma_transfer_cb cb;
hw_dma_transfer_cb cb;
NVIC_DisableIRQ(DMA_IRQn);
cb = dma_callbacks_user_data[channel_number].callback;
if (stop_dma)
{
dma_callbacks_user_data[channel_number].callback = NULL;
hw_dma_channel_enable(channel_number, HW_DMA_STATE_DISABLED);
}
if (cb)
{
cb(dma_callbacks_user_data[channel_number].user_data, len);
}
NVIC_EnableIRQ(DMA_IRQn);
NVIC_DisableIRQ(DMA_IRQn);
cb = dma_callbacks_user_data[channel_number].callback;
if (stop_dma) {
dma_callbacks_user_data[channel_number].callback = NULL;
hw_dma_channel_enable(channel_number, HW_DMA_STATE_DISABLED);
}
if (cb) {
cb(dma_callbacks_user_data[channel_number].user_data, len);
}
NVIC_EnableIRQ(DMA_IRQn);
}
bool hw_dma_channel_active(void)
{
int dma_on;
int dma_on;
dma_on = REG_GETF(DMA, DMA0_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA1_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA2_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA3_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA4_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA5_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA6_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA7_CTRL_REG, DMA_ON);
dma_on = REG_GETF(DMA, DMA0_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA1_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA2_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA3_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA4_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA5_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA6_CTRL_REG, DMA_ON);
dma_on |= REG_GETF(DMA, DMA7_CTRL_REG, DMA_ON);
return (dma_on == 1);
return (dma_on == 1);
}
/**
@@ -400,62 +361,60 @@ bool hw_dma_channel_active(void)
*/
void DMA_Handler(void)
{
SEGGER_SYSTEMVIEW_ISR_ENTER();
SEGGER_SYSTEMVIEW_ISR_ENTER();
uint16_t risen;
uint16_t i;
volatile uint16 *dma_x_len_reg;
volatile uint16 *dma_x_int_reg;
volatile uint16 *dma_x_ctrl_reg;
uint16_t risen;
uint16_t i;
volatile uint16 *dma_x_len_reg;
volatile uint16 *dma_x_int_reg;
volatile uint16 *dma_x_ctrl_reg;
risen = DMA->DMA_INT_STATUS_REG;
risen = DMA->DMA_INT_STATUS_REG;
for (i = 0; risen != 0 && i < 8; ++i, risen >>= 1)
{
if (risen & 1)
{
bool stop;
for (i = 0; risen != 0 && i < 8; ++i, risen >>= 1) {
if (risen & 1) {
bool stop;
/*
* DMAx_INT_REG shows after how many transfers the interrupt
* is generated
*/
dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, i);
/*
* DMAx_INT_REG shows after how many transfers the interrupt
* is generated
*/
dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_INT_REG, i);
/*
* DMAx_LEN_REG shows the length of the DMA transfer
*/
dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, i);
/*
* DMAx_LEN_REG shows the length of the DMA transfer
*/
dma_x_len_reg = DMA_CHN_REG(DMA->DMA0_LEN_REG, i);
dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, i);
dma_x_ctrl_reg = DMA_CHN_REG(DMA->DMA0_CTRL_REG, i);
/*
* Stop DMA if:
* - transfer is completed
* - mode is not circular
*/
stop = (*dma_x_int_reg == *dma_x_len_reg)
&& (!REG_GET_FIELD(DMA, DMA0_CTRL_REG, CIRCULAR, *dma_x_ctrl_reg));
DMA->DMA_CLEAR_INT_REG = 1 << i;
dma_helper(i, *dma_x_int_reg + 1, stop);
/*
* Stop DMA if:
* - transfer is completed
* - mode is not circular
*/
stop = (*dma_x_int_reg == *dma_x_len_reg)
&& (!REG_GET_FIELD(DMA, DMA0_CTRL_REG, CIRCULAR, *dma_x_ctrl_reg));
DMA->DMA_CLEAR_INT_REG = 1 << i;
dma_helper(i, *dma_x_int_reg + 1, stop);
}
}
}
SEGGER_SYSTEMVIEW_ISR_EXIT();
SEGGER_SYSTEMVIEW_ISR_EXIT();
}
void hw_dma_channel_stop(HW_DMA_CHANNEL channel_number)
{
// Stopping DMA will clear DMAx_IDX_REG so read it before
volatile uint16 *dma_x_idx_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number);
dma_helper(channel_number, *dma_x_idx_reg, true);
// Stopping DMA will clear DMAx_IDX_REG so read it before
volatile uint16 *dma_x_idx_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number);
dma_helper(channel_number, *dma_x_idx_reg, true);
}
uint16_t hw_dma_transfered_bytes(HW_DMA_CHANNEL channel_number)
{
volatile uint16 *dma_x_int_reg = dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number);
volatile uint16 *dma_x_int_reg = dma_x_int_reg = DMA_CHN_REG(DMA->DMA0_IDX_REG, channel_number);
return *dma_x_int_reg;
return *dma_x_int_reg;
}
#endif /* dg_configUSE_HW_DMA */
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_fem_sky66112-11.c
Vendored
-680
View File
@@ -1,680 +0,0 @@
/**
* \addtogroup BSP
* \{
* \addtogroup DEVICES
* \{
* \addtogroup FEM
* \{
*/
/**
*****************************************************************************************
*
* @file
*
* @brief FEM Driver for SKYWORKS SKY66112-11 Radio module
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*****************************************************************************************
*/
#if dg_configFEM == FEM_SKY66112_11
#include "stdint.h"
#include "sdk_defs.h"
#include "hw_gpio.h"
#include "hw_fem_sky66112-11.h"
static hw_fem_config fem_config __RETAINED;
#if !defined(dg_configFEM_SKY66112_11_CTX_PORT) || !defined(dg_configFEM_SKY66112_11_CTX_PIN)
#error FEM CTX GPIO must be defined!!
#endif
#if !defined(dg_configFEM_SKY66112_11_CRX_PORT) || !defined(dg_configFEM_SKY66112_11_CRX_PIN)
#error FEM CRX GPIO must be defined!!
#endif
int hw_fem_set_bias(uint16_t voltage)
{
uint16_t value;
if (voltage < 1200 || voltage > 1975)
{
return -1;
}
value = (voltage - 1200) / 27.5;
#ifdef dg_configFEM_SKY66112_11_FEM_BIAS_V18P
REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, value);
return 0;
#elif defined(dg_configFEM_SKY66112_11_FEM_BIAS_V18)
REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, value);
return 0;
#else
return -2;
#endif
}
int hw_fem_set_bias2(uint16_t voltage)
{
uint16_t value;
if (voltage < 1200 || voltage > 1975)
{
return -1;
}
value = (voltage - 1200) / 27.5;
// /* Value is actually one lower than computed */
// if (value > 0)
// value--;
#ifdef dg_configFEM_SKY66112_11_FEM_BIAS2_V18P
REG_SETF(DCDC, DCDC_V18P_0_REG, DCDC_V18P_VOLTAGE, value);
#elif defined(dg_configFEM_SKY66112_11_FEM_BIAS2_V18)
REG_SETF(DCDC, DCDC_V18_0_REG, DCDC_V18_VOLTAGE, value);
#else
return -2;
#endif
return 0;
}
#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A
void hw_fem_set_txpower(bool high)
{
#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN)
GLOBAL_INT_DISABLE();
fem_config.tx_power = high;
if (fem_config.started)
{
if (high == false)
{
/* TX Power low. Stop DCF, set GPIO to low */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT,
dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG,
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_RX_Msk |
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk, 0);
}
else
{
/* TX Power high. Configure GPIO for DCF. Enable DCF on TX. */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CHL_PORT,
dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT4_DCF);
REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG,
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_RX_Msk |
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk,
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk);
}
}
GLOBAL_INT_RESTORE();
#endif
}
static void set_bypass(void)
{
uint16_t m = 0;
if (fem_config.tx_bypass)
{
m = RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_TX_Msk;
}
if (fem_config.rx_bypass)
{
m |= RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_RX_Msk;
}
REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG,
RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_RX_Msk |
RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_TX_Msk, m);
if (m == 0)
{
/* No RX/TX bypass. Drive the interface line to low */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CPS_PORT,
dg_configFEM_SKY66112_11_CPS_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
}
else
{
/* At least one of TX/RX needs bypass */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CPS_PORT,
dg_configFEM_SKY66112_11_CPS_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT3_DCF);
}
}
void hw_fem_set_tx_bypass(bool enable)
{
#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN)
GLOBAL_INT_DISABLE();
fem_config.tx_bypass = enable;
if (fem_config.started)
{
set_bypass();
}
GLOBAL_INT_RESTORE();
#endif
}
void hw_fem_set_rx_bypass(bool enable)
{
#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN)
GLOBAL_INT_DISABLE();
fem_config.rx_bypass = enable;
if (fem_config.started)
{
set_bypass();
}
GLOBAL_INT_RESTORE();
#endif
}
bool hw_fem_get_txpower(void)
{
return fem_config.tx_power;
}
bool hw_fem_get_tx_bypass(void)
{
return fem_config.tx_bypass;
}
bool hw_fem_get_rx_bypass(void)
{
return fem_config.rx_bypass;
}
#else /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */
#ifdef CONFIG_USE_BLE
bool hw_fem_get_txpower_ble(void)
{
return fem_config.tx_power_ble;
}
bool hw_fem_get_tx_bypass_ble(void)
{
return fem_config.tx_bypass_ble;
}
bool hw_fem_get_rx_bypass_ble(void)
{
return fem_config.rx_bypass_ble;
}
#endif /* CONFIG_USE_BLE */
#ifdef CONFIG_USE_FTDF
bool hw_fem_get_txpower_ftdf(void)
{
return fem_config.tx_power_ftdf;
}
bool hw_fem_get_tx_bypass_ftdf(void)
{
return fem_config.tx_bypass_ftdf;
}
bool hw_fem_get_rx_bypass_ftdf(void)
{
return fem_config.rx_bypass_ftdf;
}
#endif /* CONFIG_USE_FTDF */
bool hw_fem_get_txpower(void)
{
return fem_config.tx_power_ble;
}
bool hw_fem_get_tx_bypass(void)
{
return fem_config.tx_bypass_ble;
}
bool hw_fem_get_rx_bypass(void)
{
return fem_config.rx_bypass_ble;
}
static void set_txpower(void)
{
if (!fem_config.started)
{
return;
}
/* CHL is always 0 on RX */
REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_RX);
REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_RX);
if (fem_config.tx_power_ble)
{
REG_SET_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_TX);
}
if (fem_config.tx_power_ftdf)
{
REG_SET_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_TX);
}
if (fem_config.tx_power_ble || fem_config.tx_power_ftdf)
{
/* TX Power high. Configure GPIO for DCF. Enable DCF on TX. */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CHL_PORT,
dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT4_DCF);
}
else
{
/* TX Power low. Stop DCF, set GPIO to low */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT,
dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
}
}
void hw_fem_set_txpower_ble(bool high)
{
#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN)
GLOBAL_INT_DISABLE();
fem_config.tx_power_ble = high;
set_txpower();
GLOBAL_INT_RESTORE();
#endif
}
void hw_fem_set_txpower_ftdf(bool high)
{
#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN)
GLOBAL_INT_DISABLE();
fem_config.tx_power_ftdf = high;
set_txpower();
GLOBAL_INT_RESTORE();
#endif
}
void hw_fem_set_txpower(bool high)
{
hw_fem_set_txpower_ble(high);
}
static void set_bypass(void)
{
uint16_t m_ble = 0;
uint16_t m_ftdf = 0;
if (fem_config.tx_bypass_ble)
{
m_ble = RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk;
}
if (fem_config.rx_bypass_ble)
{
m_ble |= RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk;
}
if (fem_config.tx_bypass_ftdf)
{
m_ftdf = RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk;
}
if (fem_config.rx_bypass_ftdf)
{
m_ftdf |= RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk;
}
REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_BLE_REG,
RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk |
RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk, m_ble);
REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_FTDF_REG,
RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk |
RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk, m_ftdf);
if (m_ble == 0 && m_ftdf == 0)
{
/* No RX/TX bypass. Drive the interface line to low */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CPS_PORT,
dg_configFEM_SKY66112_11_CPS_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
}
else
{
/* At least one of TX/RX needs bypass */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CPS_PORT,
dg_configFEM_SKY66112_11_CPS_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT3_DCF);
}
}
#ifdef CONFIG_USE_BLE
void hw_fem_set_tx_bypass_ble(bool enable)
{
#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN)
GLOBAL_INT_DISABLE();
fem_config.tx_bypass_ble = enable;
if (fem_config.started)
{
set_bypass();
}
GLOBAL_INT_RESTORE();
#endif
}
void hw_fem_set_rx_bypass_ble(bool enable)
{
#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN)
GLOBAL_INT_DISABLE();
fem_config.rx_bypass_ble = enable;
if (fem_config.started)
{
set_bypass();
}
GLOBAL_INT_RESTORE();
#endif
}
#endif /* CONFIG_USE_BLE */
#ifdef CONFIG_USE_FTDF
void hw_fem_set_tx_bypass_ftdf(bool enable)
{
#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN)
GLOBAL_INT_DISABLE();
fem_config.tx_bypass_ftdf = enable;
if (fem_config.started)
{
set_bypass();
}
GLOBAL_INT_RESTORE();
#endif
}
void hw_fem_set_rx_bypass_ftdf(bool enable)
{
#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN)
GLOBAL_INT_DISABLE();
fem_config.rx_bypass_ftdf = enable;
if (fem_config.started)
{
set_bypass();
}
GLOBAL_INT_RESTORE();
#endif
}
#endif /* CONFIG_USE_FTDF */
void hw_fem_set_tx_bypass(bool enable)
{
hw_fem_set_tx_bypass_ftdf(enable);
}
void hw_fem_set_rx_bypass(bool enable)
{
hw_fem_set_rx_bypass_ftdf(enable);
}
#endif /* dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_B */
void hw_fem_set_antenna(bool one)
{
#if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN)
GLOBAL_INT_DISABLE();
fem_config.antsel = one;
if (fem_config.started)
{
/* Antenna selection */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANTSEL_PORT,
dg_configFEM_SKY66112_11_ANTSEL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, fem_config.antsel);
}
GLOBAL_INT_RESTORE();
#endif
}
bool hw_fem_get_antenna(void)
{
return fem_config.antsel;
}
void hw_fem_start(void)
{
GLOBAL_INT_DISABLE();
fem_config.started = true;
uint8_t set_delay;
uint8_t reset_delay;
uint16_t rf_port_en;
/******************************************************
* Setup GPIOs
*/
/* CSD GPIO Config */
#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN)
# if dg_configFEM_SKY66112_11_CSD_USE_DCF == 0
/* Manually set CSD (Enable FEM) */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true);
# else
/* Use DCF for CSD */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT2_DCF);
# endif
#endif
/* Timer 27 GPIO (DCF Port 0). Used for TX EN */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CTX_PORT, dg_configFEM_SKY66112_11_CTX_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT0_DCF);
/* Timer 28 (DCF Port 1). Used for RX EN */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CRX_PORT, dg_configFEM_SKY66112_11_CRX_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT1_DCF);
/* Antenna selection */
#if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANTSEL_PORT, dg_configFEM_SKY66112_11_ANTSEL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, fem_config.antsel);
#endif
/******************************************************
* Setup RF_ANT_TRIM GPIOs
*/
/* RF_ANT_TRIM_0 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM0);
#endif
/* RF_ANT_TRIM_1 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM1);
#endif
/* RF_ANT_TRIM_2 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM2);
#endif
/******************************************************
* Setup DCFs
*/
/* assign values to the timer registers for CTX/CRX (in usec) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_27_REG, SET_OFFSET, dg_configFEM_SKY66112_11_TXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_27_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_28_REG, SET_OFFSET, dg_configFEM_SKY66112_11_RXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_28_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_RXRESET_DCF);
rf_port_en = 0x6; /* Start with Port 0: TX, Port 1: RX */
/* Compute set/reset delays to use for CSD, CPS, CHL DCFs: For setting delay,
* smaller of TXSET, RXSET, and for resetting delay, larger of TXSET, RXSET
*/
#if dg_configFEM_SKY66112_11_RXSET_DCF > dg_configFEM_SKY66112_11_TXSET_DCF
set_delay = dg_configFEM_SKY66112_11_TXSET_DCF;
#else
set_delay = dg_configFEM_SKY66112_11_RXSET_DCF;
#endif
#if dg_configFEM_SKY66112_11_RXRESET_DCF > dg_configFEM_SKY66112_11_TXRESET_DCF
reset_delay = dg_configFEM_SKY66112_11_RXRESET_DCF;
#else
reset_delay = dg_configFEM_SKY66112_11_TXRESET_DCF;
#endif
/* CSD DCF (if enabled) configuration */
#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN)
# if dg_configFEM_SKY66112_11_CSD_USE_DCF != 0
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_29_REG, SET_OFFSET, set_delay);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_29_REG, RESET_OFFSET, reset_delay);
/* enable DCF Signals for Port 2 (CSD) for both rx/tx */
rf_port_en |= 0x30;
# endif /* dg_configFEM_SKY66112_11_CSD_USE_DCF != 0 */
#endif
/* Set bypass (CPS) DCF timers (but don't enable yet) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_30_REG, SET_OFFSET, set_delay);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_30_REG, RESET_OFFSET, reset_delay);
/* Set TX Power (CHL) DCF timers (but don't enable yet) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, SET_OFFSET, dg_configFEM_SKY66112_11_TXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF);
/* Enable DCFs */
#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A
RFCU_POWER->RF_PORT_EN_REG = rf_port_en;
hw_fem_set_txpower(fem_config.tx_power);
#else
RFCU_POWER->RF_PORT_EN_BLE_REG = rf_port_en;
RFCU_POWER->RF_PORT_EN_FTDF_REG = rf_port_en;
set_txpower();
#endif
set_bypass();
GLOBAL_INT_RESTORE();
}
void hw_fem_stop(void)
{
GLOBAL_INT_DISABLE();
fem_config.started = false;
/* Stop DCF Timers */
#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A
RFCU_POWER->RF_PORT_EN_REG = 0x0;
#else
RFCU_POWER->RF_PORT_EN_BLE_REG = 0x0;
RFCU_POWER->RF_PORT_EN_FTDF_REG = 0x0;
#endif
/* Set all FEM interface outputs to GPIO mode, and value 0, in order to get the minimum
* possible power consumption from FEM
*/
#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#endif
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CTX_PORT, dg_configFEM_SKY66112_11_CTX_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT, dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#endif
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CRX_PORT, dg_configFEM_SKY66112_11_CRX_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#if defined(dg_configFEM_SKY66112_11_CPS_PORT) && defined(dg_configFEM_SKY66112_11_CPS_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CPS_PORT, dg_configFEM_SKY66112_11_CPS_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#endif
#if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANTSEL_PORT, dg_configFEM_SKY66112_11_ANTSEL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#endif
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#endif
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#endif
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
#endif
GLOBAL_INT_RESTORE();
}
#endif /* dg_configFEM == FEM_SKY66112_11 */
/**
* \}
* \}
* \}
*/
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpadc.c
Vendored
+50 -24
View File
@@ -14,12 +14,30 @@
*
* @brief Implementation of the GPADC Low Level Driver.
*
* Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer
* program includes Confidential, Proprietary Information and is a Trade Secret of
* Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited
* unless authorized in writing. All Rights Reserved.
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* <[email protected]> and contributors.
*
****************************************************************************************
*/
@@ -238,33 +256,41 @@ void hw_gpadc_test_measurements(void)
uint16_t hw_gpadc_get_raw_value(void)
{
int32_t adc_raw_res = GPADC->GP_ADC_RESULT_REG;
int16_t gain_error = 0;
uint16_t offset_trim = 0;
uint16_t adc_raw_res = GPADC->GP_ADC_RESULT_REG;
int32_t res = adc_raw_res;
if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) {
if (hw_gpadc_pre_check_for_gain_error()) {
int16_t gain_trim;
const HW_GPADC_INPUT_MODE input_mode = hw_gpadc_get_input_mode();
if (input_mode == HW_GPADC_INPUT_MODE_DIFFERENTIAL) {
gain_error = hw_gpadc_differential_gain_error;
offset_trim = 0x8000;
} else if (input_mode == HW_GPADC_INPUT_MODE_SINGLE_ENDED) {
gain_error = hw_gpadc_single_ended_gain_error;
offset_trim = 0;
}
adc_raw_res = adc_raw_res -
((adc_raw_res - offset_trim ) * gain_error ) / 0x10000;
/* Adjust value for edge cases */
if (adc_raw_res & 0x80000000) { /* negative overflow */
return 0;
}
if (adc_raw_res & 0x7FFF0000) { /* positive overflow */
return UINT16_MAX;
if (input_mode == HW_GPADC_INPUT_MODE_SINGLE_ENDED) {
gain_trim = hw_gpadc_single_ended_gain_error;
/* Gain correction */
res = 0xFFFFU * adc_raw_res / (0xFFFFU + gain_trim);
/* Boundary check */
if ((uint32_t)res > UINT16_MAX) {
return UINT16_MAX;
}
} else if (input_mode == HW_GPADC_INPUT_MODE_DIFFERENTIAL) {
gain_trim = hw_gpadc_differential_gain_error;
res = (int16_t)(adc_raw_res ^ 0x8000);
/* Gain correction */
res = 0xFFFF * res / (0xFFFF + gain_trim);
/* Boundary check for lower limit */
if (res < INT16_MIN) {
return 0; /* INT16_MIN ^ 0x8000 */
}
/* Boundary check for upper limit */
if (res > INT16_MAX) {
return UINT16_MAX; /* INT16_MAX ^ 0x8000 */
}
res ^= 0x8000;
}
}
}
return adc_raw_res;
return res;
}
#endif /* dg_configUSE_HW_GPADC */
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_gpio.c
Vendored
+121 -162
View File
@@ -67,17 +67,15 @@ static uint16_t Px_DATA_REG_cache[5];
#endif
#if (dg_configIMAGE_SETUP == PRODUCTION_MODE) && (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1)
#warning "GPIO assignment monitoring is active in PRODUCTION build!"
#warning "GPIO assignment monitoring is active in PRODUCTION build!"
#endif
static volatile uint8_t GPIO_status[HW_GPIO_NUM_PORTS] = { 0 };
const uint8_t hw_gpio_port_num_pins[HW_GPIO_NUM_PORTS] =
{
HW_GPIO_PORT_0_NUM_PINS, HW_GPIO_PORT_1_NUM_PINS,
HW_GPIO_PORT_2_NUM_PINS, HW_GPIO_PORT_3_NUM_PINS,
HW_GPIO_PORT_4_NUM_PINS
};
const uint8_t hw_gpio_port_num_pins[HW_GPIO_NUM_PORTS] = {
HW_GPIO_PORT_0_NUM_PINS, HW_GPIO_PORT_1_NUM_PINS,
HW_GPIO_PORT_2_NUM_PINS, HW_GPIO_PORT_3_NUM_PINS,
HW_GPIO_PORT_4_NUM_PINS };
/*
* Global Functions
@@ -87,252 +85,213 @@ const uint8_t hw_gpio_port_num_pins[HW_GPIO_NUM_PORTS] =
void hw_gpio_configure(const gpio_config cfg[])
{
#if dg_configIMAGE_SETUP == DEVELOPMENT_MODE
int num_pins = 0;
uint8_t set_mask[HW_GPIO_NUM_PORTS];
int num_pins = 0;
uint8_t set_mask[HW_GPIO_NUM_PORTS] = { 0 };
#endif
if (!cfg)
{
return;
}
if (!cfg) {
return;
}
while (cfg->pin != 0xFF)
{
uint8_t port = cfg->pin >> 4;
uint8_t pin = cfg->pin & 0x0F;
while (cfg->pin != 0xFF) {
uint8_t port = cfg->pin >> 4;
uint8_t pin = cfg->pin & 0x0F;
#if dg_configIMAGE_SETUP == DEVELOPMENT_MODE
if (port >= HW_GPIO_NUM_PORTS || pin >= hw_gpio_port_num_pins[port]) {
/*
* invalid port or pin number specified, it was either incorrectly specified
* of cfg was not terminated properly using HW_GPIO_PINCONFIG_END so we're
* reading garbage
*/
__BKPT(0);
}
if (port >= HW_GPIO_NUM_PORTS || pin >= hw_gpio_port_num_pins[port])
{
/*
* invalid port or pin number specified, it was either incorrectly specified
* of cfg was not terminated properly using HW_GPIO_PINCONFIG_END so we're
* reading garbage
*/
__BKPT(0);
}
if (++num_pins > HW_GPIO_NUM_PINS) {
/*
* trying to set more pins than available, perhaps cfg was not terminated
* properly using HW_GPIO_PINCONFIG_END?
*/
__BKPT(0);
}
if (++num_pins > HW_GPIO_NUM_PINS)
{
/*
* trying to set more pins than available, perhaps cfg was not terminated
* properly using HW_GPIO_PINCONFIG_END?
*/
__BKPT(0);
}
if (set_mask[port] & (1 << pin)) {
/*
* trying to set pin which has been already set by this call which means
* there is duplicated pin in configuration - does not make sense
*/
__BKPT(0);
}
if (set_mask[port] & (1 << pin))
{
/*
* trying to set pin which has been already set by this call which means
* there is duplicated pin in configuration - does not make sense
*/
__BKPT(0);
}
set_mask[port] |= (1 << pin);
set_mask[port] |= (1 << pin);
#endif
if (cfg->reserve)
{
hw_gpio_reserve_and_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high);
}
else
{
hw_gpio_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high);
}
if (cfg->reserve) {
hw_gpio_reserve_and_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high);
} else {
hw_gpio_configure_pin(port, pin, cfg->mode, cfg->func, cfg->high);
}
cfg++;
}
cfg++;
}
}
bool hw_gpio_reserve_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin)
{
if ((GPIO_status[port] & (1 << pin)))
{
return false;
}
if ((GPIO_status[port] & (1 << pin))) {
return false;
}
GPIO_status[port] |= (1 << pin);
GPIO_status[port] |= (1 << pin);
return true;
return true;
}
bool hw_gpio_reserve_and_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode,
HW_GPIO_FUNC function, bool high)
HW_GPIO_FUNC function, bool high)
{
if (!hw_gpio_reserve_pin(port, pin))
{
return false;
}
if (!hw_gpio_reserve_pin(port, pin)) {
return false;
}
hw_gpio_configure_pin(port, pin, mode, function, high);
hw_gpio_configure_pin(port, pin, mode, function, high);
return true;
return true;
}
void hw_gpio_unreserve_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin)
{
GPIO_status[port] &= ~(1 << pin);
GPIO_status[port] &= ~(1 << pin);
}
static void hw_gpio_verify_reserved(HW_GPIO_PORT port, HW_GPIO_PIN pin)
{
#if (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1)
if (!(GPIO_status[port] & (1 << pin)))
{
// If debugger stops at this line, there is configuration problem
// pin is used without being reserved first
__BKPT(0); /* this pin has not been previously reserved! */
}
if (!(GPIO_status[port] & (1 << pin))) {
// If debugger stops at this line, there is configuration problem
// pin is used without being reserved first
__BKPT(0); /* this pin has not been previously reserved! */
}
#endif // (DEBUG_GPIO_ALLOC_MONITOR_ENABLED == 1)
}
void hw_gpio_set_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode,
HW_GPIO_FUNC function)
HW_GPIO_FUNC function)
{
hw_gpio_verify_reserved(port, pin);
hw_gpio_verify_reserved(port, pin);
PXX_MODE_REG(port, pin) = mode | function;
PXX_MODE_REG(port, pin) = mode | function;
}
void hw_gpio_get_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE *mode,
HW_GPIO_FUNC *function)
void hw_gpio_get_pin_function(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE* mode,
HW_GPIO_FUNC* function)
{
uint16_t val;
uint16_t val;
hw_gpio_verify_reserved(port, pin);
hw_gpio_verify_reserved(port, pin);
val = PXX_MODE_REG(port, pin);
*mode = val & 0x0700;
*function = val & 0x00ff;
val = PXX_MODE_REG(port, pin);
*mode = val & 0x0700;
*function = val & 0x00ff;
}
void hw_gpio_configure_pin(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_MODE mode,
HW_GPIO_FUNC function, const bool high)
HW_GPIO_FUNC function, const bool high)
{
hw_gpio_verify_reserved(port, pin);
hw_gpio_verify_reserved(port, pin);
if (high)
{
hw_gpio_set_active(port, pin);
}
else
{
hw_gpio_set_inactive(port, pin);
}
if (high)
hw_gpio_set_active(port, pin);
else
hw_gpio_set_inactive(port, pin);
hw_gpio_set_pin_function(port, pin, mode, function);
hw_gpio_set_pin_function(port, pin, mode, function);
}
void hw_gpio_configure_pin_power(HW_GPIO_PORT port, HW_GPIO_PIN pin, HW_GPIO_POWER power)
{
uint16_t padpwr;
uint16_t padpwr;
padpwr = PX_PADPWR_CTRL_REG(port);
padpwr &= ~(1 << pin);
if (power == HW_GPIO_POWER_VDD1V8P)
{
padpwr |= (1 << pin);
}
PX_PADPWR_CTRL_REG(port) = padpwr;
padpwr = PX_PADPWR_CTRL_REG(port);
padpwr &= ~(1 << pin);
if (power == HW_GPIO_POWER_VDD1V8P) {
padpwr |= (1 << pin);
}
PX_PADPWR_CTRL_REG(port) = padpwr;
}
void hw_gpio_set_active(HW_GPIO_PORT port, HW_GPIO_PIN pin)
{
hw_gpio_verify_reserved(port, pin);
hw_gpio_verify_reserved(port, pin);
PX_SET_DATA_REG(port) = 1 << pin;
PX_SET_DATA_REG(port) = 1 << pin;
#ifdef FPGA_PAD_LOOPBACK_BROKEN
Px_DATA_REG_cache[port] |= 1 << pin;
Px_DATA_REG_cache[port] |= 1 << pin;
#endif
}
void hw_gpio_set_inactive(HW_GPIO_PORT port, HW_GPIO_PIN pin)
{
hw_gpio_verify_reserved(port, pin);
hw_gpio_verify_reserved(port, pin);
PX_RESET_DATA_REG(port) = 1 << pin;
PX_RESET_DATA_REG(port) = 1 << pin;
#ifdef FPGA_PAD_LOOPBACK_BROKEN
Px_DATA_REG_cache[port] &= ~(1 << pin);
Px_DATA_REG_cache[port] &= ~(1 << pin);
#endif
}
bool hw_gpio_get_pin_status(HW_GPIO_PORT port, HW_GPIO_PIN pin)
{
#ifdef FPGA_PAD_LOOPBACK_BROKEN
HW_GPIO_MODE mode;
HW_GPIO_FUNC function;
HW_GPIO_MODE mode;
HW_GPIO_FUNC function;
#endif
hw_gpio_verify_reserved(port, pin);
hw_gpio_verify_reserved(port, pin);
#ifdef FPGA_PAD_LOOPBACK_BROKEN
hw_gpio_get_pin_function(port, pin, &mode, &function);
if (mode != HW_GPIO_MODE_OUTPUT)
{
return !!(PX_DATA_REG(port) & (1 << pin));
}
else
{
return !!(Px_DATA_REG_cache[port] & (1 << pin));
}
hw_gpio_get_pin_function(port, pin, &mode, &function);
if (mode != HW_GPIO_MODE_OUTPUT)
return !!(PX_DATA_REG(port) & (1 << pin));
else
return !!(Px_DATA_REG_cache[port] & (1 << pin));
#else
return ((PX_DATA_REG(port) & (1 << pin)) != 0);
return ( (PX_DATA_REG(port) & (1 << pin)) != 0 );
#endif
}
void hw_gpio_toggle(HW_GPIO_PORT port, HW_GPIO_PIN pin)
{
hw_gpio_verify_reserved(port, pin);
hw_gpio_verify_reserved(port, pin);
if (hw_gpio_get_pin_status(port, pin))
{
hw_gpio_set_inactive(port, pin);
}
else
{
hw_gpio_set_active(port, pin);
}
if (hw_gpio_get_pin_status(port, pin))
hw_gpio_set_inactive(port, pin);
else
hw_gpio_set_active(port, pin);
}
int hw_gpio_get_pins_with_function(HW_GPIO_FUNC func, uint8_t *buf, int buf_size)
{
int count = 0;
int port;
int pin;
HW_GPIO_MODE mode;
HW_GPIO_FUNC pin_func;
int count = 0;
int port;
int pin;
HW_GPIO_MODE mode;
HW_GPIO_FUNC pin_func;
for (port = 0; port < HW_GPIO_NUM_PORTS; ++port)
{
for (pin = 0; pin < hw_gpio_port_num_pins[port]; ++pin)
{
hw_gpio_get_pin_function(port, pin, &mode, &pin_func);
if (pin_func != func)
{
continue;
}
if (count < buf_size && buf != NULL)
{
buf[count] = (uint8_t)((port << 4) | pin);
}
count++;
for (port = 0; port < HW_GPIO_NUM_PORTS; ++port) {
for (pin = 0; pin < hw_gpio_port_num_pins[port]; ++pin) {
hw_gpio_get_pin_function(port, pin, &mode, &pin_func);
if (pin_func != func) {
continue;
}
if (count < buf_size && buf != NULL) {
buf[count] = (uint8_t) ((port << 4) | pin);
}
count++;
}
}
}
return count;
return count;
}
#endif /* dg_configUSE_HW_GPIO */
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_hard_fault.c
Vendored
+59 -61
View File
@@ -41,6 +41,7 @@
*
****************************************************************************************
*/
#include <stdint.h>
#include <stdio.h>
#include "sdk_defs.h"
@@ -91,80 +92,77 @@ __attribute__((section("text_retained")))
#endif
void HardFault_HandlerC(unsigned long *hardfault_args)
{
// Stack frame contains:
// r0, r1, r2, r3, r12, r14, the return address and xPSR
// - Stacked R0 = hf_args[0]
// - Stacked R1 = hf_args[1]
// - Stacked R2 = hf_args[2]
// - Stacked R3 = hf_args[3]
// - Stacked R12 = hf_args[4]
// - Stacked LR = hf_args[5]
// - Stacked PC = hf_args[6]
// - Stacked xPSR= hf_args[7]
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
{
hw_watchdog_freeze(); // Stop WDOG
// Stack frame contains:
// r0, r1, r2, r3, r12, r14, the return address and xPSR
// - Stacked R0 = hf_args[0]
// - Stacked R1 = hf_args[1]
// - Stacked R2 = hf_args[2]
// - Stacked R3 = hf_args[3]
// - Stacked R12 = hf_args[4]
// - Stacked LR = hf_args[5]
// - Stacked PC = hf_args[6]
// - Stacked xPSR= hf_args[7]
if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE) {
hw_watchdog_freeze(); // Stop WDOG
ENABLE_DEBUGGER;
ENABLE_DEBUGGER;
*(volatile unsigned long *)(STATUS_BASE) = hardfault_args[0]; // R0
*(volatile unsigned long *)(STATUS_BASE + 0x04) = hardfault_args[1]; // R1
*(volatile unsigned long *)(STATUS_BASE + 0x08) = hardfault_args[2]; // R2
*(volatile unsigned long *)(STATUS_BASE + 0x0C) = hardfault_args[3]; // R3
*(volatile unsigned long *)(STATUS_BASE + 0x10) = hardfault_args[4]; // R12
*(volatile unsigned long *)(STATUS_BASE + 0x14) = hardfault_args[5]; // LR
*(volatile unsigned long *)(STATUS_BASE + 0x18) = hardfault_args[6]; // PC
*(volatile unsigned long *)(STATUS_BASE + 0x1C) = hardfault_args[7]; // PSR
*(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)hardfault_args; // Stack Pointer
*(volatile unsigned long *)(STATUS_BASE ) = hardfault_args[0]; // R0
*(volatile unsigned long *)(STATUS_BASE + 0x04) = hardfault_args[1]; // R1
*(volatile unsigned long *)(STATUS_BASE + 0x08) = hardfault_args[2]; // R2
*(volatile unsigned long *)(STATUS_BASE + 0x0C) = hardfault_args[3]; // R3
*(volatile unsigned long *)(STATUS_BASE + 0x10) = hardfault_args[4]; // R12
*(volatile unsigned long *)(STATUS_BASE + 0x14) = hardfault_args[5]; // LR
*(volatile unsigned long *)(STATUS_BASE + 0x18) = hardfault_args[6]; // PC
*(volatile unsigned long *)(STATUS_BASE + 0x1C) = hardfault_args[7]; // PSR
*(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)hardfault_args; // Stack Pointer
*(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR
*(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR
*(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR
*(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR
*(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR
*(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR
*(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR
*(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR
*(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR
*(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR
*(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR
*(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR
if (VERBOSE_HARDFAULT)
{
printf("HardFault Handler:\r\n");
printf("- R0 = 0x%08lx\r\n", hardfault_args[0]);
printf("- R1 = 0x%08lx\r\n", hardfault_args[1]);
printf("- R2 = 0x%08lx\r\n", hardfault_args[2]);
printf("- R3 = 0x%08lx\r\n", hardfault_args[3]);
printf("- R12 = 0x%08lx\r\n", hardfault_args[4]);
printf("- LR = 0x%08lx\r\n", hardfault_args[5]);
printf("- PC = 0x%08lx\r\n", hardfault_args[6]);
printf("- xPSR= 0x%08lx\r\n", hardfault_args[7]);
if (VERBOSE_HARDFAULT) {
printf("HardFault Handler:\r\n");
printf("- R0 = 0x%08lx\r\n", hardfault_args[0]);
printf("- R1 = 0x%08lx\r\n", hardfault_args[1]);
printf("- R2 = 0x%08lx\r\n", hardfault_args[2]);
printf("- R3 = 0x%08lx\r\n", hardfault_args[3]);
printf("- R12 = 0x%08lx\r\n", hardfault_args[4]);
printf("- LR = 0x%08lx\r\n", hardfault_args[5]);
printf("- PC = 0x%08lx\r\n", hardfault_args[6]);
printf("- xPSR= 0x%08lx\r\n", hardfault_args[7]);
}
hw_cpm_assert_trigger_gpio();
while (1);
}
hw_cpm_assert_trigger_gpio();
while (1);
}
else
{
else {
# ifdef PRODUCTION_DEBUG_OUTPUT
# if (USE_WDOG)
WDOG->WATCHDOG_REG = 0xC8; // Reset WDOG! 200 * 10.24ms active time for UART to finish printing!
WDOG->WATCHDOG_REG = 0xC8; // Reset WDOG! 200 * 10.24ms active time for UART to finish printing!
# endif
dbg_prod_output(1, hardfault_args);
dbg_prod_output(1, hardfault_args);
# endif // PRODUCTION_DEBUG_OUTPUT
hardfault_event_data[0] = HARDFAULT_MAGIC_NUMBER;
hardfault_event_data[1] = hardfault_args[0]; // R0
hardfault_event_data[2] = hardfault_args[1]; // R1
hardfault_event_data[3] = hardfault_args[2]; // R2
hardfault_event_data[4] = hardfault_args[3]; // R3
hardfault_event_data[5] = hardfault_args[4]; // R12
hardfault_event_data[6] = hardfault_args[5]; // LR
hardfault_event_data[7] = hardfault_args[6]; // PC
hardfault_event_data[8] = hardfault_args[7]; // PSR
hardfault_event_data[0] = HARDFAULT_MAGIC_NUMBER;
hardfault_event_data[1] = hardfault_args[0]; // R0
hardfault_event_data[2] = hardfault_args[1]; // R1
hardfault_event_data[3] = hardfault_args[2]; // R2
hardfault_event_data[4] = hardfault_args[3]; // R3
hardfault_event_data[5] = hardfault_args[4]; // R12
hardfault_event_data[6] = hardfault_args[5]; // LR
hardfault_event_data[7] = hardfault_args[6]; // PC
hardfault_event_data[8] = hardfault_args[7]; // PSR
hw_cpm_reboot_system(); // Force reset
hw_cpm_reboot_system(); // Force reset
while (1);
}
while (1);
}
}
/**
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_otpc.c
Vendored
+596 -685
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_qspi.c
Vendored
+86 -104
View File
@@ -54,137 +54,119 @@ __attribute__((section("text_retained")))
#endif
void hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE mode)
{
switch (mode)
{
case HW_QSPI_BUS_MODE_SINGLE:
QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE);
break;
case HW_QSPI_BUS_MODE_DUAL:
QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_DUAL);
break;
case HW_QSPI_BUS_MODE_QUAD:
QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD);
hw_qspi_set_io2_output(false);
hw_qspi_set_io3_output(false);
break;
}
switch (mode) {
case HW_QSPI_BUS_MODE_SINGLE:
QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_SINGLE);
break;
case HW_QSPI_BUS_MODE_DUAL:
QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_DUAL);
break;
case HW_QSPI_BUS_MODE_QUAD:
QSPIC->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_SET_QUAD);
hw_qspi_set_io2_output(false);
hw_qspi_set_io3_output(false);
break;
}
}
__attribute__((section("text_retained"))) void hw_qspi_set_automode(bool automode)
{
if (automode)
{
const uint32_t burst_cmd_a = QSPIC->QSPIC_BURSTCMDA_REG;
const uint32_t burst_cmd_b = QSPIC->QSPIC_BURSTCMDB_REG;
const uint32_t status_cmd = QSPIC->QSPIC_STATUSCMD_REG;
const uint32_t erase_cmd_b = QSPIC->QSPIC_ERASECMDB_REG;
const uint32_t burstbrk = QSPIC->QSPIC_BURSTBRK_REG;
if (GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_INST_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_ADR_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_DMY_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_EXT_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_ERS_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_WEN_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_SUS_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_RES_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_EAD_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTBRK_REG, burstbrk, QSPIC_BRK_TX_MD) == HW_QSPI_BUS_MODE_QUAD)
{
hw_qspi_set_io2_output(false);
hw_qspi_set_io3_output(false);
if (automode) {
const uint32_t burst_cmd_a = QSPIC->QSPIC_BURSTCMDA_REG;
const uint32_t burst_cmd_b = QSPIC->QSPIC_BURSTCMDB_REG;
const uint32_t status_cmd = QSPIC->QSPIC_STATUSCMD_REG;
const uint32_t erase_cmd_b = QSPIC->QSPIC_ERASECMDB_REG;
const uint32_t burstbrk = QSPIC->QSPIC_BURSTBRK_REG;
if (GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_INST_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_ADR_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_DMY_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDA_REG, burst_cmd_a, QSPIC_EXT_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTCMDB_REG, burst_cmd_b, QSPIC_DAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_RX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_STATUSCMD_REG, status_cmd, QSPIC_RSTAT_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_ERS_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_WEN_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_SUS_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_RES_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_ERASECMDB_REG, erase_cmd_b, QSPIC_EAD_TX_MD) == HW_QSPI_BUS_MODE_QUAD ||
GETBITS32(QSPIC, QSPIC_BURSTBRK_REG, burstbrk, QSPIC_BRK_TX_MD) == HW_QSPI_BUS_MODE_QUAD) {
hw_qspi_set_io2_output(false);
hw_qspi_set_io3_output(false);
}
}
}
HW_QSPIC_REG_SETF(CTRLMODE, AUTO_MD, automode);
HW_QSPIC_REG_SETF(CTRLMODE, AUTO_MD, automode);
}
void hw_qspi_set_wrapping_burst_instruction(uint8_t inst, HW_QSPI_WRAP_LEN len,
HW_QSPI_WRAP_SIZE size)
HW_QSPI_WRAP_SIZE size)
{
HW_QSPIC_REG_SETF(BURSTCMDA, INST_WB, inst);
QSPIC->QSPIC_BURSTCMDB_REG =
(QSPIC->QSPIC_BURSTCMDB_REG &
~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE) |
REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN))) |
BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE, size) |
BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN, len) |
BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_MD, 1);
HW_QSPIC_REG_SETF(BURSTCMDA, INST_WB, inst);
QSPIC->QSPIC_BURSTCMDB_REG =
(QSPIC->QSPIC_BURSTCMDB_REG &
~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE) |
REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN))) |
BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_SIZE, size) |
BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_LEN, len) |
BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_WRAP_MD, 1);
}
void hw_qspi_set_dummy_bytes_count(uint8_t count)
{
if (count == 3)
{
HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1);
}
else
{
QSPIC->QSPIC_BURSTCMDB_REG =
(QSPIC->QSPIC_BURSTCMDB_REG &
~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) |
REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) |
BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM,
dummy_num[count]);
}
if (count == 3) {
HW_QSPIC_REG_SETF(BURSTCMDB, DMY_FORCE, 1);
} else {
QSPIC->QSPIC_BURSTCMDB_REG =
(QSPIC->QSPIC_BURSTCMDB_REG &
~(REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE) |
REG_MSK(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM))) |
BITS32(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM,
dummy_num[count]);
}
}
void hw_qspi_erase_block(uint32_t addr)
{
if (!hw_qspi_get_automode())
{
hw_qspi_set_automode(true);
}
if (!hw_qspi_get_automode()) {
hw_qspi_set_automode(true);
}
// Wait for previous erase to end
while (hw_qspi_get_erase_status() != 0) {
}
// Wait for previous erase to end
while (hw_qspi_get_erase_status() != 0)
{
}
if (hw_qspi_get_address_size() == HW_QSPI_ADDR_SIZE_32)
{
addr >>= 12;
}
else
{
addr >>= 4;
}
// Setup erase block page
HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr);
// Fire erase
HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1);
if (hw_qspi_get_address_size() == HW_QSPI_ADDR_SIZE_32) {
addr >>= 12;
} else {
addr >>= 4;
}
// Setup erase block page
HW_QSPIC_REG_SETF(ERASECTRL, ERS_ADDR, addr);
// Fire erase
HW_QSPIC_REG_SETF(ERASECTRL, ERASE_EN, 1);
}
void hw_qspi_set_pads(HW_QSPI_SLEW_RATE rate, HW_QSPI_DRIVE_CURRENT current)
{
QSPIC->QSPIC_GP_REG =
BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_SLEW, rate) |
BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_DRV, current);
QSPIC->QSPIC_GP_REG =
BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_SLEW, rate) |
BITS16(QSPIC, QSPIC_GP_REG, QSPIC_PADS_DRV, current);
}
void hw_qspi_init(const qspi_config *cfg)
{
hw_qspi_enable_clock();
hw_qspi_set_automode(false);
hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE);
hw_qspi_set_io2_output(true);
hw_qspi_set_io2(1);
hw_qspi_set_io3_output(true);
hw_qspi_set_io3(1);
hw_qspi_enable_clock();
hw_qspi_set_automode(false);
hw_qspi_set_bus_mode(HW_QSPI_BUS_MODE_SINGLE);
hw_qspi_set_io2_output(true);
hw_qspi_set_io2(1);
hw_qspi_set_io3_output(true);
hw_qspi_set_io3(1);
if (cfg)
{
hw_qspi_set_address_size(cfg->address_size);
hw_qspi_set_clock_mode(cfg->idle_clock);
hw_qspi_set_read_sampling_edge(cfg->sampling_edge);
}
if (cfg) {
hw_qspi_set_address_size(cfg->address_size);
hw_qspi_set_clock_mode(cfg->idle_clock);
hw_qspi_set_read_sampling_edge(cfg->sampling_edge);
}
}
#endif /* dg_configUSE_HW_QSPI */
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_rf.c
Vendored
+1039 -1127
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_timer0.c
Vendored
+30 -30
View File
@@ -60,58 +60,58 @@ static hw_timer0_interrupt_cb intr_cb;
void hw_timer0_init(const timer0_config *cfg)
{
/* Enable clock for peripheral */
uint32_t clk_tmr_reg = CRG_TOP->CLK_TMR_REG;
clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk;
clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk;
clk_tmr_reg |= CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk;
CRG_TOP->CLK_TMR_REG = clk_tmr_reg ;
/* Enable clock for peripheral */
GLOBAL_INT_DISABLE();
uint32_t clk_tmr_reg = CRG_TOP->CLK_TMR_REG;
clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk;
clk_tmr_reg &= ~CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk;
clk_tmr_reg |= CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk;
CRG_TOP->CLK_TMR_REG = clk_tmr_reg ;
GLOBAL_INT_RESTORE();
/* Reset control register, i.e. disable timer */
GP_TIMERS->TIMER0_CTRL_REG = 0x0;
/* Reset control register, i.e. disable timer */
GP_TIMERS->TIMER0_CTRL_REG = 0x0;
/* Disable NVIC interrupt */
NVIC_DisableIRQ(SWTIM0_IRQn);
/* Disable NVIC interrupt */
NVIC_DisableIRQ(SWTIM0_IRQn);
intr_cb = NULL;
intr_cb = NULL;
hw_timer0_configure(cfg);
hw_timer0_configure(cfg);
}
void hw_timer0_configure(const timer0_config *cfg)
{
if (cfg)
{
hw_timer0_set_clock_source(cfg->clk_src);
hw_timer0_set_fast_clock_div(cfg->fast_clk_div);
hw_timer0_set_on_clock_div(cfg->on_clock_div);
hw_timer0_set_on_reload(cfg->on_reload);
hw_timer0_set_t0_reload(cfg->t0_reload_m, cfg->t0_reload_n);
}
if (cfg) {
hw_timer0_set_clock_source(cfg->clk_src);
hw_timer0_set_fast_clock_div(cfg->fast_clk_div);
hw_timer0_set_on_clock_div(cfg->on_clock_div);
hw_timer0_set_on_reload(cfg->on_reload);
hw_timer0_set_t0_reload(cfg->t0_reload_m, cfg->t0_reload_n);
}
}
void hw_timer0_register_int(hw_timer0_interrupt_cb handler)
{
intr_cb = handler;
NVIC_EnableIRQ(SWTIM0_IRQn);
intr_cb = handler;
NVIC_EnableIRQ(SWTIM0_IRQn);
}
void hw_timer0_unregister_int(void)
{
NVIC_DisableIRQ(SWTIM0_IRQn);
intr_cb = NULL;
NVIC_DisableIRQ(SWTIM0_IRQn);
intr_cb = NULL;
}
void SWTIM0_Handler(void)
{
SEGGER_SYSTEMVIEW_ISR_ENTER();
SEGGER_SYSTEMVIEW_ISR_ENTER();
if (intr_cb)
{
intr_cb();
}
if (intr_cb) {
intr_cb();
}
SEGGER_SYSTEMVIEW_ISR_EXIT();
SEGGER_SYSTEMVIEW_ISR_EXIT();
}
#endif /* dg_configUSE_HW_TIMER0 */
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_trng.c
Vendored
+37 -43
View File
@@ -50,82 +50,76 @@ static hw_trng_cb trng_cb;
void hw_trng_disable_clk(void)
{
GLOBAL_INT_DISABLE();
REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE);
GLOBAL_INT_RESTORE();
GLOBAL_INT_DISABLE();
REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE);
GLOBAL_INT_RESTORE();
}
void hw_trng_clear_pending(void)
{
uint32_t dummy __attribute__((unused));
/* read TRNG_FIFOLVL_REG to clear level-sensitive source. */
dummy = TRNG->TRNG_FIFOLVL_REG;
NVIC_ClearPendingIRQ(TRNG_IRQn);
uint32_t dummy __attribute__((unused));
/* read TRNG_FIFOLVL_REG to clear level-sensitive source. */
dummy = TRNG->TRNG_FIFOLVL_REG;
NVIC_ClearPendingIRQ(TRNG_IRQn);
}
void hw_trng_enable(hw_trng_cb callback)
{
if (callback != NULL)
{
trng_cb = callback;
hw_trng_clear_pending();
NVIC_EnableIRQ(TRNG_IRQn);
}
if (callback != NULL) {
trng_cb = callback;
hw_trng_clear_pending();
NVIC_EnableIRQ(TRNG_IRQn);
}
GLOBAL_INT_DISABLE();
REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE);
GLOBAL_INT_RESTORE();
REG_SET_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE);
GLOBAL_INT_DISABLE();
REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE);
GLOBAL_INT_RESTORE();
REG_SET_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE);
}
void hw_trng_get_numbers(uint32_t *buffer, uint8_t size)
void hw_trng_get_numbers(uint32_t* buffer, uint8_t size)
{
if (size > HW_TRNG_FIFO_DEPTH)
{
size = HW_TRNG_FIFO_DEPTH;
}
if (size > HW_TRNG_FIFO_DEPTH)
size = HW_TRNG_FIFO_DEPTH;
for (int i = 0; i < size ; i++)
{
buffer[i] = hw_trng_get_number();
}
for (int i = 0; i < size ; i++) {
buffer[i] = hw_trng_get_number();
}
}
__RETAINED_CODE uint8_t hw_trng_get_fifo_level(void)
{
return (TRNG->TRNG_FIFOLVL_REG) & (REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOLVL) |
REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOFULL));
return (TRNG->TRNG_FIFOLVL_REG) & (REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOLVL) |
REG_MSK(TRNG, TRNG_FIFOLVL_REG, TRNG_FIFOFULL));
}
void hw_trng_disable_interrupt(void)
{
NVIC_DisableIRQ(TRNG_IRQn);
trng_cb = NULL;
NVIC_DisableIRQ(TRNG_IRQn);
trng_cb = NULL;
}
void hw_trng_disable(void)
{
hw_trng_stop();
hw_trng_disable_interrupt();
hw_trng_clear_pending();
hw_trng_disable_clk();
hw_trng_stop();
hw_trng_disable_interrupt();
hw_trng_clear_pending();
hw_trng_disable_clk();
}
void TRNG_Handler(void)
{
uint32_t dummy __attribute__((unused));
uint32_t dummy __attribute__((unused));
SEGGER_SYSTEMVIEW_ISR_ENTER();
SEGGER_SYSTEMVIEW_ISR_ENTER();
if (trng_cb != NULL)
{
trng_cb();
}
if (trng_cb != NULL)
trng_cb();
/* read TRNG_FIFOLVL_REG to clear level-sensitive source. */
dummy = TRNG->TRNG_FIFOLVL_REG;
/* read TRNG_FIFOLVL_REG to clear level-sensitive source. */
dummy = TRNG->TRNG_FIFOLVL_REG;
SEGGER_SYSTEMVIEW_ISR_EXIT();
SEGGER_SYSTEMVIEW_ISR_EXIT();
}
#endif /* dg_configUSE_HW_TRNG */
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_uart.c
Vendored
+895 -1049
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/bsp/peripherals/src/hw_watchdog.c
Vendored
+62 -71
View File
@@ -62,101 +62,94 @@ static hw_watchdog_interrupt_cb int_handler __RETAINED = NULL;
bool hw_watchdog_freeze(void)
{
GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk;
GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk;
return !REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST);
return !REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST);
}
void hw_watchdog_unfreeze(void)
{
GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk;
GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk;
}
HW_WDG_RESET hw_watchdog_is_irq_or_rst_gen(void)
{
if (REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST))
{
return HW_WDG_RESET_RST;
}
if (REG_GETF(WDOG, WATCHDOG_CTRL_REG, NMI_RST)) {
return HW_WDG_RESET_RST;
}
return HW_WDG_RESET_NMI;
return HW_WDG_RESET_NMI;
}
void hw_watchdog_register_int(hw_watchdog_interrupt_cb handler)
{
int_handler = handler;
int_handler = handler;
}
void hw_watchdog_unregister_int(void)
{
int_handler = NULL;
int_handler = NULL;
}
__RETAINED_CODE void hw_watchdog_handle_int(unsigned long *exception_args)
{
// Reached this point due to a WDOG timeout
uint16_t pmu_ctrl_reg = CRG_TOP->PMU_CTRL_REG;
pmu_ctrl_reg |= ((1 << CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos) | /* turn off BLE */
(1 << CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos) | /* turn off FTDF */
(1 << CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos) | /* turn off radio PD */
(1 << CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos)); /* turn off peripheral power domain */
CRG_TOP->PMU_CTRL_REG = pmu_ctrl_reg;
REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, BLE_LP_RESET); /* reset the BLE LP timer */
// Reached this point due to a WDOG timeout
uint16_t pmu_ctrl_reg = CRG_TOP->PMU_CTRL_REG;
pmu_ctrl_reg |= ((1 << CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos) | /* turn off BLE */
(1 << CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos) | /* turn off FTDF */
(1 << CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos) | /* turn off radio PD */
(1 << CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos)); /* turn off peripheral power domain */
CRG_TOP->PMU_CTRL_REG = pmu_ctrl_reg;
REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, BLE_LP_RESET); /* reset the BLE LP timer */
#if (dg_configIMAGE_SETUP == DEVELOPMENT_MODE)
hw_watchdog_freeze(); // Stop WDOG
hw_watchdog_freeze(); // Stop WDOG
ENABLE_DEBUGGER;
ENABLE_DEBUGGER;
if (exception_args != NULL)
{
*(volatile unsigned long *)(STATUS_BASE) = exception_args[0]; // R0
*(volatile unsigned long *)(STATUS_BASE + 0x04) = exception_args[1]; // R1
*(volatile unsigned long *)(STATUS_BASE + 0x08) = exception_args[2]; // R2
*(volatile unsigned long *)(STATUS_BASE + 0x0C) = exception_args[3]; // R3
*(volatile unsigned long *)(STATUS_BASE + 0x10) = exception_args[4]; // R12
*(volatile unsigned long *)(STATUS_BASE + 0x14) = exception_args[5]; // LR
*(volatile unsigned long *)(STATUS_BASE + 0x18) = exception_args[6]; // PC
*(volatile unsigned long *)(STATUS_BASE + 0x1C) = exception_args[7]; // PSR
*(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)exception_args; // Stack Pointer
if (exception_args != NULL) {
*(volatile unsigned long *)(STATUS_BASE ) = exception_args[0]; // R0
*(volatile unsigned long *)(STATUS_BASE + 0x04) = exception_args[1]; // R1
*(volatile unsigned long *)(STATUS_BASE + 0x08) = exception_args[2]; // R2
*(volatile unsigned long *)(STATUS_BASE + 0x0C) = exception_args[3]; // R3
*(volatile unsigned long *)(STATUS_BASE + 0x10) = exception_args[4]; // R12
*(volatile unsigned long *)(STATUS_BASE + 0x14) = exception_args[5]; // LR
*(volatile unsigned long *)(STATUS_BASE + 0x18) = exception_args[6]; // PC
*(volatile unsigned long *)(STATUS_BASE + 0x1C) = exception_args[7]; // PSR
*(volatile unsigned long *)(STATUS_BASE + 0x20) = (unsigned long)exception_args; // Stack Pointer
*(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR
*(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR
*(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR
*(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR
*(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR
*(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR
}
*(volatile unsigned long *)(STATUS_BASE + 0x24) = (*((volatile unsigned long *)(0xE000ED28))); // CFSR
*(volatile unsigned long *)(STATUS_BASE + 0x28) = (*((volatile unsigned long *)(0xE000ED2C))); // HFSR
*(volatile unsigned long *)(STATUS_BASE + 0x2C) = (*((volatile unsigned long *)(0xE000ED30))); // DFSR
*(volatile unsigned long *)(STATUS_BASE + 0x30) = (*((volatile unsigned long *)(0xE000ED3C))); // AFSR
*(volatile unsigned long *)(STATUS_BASE + 0x34) = (*((volatile unsigned long *)(0xE000ED34))); // MMAR
*(volatile unsigned long *)(STATUS_BASE + 0x38) = (*((volatile unsigned long *)(0xE000ED38))); // BFAR
}
hw_cpm_assert_trigger_gpio();
hw_cpm_assert_trigger_gpio();
if (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE))
{
__BKPT(0);
}
else
{
while (1);
}
if (REG_GETF(CRG_TOP, SYS_STAT_REG, DBG_IS_ACTIVE)) {
__BKPT(0);
}
else {
while (1);
}
#else // dg_configIMAGE_SETUP == DEVELOPMENT_MODE
if (exception_args != NULL) {
nmi_event_data[0] = NMI_MAGIC_NUMBER;
nmi_event_data[1] = exception_args[0]; // R0
nmi_event_data[2] = exception_args[1]; // R1
nmi_event_data[3] = exception_args[2]; // R2
nmi_event_data[4] = exception_args[3]; // R3
nmi_event_data[5] = exception_args[4]; // R12
nmi_event_data[6] = exception_args[5]; // LR
nmi_event_data[7] = exception_args[6]; // PC
nmi_event_data[8] = exception_args[7]; // PSR
}
if (exception_args != NULL)
{
nmi_event_data[0] = NMI_MAGIC_NUMBER;
nmi_event_data[1] = exception_args[0]; // R0
nmi_event_data[2] = exception_args[1]; // R1
nmi_event_data[3] = exception_args[2]; // R2
nmi_event_data[4] = exception_args[3]; // R3
nmi_event_data[5] = exception_args[4]; // R12
nmi_event_data[6] = exception_args[5]; // LR
nmi_event_data[7] = exception_args[6]; // PC
nmi_event_data[8] = exception_args[7]; // PSR
}
// Wait for the reset to occur
while (1);
// Wait for the reset to occur
while (1);
#endif // dg_configIMAGE_SETUP == DEVELOPMENT_MODE
}
@@ -164,14 +157,12 @@ __RETAINED_CODE void NMI_HandlerC(unsigned long *exception_args);
void NMI_HandlerC(unsigned long *exception_args)
{
if (int_handler)
{
int_handler(exception_args);
}
else
{
hw_watchdog_handle_int(exception_args);
}
if (int_handler) {
int_handler(exception_args);
}
else {
hw_watchdog_handle_int(exception_args);
}
}
/**
third_party/dialog/DialogSDK/bsp/peripherals/src/sys_tcs.c
Vendored
+230 -279
View File
@@ -8,7 +8,7 @@
*/
/**
****************************************************************************************
****************************************************************************************
*
* @file sys_tcs.c
*
@@ -16,37 +16,36 @@
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
****************************************************************************************
*/
#include <stdint.h>
#include "hw_cpm.h"
#include "sys_tcs.h"
#include "hw_gpadc.h"
#include "hw_gpio.h"
#define APPEND_TCS_LENGTH (0)
@@ -78,58 +77,57 @@ bool sys_tcs_is_calibrated_chip __RETAINED_UNINIT; // Initial value: false
* Local variables
*/
static const uint32_t uncalibrated_tcs_data[] =
{
/* BANDGAP_REG: (offset 0)
* [14]: BYPASS_COLD_BOOT_DISABLE = 0
* [13:10]: LDO_SLEEP_TRIM = 0x4
* [9:5]: BGR_ITRIM = 0x00
* [4:0]: BGR_TRIM = 0x13 (change until V12 is 1.2V)
*
* Especially for this register, merge the trimmed and preferred settings.
*/
(uint32_t) &CRG_TOP->BANDGAP_REG, 0x1013,
static const uint32_t uncalibrated_tcs_data[] = {
/* BANDGAP_REG: (offset 0)
* [14]: BYPASS_COLD_BOOT_DISABLE = 0
* [13:10]: LDO_SLEEP_TRIM = 0x4
* [9:5]: BGR_ITRIM = 0x00
* [4:0]: BGR_TRIM = 0x13 (change until V12 is 1.2V)
*
* Especially for this register, merge the trimmed and preferred settings.
*/
(uint32_t)&CRG_TOP->BANDGAP_REG, 0x1013,
/* CLK_FREQ_TRIM_REG: (offset 2)
* [10:8]: COARSE_ADJ = 0x4
* [7:0]: FINE_ADJ = 0x60
*/
(uint32_t) &CRG_TOP->CLK_FREQ_TRIM_REG, 0x0460,
/* CLK_FREQ_TRIM_REG: (offset 2)
* [10:8]: COARSE_ADJ = 0x4
* [7:0]: FINE_ADJ = 0x60
*/
(uint32_t)&CRG_TOP->CLK_FREQ_TRIM_REG, 0x0460,
/* CLK_16M_REG: (offset 4)
* [15]: RC16M_STARTUP_DISABLE = 0
* [14]: XTAL16_HPASS_FLT_EN = 0
* [13]: XTAL16_SPIKE_FLT_BYPASS = 0
* [12:10]: XTAL16_AMP_TRIM = 0x5
* [9]: XTAL16_EXT_CLK_ENABLE = 0
* [8]: XTAL16_MAX_CURRENT = 0
* [7:5]: XTAL16_CUR_SET = 0x5
* [4:1]: RC16M_TRIM = 0x9
* [0]: RC16M_ENABLE = 0
*
* Apply the trimmed and a default preferred value. The correct one is applied
* later.
*/
(uint32_t) &CRG_TOP->CLK_16M_REG, 0x14B2,
/* CLK_16M_REG: (offset 4)
* [15]: RC16M_STARTUP_DISABLE = 0
* [14]: XTAL16_HPASS_FLT_EN = 0
* [13]: XTAL16_SPIKE_FLT_BYPASS = 0
* [12:10]: XTAL16_AMP_TRIM = 0x5
* [9]: XTAL16_EXT_CLK_ENABLE = 0
* [8]: XTAL16_MAX_CURRENT = 0
* [7:5]: XTAL16_CUR_SET = 0x5
* [4:1]: RC16M_TRIM = 0x9
* [0]: RC16M_ENABLE = 0
*
* Apply the trimmed and a default preferred value. The correct one is applied
* later.
*/
(uint32_t)&CRG_TOP->CLK_16M_REG, 0x14B2,
/* CLK_32K_REG: (offset 6)
* [15:13]: 0
* [12]: XTAL32K_DISABLE_AMPREG0 = 0
* [11:8]: RC32K_TRIM = 0x07
* [7]: RC32K_ENABLE = 0x1 (reset value)
* [6:3]: XTAL32K_CUR = 0x3 (reset value)
* [2:1]: XTAL32K_RBIAS = 0x2 (reset value)
* [0]: XTAL32K_ENABLE = 0
*/
(uint32_t) &CRG_TOP->CLK_32K_REG, 0x79C,
/* CLK_32K_REG: (offset 6)
* [15:13]: 0
* [12]: XTAL32K_DISABLE_AMPREG0 = 0
* [11:8]: RC32K_TRIM = 0x07
* [7]: RC32K_ENABLE = 0x1 (reset value)
* [6:3]: XTAL32K_CUR = 0x3 (reset value)
* [2:1]: XTAL32K_RBIAS = 0x2 (reset value)
* [0]: XTAL32K_ENABLE = 0
*/
(uint32_t)&CRG_TOP->CLK_32K_REG, 0x79C,
/* CHARGER_CTRL2_REG: (offset 8)
* [15:13]: 0
* [12:8]: CURRENT_OFFSET_TRIM = 0x0C
* [7:4]: CHARGER_VFLOAT_ADJ = 0x5
* [3:0]: CURRENT_GAIN_TRIM = 0xA
*/
(uint32_t) &ANAMISC->CHARGER_CTRL2_REG, 0x0C5A,
/* CHARGER_CTRL2_REG: (offset 8)
* [15:13]: 0
* [12:8]: CURRENT_OFFSET_TRIM = 0x0C
* [7:4]: CHARGER_VFLOAT_ADJ = 0x5
* [3:0]: CURRENT_GAIN_TRIM = 0xA
*/
(uint32_t)&ANAMISC->CHARGER_CTRL2_REG, 0x0C5A,
};
#define UNCALIBRATED_DATA_NON_RETAINED_OFFSET (8)
@@ -176,14 +174,12 @@ static const uint32_t uncalibrated_tcs_data[] =
*/
static void apply_pair(uint32_t address, uint32_t value)
{
if (address & 0x2)
{
*(volatile uint16_t *)address = value;
}
else
{
*(volatile uint32_t *)address = value;
}
if (address & 0x2) {
*(volatile uint16_t *)address = value;
}
else {
*(volatile uint32_t *)address = value;
}
}
/**
@@ -195,17 +191,15 @@ static void apply_pair(uint32_t address, uint32_t value)
*/
static void apply_entry(uint8_t index)
{
uint32_t address = tcs_ptr[index];
uint32_t value = tcs_ptr[index + 1];
uint32_t address = tcs_ptr[index];
uint32_t value = tcs_ptr[index + 1];
if (address & 0x2)
{
*(volatile uint16_t *)address = value;
}
else
{
*(volatile uint32_t *)address = value;
}
if (address & 0x2) {
*(volatile uint16_t *)address = value;
}
else {
*(volatile uint32_t *)address = value;
}
}
/**
@@ -217,10 +211,10 @@ static void apply_entry(uint8_t index)
*/
static void store_in_array(uint32_t address, uint32_t value)
{
tcs_data[tcs_length] = address;
tcs_length++;
tcs_data[tcs_length] = value;
tcs_length++;
tcs_data[tcs_length] = address;
tcs_length++;
tcs_data[tcs_length] = value;
tcs_length++;
}
/**
@@ -234,15 +228,15 @@ static void store_in_array(uint32_t address, uint32_t value)
*/
static void swap_entries(uint32_t first_pos, uint32_t second_pos)
{
uint32_t address_stored;
uint32_t value_stored;
uint32_t address_stored;
uint32_t value_stored;
address_stored = tcs_data[second_pos];
value_stored = tcs_data[second_pos + 1];
tcs_data[second_pos] = tcs_data[first_pos];
tcs_data[second_pos + 1] = tcs_data[first_pos + 1];
tcs_data[first_pos] = address_stored;
tcs_data[first_pos + 1] = value_stored;
address_stored = tcs_data[second_pos];
value_stored = tcs_data[second_pos + 1];
tcs_data[second_pos] = tcs_data[first_pos];
tcs_data[second_pos + 1] = tcs_data[first_pos + 1];
tcs_data[first_pos] = address_stored;
tcs_data[first_pos + 1] = value_stored;
}
/**
@@ -260,240 +254,197 @@ static void swap_entries(uint32_t first_pos, uint32_t second_pos)
*/
static int sys_tcs_sort_area(uint32_t area_base, uint32_t area_size, uint32_t array_ptr, uint8_t *ptr, uint8_t *size)
{
uint32_t i = array_ptr;
uint32_t sort_start;
uint32_t sort_end;
uint32_t i = array_ptr;
uint32_t sort_start;
uint32_t sort_end;
if (array_ptr == tcs_length)
{
return array_ptr; // Nothing else is left in the array or tcs_length is zero
}
sort_start = array_ptr;
sort_end = array_ptr;
/* Make sure that the values in TCS don't overflow the allocated array */
ASSERT_WARNING(tcs_length <= sizeof(tcs_data) / sizeof(tcs_data[0]));
while (i < (tcs_length - 1))
{
if (IS_IN_AREA(tcs_data[i], area_base, area_size))
{
if (i == array_ptr)
{
if (sort_start == array_ptr)
{
sort_start = array_ptr;
sort_end = sort_start + 2;
}
}
else
{
// Copy it to the proper place.
if (i != sort_end)
{
swap_entries(sort_end, i);
}
sort_end += 2;
}
if (array_ptr == tcs_length) {
return array_ptr; // Nothing else is left in the array or tcs_length is zero
}
i += 2;
}
sort_start = array_ptr;
sort_end = array_ptr;
*ptr = sort_start;
*size = sort_end - sort_start;
/* Make sure that the values in TCS don't overflow the allocated array */
ASSERT_WARNING(tcs_length <= sizeof(tcs_data)/sizeof(tcs_data[0]));
return sort_end;
while (i < (tcs_length - 1)) {
if (IS_IN_AREA(tcs_data[i], area_base, area_size)) {
if (i == array_ptr) {
if (sort_start == array_ptr) {
sort_start = array_ptr;
sort_end = sort_start + 2;
}
}
else {
// Copy it to the proper place.
if (i != sort_end) {
swap_entries(sort_end, i);
}
sort_end += 2;
}
}
i += 2;
}
*ptr = sort_start;
*size = sort_end - sort_start;
return sort_end;
}
void sys_tcs_init(void)
{
tcs_length = 0;
sys_tcs_is_calibrated_chip = false;
hw_cpm_bod_enabled_in_tcs = 0;
tcs_length = 0;
sys_tcs_is_calibrated_chip = false;
hw_cpm_bod_enabled_in_tcs = 0;
}
bool sys_tcs_store_pair(uint32_t address, uint32_t value)
{
// If it stops here then tcs_length must become uint16_t.
ASSERT_WARNING((256 * sizeof(tcs_length)) >= (24 * 2 + APPEND_TCS_LENGTH));
// If it stops here then tcs_length must become uint16_t.
ASSERT_WARNING( (256 * sizeof(tcs_length)) >= (24 * 2 + APPEND_TCS_LENGTH) );
// Check if the address is in Always-ON or of a retained register and apply it.
if (IS_IN_AREA(address, CRG_TOP_BASE, sizeof(CRG_TOP_Type))
|| IS_IN_AREA(address, TIMER1_BASE, sizeof(TIMER1_Type))
|| IS_IN_AREA(address, WAKEUP_BASE, sizeof(WAKEUP_Type))
|| IS_IN_AREA(address, DCDC_BASE, sizeof(DCDC_Type))
|| IS_IN_AREA(address, QSPIC_BASE, sizeof(QSPIC_Type))
|| IS_IN_AREA(address, CACHE_BASE, sizeof(CACHE_Type))
|| IS_IN_AREA(address, OTPC_BASE, sizeof(OTPC_Type)))
{
if (address == (uint32_t)&CRG_TOP->BANDGAP_REG)
{
sys_tcs_is_calibrated_chip = true;
}
else if (address == (uint32_t)&CRG_TOP->CLK_16M_REG)
{
value |= CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk; // Make sure that RC16 is enabled!
}
else if (address == (uint32_t)&CRG_TOP->XTALRDY_CTRL_REG)
{
sys_tcs_xtal16m_settling_time = value;
}
else if (address == (uint32_t)&CRG_TOP->BOD_CTRL2_REG)
{
hw_cpm_bod_enabled_in_tcs = value;
/*
* Read the ADC Gain Error. Given that the Chip Configuration Section
* (CCS) of OTP is out of space, the values are stored in the TCS section
* using as address the read-only register SYS_STAT_REG.
* The 16 LSB of the 32bit data-value is the single ended gain error.
* The 16 MSB of the 32bit data-value is the differential gain error.
* Both gain error values should be interpreted as signed 16bit integers.
*/
}
else if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1)
{
if (address == (uint32_t)&CRG_TOP->SYS_STAT_REG)
{
hw_gpadc_store_se_gain_error(ADC_SE_GAIN_ERROR(value));
hw_gpadc_store_diff_gain_error(ADC_DIFF_GAIN_ERROR(value));
}
// Check if the address is in Always-ON or of a retained register and apply it.
if (IS_IN_AREA(address, CRG_TOP_BASE, sizeof(CRG_TOP_Type))
|| IS_IN_AREA(address, TIMER1_BASE, sizeof(TIMER1_Type))
|| IS_IN_AREA(address, WAKEUP_BASE, sizeof(WAKEUP_Type))
|| IS_IN_AREA(address, DCDC_BASE, sizeof(DCDC_Type))
|| IS_IN_AREA(address, QSPIC_BASE, sizeof(QSPIC_Type))
|| IS_IN_AREA(address, CACHE_BASE, sizeof(CACHE_Type))
|| IS_IN_AREA(address, OTPC_BASE, sizeof(OTPC_Type))) {
if (address == (uint32_t)&CRG_TOP->BANDGAP_REG) {
sys_tcs_is_calibrated_chip = true;
} else if (address == (uint32_t)&CRG_TOP->CLK_16M_REG) {
value |= CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk; // Make sure that RC16 is enabled!
} else if (address == (uint32_t)&CRG_TOP->XTALRDY_CTRL_REG) {
sys_tcs_xtal16m_settling_time = value;
} else if (address == (uint32_t)&CRG_TOP->BOD_CTRL2_REG) {
hw_cpm_bod_enabled_in_tcs = value;
/*
* Read the ADC Gain Error. Given that the Chip Configuration Section
* (CCS) of OTP is out of space, the values are stored in the TCS section
* using as address the read-only register SYS_STAT_REG.
* The 16 LSB of the 32bit data-value is the single ended gain error.
* The 16 MSB of the 32bit data-value is the differential gain error.
* Both gain error values should be interpreted as signed 16bit integers.
*/
} else if (dg_configUSE_ADC_GAIN_ERROR_CORRECTION == 1) {
if (address == (uint32_t)&CRG_TOP->SYS_STAT_REG) {
hw_gpadc_store_se_gain_error(ADC_SE_GAIN_ERROR(value));
hw_gpadc_store_diff_gain_error(ADC_DIFF_GAIN_ERROR(value));
}
}
apply_pair(address, value);
} else {
store_in_array(address, value);
}
apply_pair(address, value);
}
else
{
store_in_array(address, value);
}
return sys_tcs_is_calibrated_chip;
return sys_tcs_is_calibrated_chip;
}
void sys_tcs_sort_array(void)
{
int entry_ptr = 0;
int i;
int entry_ptr = 0;
int i;
/*
* Apply a default value to CLK_FREQ_TRIM_REG, if not set in TCS.
* [10:8]: COARSE_ADJ = 0x4
* [7:0]: FINE_ADJ = 0x60
*/
if (CRG_TOP->CLK_FREQ_TRIM_REG == 0)
{
CRG_TOP->CLK_FREQ_TRIM_REG = 0x0460;
}
/*
* Apply a default value to CLK_FREQ_TRIM_REG, if not set in TCS.
* [10:8]: COARSE_ADJ = 0x4
* [7:0]: FINE_ADJ = 0x60
*/
if (CRG_TOP->CLK_FREQ_TRIM_REG == 0) {
CRG_TOP->CLK_FREQ_TRIM_REG = 0x0460;
}
if (sys_tcs_is_calibrated_chip)
{
if (sys_tcs_is_calibrated_chip) {
#ifdef CONFIG_USE_BLE
entry_ptr = sys_tcs_sort_area(BLE_BASE, sizeof(BLE_Type), entry_ptr,
&area_offset[tcs_ble], &area_size[tcs_ble]);
entry_ptr = sys_tcs_sort_area(BLE_BASE, sizeof(BLE_Type), entry_ptr,
&area_offset[tcs_ble], &area_size_global[tcs_ble]);
#endif
#ifdef CONFIG_USE_FTDF
entry_ptr = sys_tcs_sort_area(FTDF_BASE, sizeof(FTDF_Type), entry_ptr,
&area_offset[tcs_ftdf], &area_size_global[tcs_ftdf]);
entry_ptr = sys_tcs_sort_area(FTDF_BASE, sizeof(FTDF_Type), entry_ptr,
&area_offset[tcs_ftdf], &area_size_global[tcs_ftdf]);
#endif
entry_ptr = sys_tcs_sort_area(RFCU_BASE, RADIO_AREA_SIZE, entry_ptr,
&area_offset[tcs_radio], &area_size_global[tcs_radio]);
entry_ptr = sys_tcs_sort_area(RFCU_BASE, RADIO_AREA_SIZE, entry_ptr,
&area_offset[tcs_radio], &area_size_global[tcs_radio]);
entry_ptr = sys_tcs_sort_area((uint32_t)&ANAMISC->CHARGER_CTRL2_REG, 1, entry_ptr,
&area_offset[tcs_charger], &area_size_global[tcs_charger]);
entry_ptr = sys_tcs_sort_area((uint32_t)&ANAMISC->CHARGER_CTRL2_REG, 1, entry_ptr,
&area_offset[tcs_charger], &area_size_global[tcs_charger]);
entry_ptr = sys_tcs_sort_area(APU_BASE, sizeof(APU_Type), entry_ptr,
&area_offset[tcs_audio], &area_size_global[tcs_audio]);
entry_ptr = sys_tcs_sort_area(APU_BASE, sizeof(APU_Type), entry_ptr,
&area_offset[tcs_audio], &area_size_global[tcs_audio]);
// The rest should be System. Assert if not!
for (i = entry_ptr; i < tcs_length; i += 2)
{
if (IS_IN_AREA(tcs_data[i], UART_BASE, PERIPHERAL_AREA_SIZE))
{
ASSERT_WARNING(0);
}
// The rest should be System. Assert if not!
for (i = entry_ptr; i < tcs_length; i += 2) {
if (IS_IN_AREA(tcs_data[i], UART_BASE, PERIPHERAL_AREA_SIZE)) {
ASSERT_WARNING(0);
}
if (IS_IN_AREA(tcs_data[i], CRG_TOP_BASE, 0x6100))
{
// It is ok (most probably).
}
else
{
ASSERT_WARNING(0);
}
if (IS_IN_AREA(tcs_data[i], CRG_TOP_BASE, 0x6100)) {
// It is ok (most probably).
}
else {
ASSERT_WARNING(0);
}
}
area_offset[tcs_system] = entry_ptr;
area_size_global[tcs_system] = tcs_length - entry_ptr;
tcs_ptr = tcs_data;
}
else {
tcs_ptr = uncalibrated_tcs_data;
area_offset[tcs_system] = entry_ptr;
area_size_global[tcs_system] = tcs_length - entry_ptr;
tcs_ptr = tcs_data;
}
else
{
tcs_ptr = uncalibrated_tcs_data;
for (i = 0; i < UNCALIBRATED_DATA_NON_RETAINED_OFFSET; i += 2)
{
apply_pair(tcs_ptr[i], tcs_ptr[i + 1]);
}
for (i = 0; i < UNCALIBRATED_DATA_NON_RETAINED_OFFSET; i += 2) {
apply_pair(tcs_ptr[i], tcs_ptr[i + 1]);
}
#ifdef CONFIG_USE_BLE
if (UNCALIBRATED_DATA_BLE_SIZE > 0)
{
area_offset[tcs_ble] = UNCALIBRATED_DATA_BLE_OFFSET;
area_size[tcs_ble] = UNCALIBRATED_DATA_BLE_SIZE;
}
if (UNCALIBRATED_DATA_BLE_SIZE > 0) {
area_offset[tcs_ble] = UNCALIBRATED_DATA_BLE_OFFSET;
area_size_global[tcs_ble] = UNCALIBRATED_DATA_BLE_SIZE;
}
#endif
#ifdef CONFIG_USE_FTDF
if (UNCALIBRATED_DATA_FTDF_SIZE > 0)
{
area_offset[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_OFFSET;
area_size_global[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_SIZE;
}
if (UNCALIBRATED_DATA_FTDF_SIZE > 0) {
area_offset[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_OFFSET;
area_size_global[tcs_ftdf] = UNCALIBRATED_DATA_FTDF_SIZE;
}
#endif
if (UNCALIBRATED_DATA_RADIO_SIZE > 0)
{
area_offset[tcs_radio] = UNCALIBRATED_DATA_RADIO_OFFSET;
area_size_global[tcs_radio] = UNCALIBRATED_DATA_RADIO_SIZE;
}
if (UNCALIBRATED_DATA_RADIO_SIZE > 0) {
area_offset[tcs_radio] = UNCALIBRATED_DATA_RADIO_OFFSET;
area_size_global[tcs_radio] = UNCALIBRATED_DATA_RADIO_SIZE;
}
if (UNCALIBRATED_DATA_CHARGER_SIZE > 0)
{
area_offset[tcs_charger] = UNCALIBRATED_DATA_CHARGER_OFFSET;
area_size_global[tcs_charger] = UNCALIBRATED_DATA_CHARGER_SIZE;
}
if (UNCALIBRATED_DATA_CHARGER_SIZE > 0) {
area_offset[tcs_charger] = UNCALIBRATED_DATA_CHARGER_OFFSET;
area_size_global[tcs_charger] = UNCALIBRATED_DATA_CHARGER_SIZE;
}
if (UNCALIBRATED_DATA_AUDIO_SIZE > 0)
{
area_offset[tcs_audio] = UNCALIBRATED_DATA_AUDIO_OFFSET;
area_size_global[tcs_audio] = UNCALIBRATED_DATA_AUDIO_SIZE;
}
if (UNCALIBRATED_DATA_AUDIO_SIZE > 0) {
area_offset[tcs_audio] = UNCALIBRATED_DATA_AUDIO_OFFSET;
area_size_global[tcs_audio] = UNCALIBRATED_DATA_AUDIO_SIZE;
}
if (UNCALIBRATED_DATA_SYSTEM_SIZE > 0)
{
area_offset[tcs_system] = UNCALIBRATED_DATA_SYSTEM_OFFSET;
area_size_global[tcs_system] = UNCALIBRATED_DATA_SYSTEM_SIZE;
if (UNCALIBRATED_DATA_SYSTEM_SIZE > 0) {
area_offset[tcs_system] = UNCALIBRATED_DATA_SYSTEM_OFFSET;
area_size_global[tcs_system] = UNCALIBRATED_DATA_SYSTEM_SIZE;
}
}
}
}
void sys_tcs_apply(sys_tcs_area_t area)
{
int i;
int i;
for (i = area_offset[area]; i < (area_offset[area] + area_size_global[area]); i += 2)
{
apply_entry(i);
}
for (i = area_offset[area]; i < (area_offset[area] + area_size_global[area]); i += 2) {
apply_entry(i);
}
}
/**
third_party/dialog/DialogSDK/bsp/startup/config.c
Vendored
+33 -15
View File
@@ -1,19 +1,37 @@
/**
****************************************************************************************
*
* @file config.c
*
* @brief Configure system.
*
* Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer
* program includes Confidential, Proprietary Information and is a Trade Secret of
* Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited
* unless authorized in writing. All Rights Reserved.
*
* <[email protected]> and contributors.
*
****************************************************************************************
*/
****************************************************************************************
*
* @file config.c
*
* @brief Configure system.
*
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
****************************************************************************************
*/
/**
\addtogroup BSP
third_party/dialog/DialogSDK/bsp/startup/system_ARMCM0.c
Vendored
+2 -2
View File
@@ -203,7 +203,7 @@ static bool apply_trim_values_from_otp(uint32_t *tcs_array, uint32_t *valid_entr
if ((address == 0) && (value == 0)) {
if ((BLACK_ORCA_TARGET_IC >= BLACK_ORCA_IC_VERSION(A, E))
|| ((dg_configUSE_AUTO_CHIP_DETECTION == 1)
&& (CHIP_IS_AE || CHIP_IS_BA))) {
&& (CHIP_IS_AE || CHIP_IS_BB))) {
if (!forward_reading) {
break;
}
@@ -429,7 +429,7 @@ void SystemInit(void)
if (dg_configUSE_AUTO_CHIP_DETECTION == 1) {
black_orca_chip_version = black_orca_get_chip_version();
if (!CHIP_IS_AE && !CHIP_IS_BA) {
if (!CHIP_IS_AE && !CHIP_IS_BB) {
// Oldest supported version is AE.
ASSERT_WARNING_UNINIT(0);
}
third_party/dialog/DialogSDK/bsp/startup/vector_table.S
Vendored
+24 -5
View File
@@ -5,15 +5,34 @@
*
* @brief Interrupt Vector Table and Patch Table
*
* Copyright (C) 2015. Dialog Semiconductor, unpublished work. This computer
* program includes Confidential, Proprietary Information and is a Trade Secret of
* Dialog Semiconductor. All use, disclosure, and/or reproduction is prohibited
* unless authorized in writing. All Rights Reserved.
* Copyright (c) 2016, Dialog Semiconductor
* All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* <black.orca.support@diasemi.com> and contributors.
*
****************************************************************************************
*/
.syntax unified
.arch armv6-m
third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_config.h
Vendored
+2 -1
View File
@@ -7,6 +7,7 @@
/**
****************************************************************************************
*
* @file ad_ftdf_config.h
*
* @brief FTDF Adapter API
@@ -105,7 +106,7 @@
* \brief Sleep value compensation
*
* Defines the sleep value compensation expressed in microseconds. This value
* is subtracted from the sleep time returned by FTDF_canSleep( )
* is subtracted from the sleep time returned by ftdf_can_sleep()
*/
#define AD_FTDF_SLEEP_COMPENSATION 1500
third_party/dialog/DialogSDK/interfaces/ftdf/include/ad_ftdf_phy_api.h
Vendored
+25 -12
View File
@@ -7,6 +7,7 @@
/**
****************************************************************************************
*
* @file ad_ftdf_phy_api.h
*
* @brief FTDF PHY Adapter API
@@ -58,7 +59,7 @@ void ad_ftdf_init(void);
*
* \param[in] address - The extended address to set
*/
void ad_ftdf_setExtAddress( FTDF_ExtAddress address);
void ad_ftdf_set_ext_address(ftdf_ext_address_t address);
/**
* \brief Get Extended Address
@@ -67,24 +68,24 @@ void ad_ftdf_setExtAddress( FTDF_ExtAddress address);
*
* \returns The extended address of the interface
*/
FTDF_ExtAddress ad_ftdf_getExtAddress( void);
ftdf_ext_address_t ad_ftdf_get_ext_address(void);
/**
* \brief Transmits a frame
*
* Transmits a frame. Params:
*
* \param[in] frameLength - The total length of the frame passed in bytes
* \param[in] frame_length - The total length of the frame passed in bytes
* \param[in] frame - a pointer to the passed frame buffer
* \param[in] channel - The channel to use for transmission in [11, 26]
* \param[in] csmaSuppress - If true, csma protocol (i.e. CCA) will not be performed
* \param[in] csma_suppress - If true, csma protocol (i.e. CCA) will not be performed
* \param[in] pti - Packet Traffic Information that will be used for this transaction.
*/
FTDF_Status ad_ftdf_send_frame_simple( FTDF_DataLength frameLength,
FTDF_Octet* frame,
FTDF_ChannelNumber channel,
FTDF_PTI pti,
FTDF_Boolean csmaSuppress);
ftdf_status_t ad_ftdf_send_frame_simple(ftdf_data_length_t frame_length,
ftdf_octet_t* frame,
ftdf_channel_number_t channel,
ftdf_pti_t pti,
ftdf_boolean_t csma_suppress);
/**
* \brief Instructs the MAC and PHY to go to sleep
@@ -94,7 +95,7 @@ FTDF_Status ad_ftdf_send_frame_simple( FTDF_DataLength frameLength,
* as soon as possible. If false, and the MAC cannot go to sleep
* immediately, sleep will be aborted.
*/
void ad_ftdf_sleep_when_possible( FTDF_Boolean allow_deferred_sleep);
void ad_ftdf_sleep_when_possible(ftdf_boolean_t allow_deferred_sleep);
/**
* \brief Instructs the MAC and PHY to wakeup, if sleeping
@@ -106,7 +107,7 @@ void ad_ftdf_wake_up(void);
/**
* \brief Configures GPIO pins for the FTDF debug bus
*
* Debug bus uses the following (fixed) GPIO pins:
* if FTDF_DBG_BUS_USE_PORT_4 == 0, the FTDF debug bus uses the following (fixed) GPIO pins,
*
* bit 0: HW_GPIO_PORT_1, HW_GPIO_PIN_4
* bit 1: HW_GPIO_PORT_1, HW_GPIO_PIN_5
@@ -116,8 +117,20 @@ void ad_ftdf_wake_up(void);
* bit 5: HW_GPIO_PORT_0, HW_GPIO_PIN_7
* bit 6: HW_GPIO_PORT_1, HW_GPIO_PIN_3
* bit 7: HW_GPIO_PORT_2, HW_GPIO_PIN_3
*
* if FTDF_DBG_BUS_USE_PORT_4 == 1, the FTDF debug bus uses the following pins:
*
* bit 0: HW_GPIO_PORT_4, HW_GPIO_PIN_0
* bit 1: HW_GPIO_PORT_4, HW_GPIO_PIN_1
* bit 2: HW_GPIO_PORT_4, HW_GPIO_PIN_2
* bit 3: HW_GPIO_PORT_4, HW_GPIO_PIN_3
* bit 4: HW_GPIO_PORT_4, HW_GPIO_PIN_4
* bit 5: HW_GPIO_PORT_4, HW_GPIO_PIN_5
* bit 6: HW_GPIO_PORT_4, HW_GPIO_PIN_6
* bit 7: HW_GPIO_PORT_4, HW_GPIO_PIN_7
*
*/
void ad_ftdf_dbgBusGpioConfig(void);
void ad_ftdf_dbg_bus_gpio_config(void);
#endif /* FTDF_DBG_BUS_ENABLE */
#endif /* AD_FTDF_PHY_API_H */
third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf.h
Vendored
+1536 -1554
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/interfaces/ftdf/include/ftdf_config_phy_api.h
Vendored
+60 -30
View File
@@ -36,16 +36,18 @@
#ifndef FTDF_CONFIG_PHY_API_H_
#define FTDF_CONFIG_PHY_API_H_
#include "osal.h" // OS_FREERTOS macro is checked within the header file.
/**
* \remark phy configuration values in microseconds
*/
#define FTDF_PHYTXSTARTUP 0x4c
#define FTDF_PHYTXLATENCY 0x01
#define FTDF_PHYTXLATENCY 0x02
#define FTDF_PHYTXFINISH 0x00
#define FTDF_PHYTRXWAIT 0x20
#define FTDF_PHYRXSTARTUP 0
#define FTDF_PHYTRXWAIT 0x22
#define FTDF_PHYRXSTARTUP 0x54
#define FTDF_PHYRXLATENCY 0
#define FTDF_PHYENABLE 0x21
#define FTDF_PHYENABLE 0x20
#ifndef FTDF_LITE
#define FTDF_LITE
@@ -54,81 +56,82 @@
/**
* \remark See FTDF_GET_MSG_BUFFER in ftdf.h
*/
#define FTDF_GET_MSG_BUFFER ad_ftdf_getMsgBuffer
#define FTDF_GET_MSG_BUFFER ad_ftdf_get_msg_buffer
/**
* \remark See FTDF_REL_MSG_BUFFER in ftdf.h
*/
#define FTDF_REL_MSG_BUFFER ad_ftdf_relMsgBuffer
#define FTDF_REL_MSG_BUFFER ad_ftdf_rel_msg_buffer
/**
* \remark See FTDF_REC_MSG in ftdf.h
*/
#define FTDF_RCV_MSG ad_ftdf_rcvMsg
#define FTDF_RCV_MSG ad_ftdf_rcv_msg
/**
* \remark See FTDF_GET_DATA_BUFFER in ftdf.h
*/
#define FTDF_GET_DATA_BUFFER ad_ftdf_getDataBuffer
#define FTDF_GET_DATA_BUFFER ad_ftdf_get_data_buffer
/**
* \remark See FTDF_REL_DATA_BUFFER in ftdf.h
*/
#define FTDF_REL_DATA_BUFFER ad_ftdf_relDataBuffer
#define FTDF_REL_DATA_BUFFER ad_ftdf_rel_data_buffer
/**
* \remark See FTDF_GET_EXT_ADDRESS in ftdf.h
*/
#define FTDF_GET_EXT_ADDRESS ad_ftdf_getExtAddress
#define FTDF_GET_EXT_ADDRESS ad_ftdf_get_ext_address
/**
* \remark See FTDF_RCV_FRAME_TRANSPARENT in ftdf.h
*/
#define FTDF_RCV_FRAME_TRANSPARENT FTDF_rcvFrameTransparent
#define FTDF_RCV_FRAME_TRANSPARENT ftdf_rcv_frame_transparent
/**
* \remark See FTDF_SEND_FRAME_TRANSPARENT_CONFIRM in ftdf.h
*/
#define FTDF_SEND_FRAME_TRANSPARENT_CONFIRM FTDF_sendFrameTransparentConfirm
#define FTDF_SEND_FRAME_TRANSPARENT_CONFIRM ftdf_send_frame_transparent_confirm
/**
* \remark See FTDF_WAKE_UP_READY in ftdf.h
*/
#define FTDF_WAKE_UP_READY ad_ftdf_wakeUpReady
#define FTDF_WAKE_UP_READY ad_ftdf_wake_up_ready
/**
* \remark See FTDF_SLEEP_CALLBACK in ftdf.h
*/
#define FTDF_SLEEP_CALLBACK ad_ftdf_sleepCb
#define FTDF_SLEEP_CALLBACK ad_ftdf_sleep_cb
/* Forward declaration */
void sleep_when_possible( uint8_t explicit_request, uint32_t sleepTime );
void sleep_when_possible(uint8_t explicit_request, uint32_t sleep_time);
#define FTDF_LMACREADY4SLEEP_CB sleep_when_possible
#define FTDF_LMACREADY4SLEEP_CB sleep_when_possible
#ifndef OS_FREERTOS
#define portDISABLE_INTERRUPTS() \
do { \
__asm volatile ( " cpsid i " ); \
__asm volatile (" cpsid i "); \
DBG_CONFIGURE_HIGH(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \
} while (0)
#define portENABLE_INTERRUPTS() \
do { \
DBG_CONFIGURE_LOW(CMN_TIMING_DEBUG, CMNDBG_CRITICAL_SECTION); \
__asm volatile ( " cpsie i " ); \
__asm volatile (" cpsie i "); \
} while (0)
void vPortEnterCritical( void );
void vPortExitCritical( void );
void vPortEnterCritical(void);
void vPortExitCritical(void);
#define OS_ENTER_CRITICAL_SECTION vPortEnterCritical
#define OS_LEAVE_CRITICAL_SECTION vPortExitCritical
#endif
/**
* \remark Critical section
*/
#define FTDF_criticalVar( )
#define FTDF_enterCritical( ) vPortEnterCritical()
#define FTDF_exitCritical( ) vPortExitCritical()
#define ftdf_critical_var( )
#define ftdf_enter_critical( ) OS_ENTER_CRITICAL_SECTION()
#define ftdf_exit_critical( ) OS_LEAVE_CRITICAL_SECTION()
#ifndef FTDF_DBG_BUS_ENABLE
/**
@@ -142,20 +145,47 @@ void vPortExitCritical( void );
#endif
#if FTDF_DBG_BUS_ENABLE
#define FTDF_DBG_BUS_GPIO_CONFIG ad_ftdf_dbgBusGpioConfig
#define FTDF_DBG_BUS_GPIO_CONFIG ad_ftdf_dbg_bus_gpio_config
#ifndef FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2
/**
* \brief Enables FTDF diagnostics on diagnostic pins 6 and 7 on GPIO P1_3 and P2_3.
*
* When enabled, UART must use pins other than the default P1_3, P2_3.
*/
#define FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2 (0)
#endif
#ifndef FTDF_DBG_BUS_USE_SWDIO_PIN
/**
* \brief Enables diagnostics on diagnostic pin 4 on GPIO P0_6.
*
* When enabled, the debugger must be disabled since SWD uses the same pin for SWDIO.
*/
#define FTDF_DBG_BUS_USE_SWDIO_PIN (0)
#endif
#ifndef FTDF_DBG_BUS_USE_PORT_4
/**
* \brief Uses Port 4 (instead of GPIOs at Ports 0, 1 and 2) for diagnostics
*
* When enabled, FTDF diagnostics pins uses P4_0 to P4_7
*/
#define FTDF_DBG_BUS_USE_PORT_4 (0)
#endif
#endif /* FTDF_DBG_BUS_ENABLE */
#ifndef FTDF_USE_AUTO_PTI
#define FTDF_USE_AUTO_PTI 0
#endif
#ifndef FTDF_USE_FP_PROCESSING_RAM
/**
* \brief Whether to use HW acceleration for indirect sending.
*
* Feature is supported as of IC revision 14683-00.
*/
#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A
#define FTDF_USE_FP_PROCESSING_RAM 1
#else
#define FTDF_USE_FP_PROCESSING_RAM 0
#endif
#endif /* FTDF_USE_FP_PROCESSING_RAM */
#endif /* FTDF_CONFIG_PHY_API_H_ */
third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.c
Vendored
+187 -162
View File
@@ -1,7 +1,7 @@
/**
****************************************************************************************
*
* @file ftdf.c
* @file ad_ftdf.c
*
* @brief FTDF FreeRTOS Adapter
*
@@ -43,14 +43,17 @@
#include "sys_power_mgr.h"
#endif
#if dg_configRF_ADAPTER
#include "ad_rf.h"
#else
#include "hw_rf.h"
#endif
#include "sys_tcs.h"
#include "sdk_defs.h"
#include "ad_ftdf.h"
#include "internal.h"
#include "regmap.h"
#if FTDF_DBG_BUS_ENABLE
#include "hw_gpio.h"
#endif /* FTDF_DBG_BUS_ENABLE */
@@ -74,166 +77,155 @@
#endif
#endif
PRIVILEGED_DATA FTDF_Boolean explicit_sleep; /* = FTDF_FALSE; */
PRIVILEGED_DATA eSleepStatus sleep_status;
PRIVILEGED_DATA ftdf_boolean_t explicit_sleep; /* = FTDF_FALSE; */
PRIVILEGED_DATA sleep_status_t sleep_status;
PRIVILEGED_DATA FTDF_ExtAddress uExtAddress;
PRIVILEGED_DATA ftdf_ext_address_t u_ext_address;
static void ad_ftdf_sleep(void)
{
ftdf_critical_var();
ftdf_enter_critical();
REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go sleep
ftdf_exit_critical();
FTDF_criticalVar();
FTDF_enterCritical();
REG_SET_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go sleep
FTDF_exitCritical();
while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_DOWN) == 0x0) // don't go-go before I sleep
{
}
// don't go-go before I sleep
while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_DOWN) == 0x0) {
}
#if FTDF_DBG_BLOCK_SLEEP_ENABLE
hw_gpio_set_inactive(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN);
hw_gpio_set_inactive(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN);
#endif
}
void ad_ftdf_wake_up_internal(bool sync)
{
if (sleep_status != BLOCK_SLEEPING)
{
return;
}
if ( sleep_status != BLOCK_SLEEPING ) {
return;
}
FTDF_criticalVar();
FTDF_enterCritical();
/* Wake up power domains */
REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up
FTDF_exitCritical();
ftdf_critical_var();
ftdf_enter_critical();
/* Wake up power domains */
REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up
ftdf_exit_critical();
while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) // don't go-go before I sleep
{
}
// don't go-go before I sleep
while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) {
}
#if FTDF_DBG_BLOCK_SLEEP_ENABLE
hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true);
hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true);
#endif
/* Power on and configure RF */
ad_rf_request_on(false);
/* Power on and configure RF */
#if dg_configRF_ADAPTER
ad_rf_request_on(false);
#else
hw_rf_request_on(false);
#endif
/* Apply trim values */
// sys_tcs_apply(tcs_ftdf);
/* Apply trim values */
sys_tcs_apply(tcs_ftdf);
ad_rf_request_recommended_settings();
#if dg_configRF_ADAPTER
ad_rf_request_recommended_settings();
#else
hw_rf_request_recommended_settings();
#endif
if (sync)
{
FTDF_initLmac();
sleep_status = BLOCK_ACTIVE;
}
else
{
/* Wake up FTDF block */
sleep_status = BLOCK_WAKING_UP;
FTDF_wakeUp();
if (sync) {
ftdf_init_lmac( );
sleep_status = BLOCK_ACTIVE;
} else {
/* Wake up FTDF block */
sleep_status = BLOCK_WAKING_UP;
ftdf_wakeup();
#if defined(FTDF_NO_CSL) && defined(FTDF_NO_TSCH)
ad_ftdf_wakeUpReady();
ad_ftdf_wake_up_ready();
#endif
}
}
}
void ad_ftdf_wake_up_async(void)
{
ad_ftdf_wake_up_internal(false);
ad_ftdf_wake_up_internal(false);
}
void ad_ftdf_wake_up_sync(void)
{
ad_ftdf_wake_up_internal(true);
ad_ftdf_wake_up_internal(true);
}
void sleep_when_possible(uint8_t explicit_request, uint32_t sleepTime)
void sleep_when_possible(uint8_t explicit_request, uint32_t sleep_time )
{
FTDF_Boolean blockSleep = FTDF_FALSE;
ftdf_boolean_t block_sleep = FTDF_FALSE;
if ((!AD_FTDF_SLEEP_WHEN_IDLE && !explicit_request) || sleep_status != BLOCK_ACTIVE)
{
return;
}
FTDF_USec us;
FTDF_criticalVar();
FTDF_enterCritical();
#ifdef FTDF_PHY_API
if (explicit_request && FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0)
{
volatile uint32_t *lmacCtrlMask = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_LMAC_CONTROL_MASK);
volatile uint32_t *lmacReady4sleepEvent = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_LMACREADY4SLEEP_D);
/* clear a previous interrupt */
*lmacReady4sleepEvent = MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_D;
/* Enable (unmask) interrupt */
*lmacCtrlMask |= MSK_F_FTDF_ON_OFF_REGMAP_LMACREADY4SLEEP_M;
us = 0;
}
else
{
us = FTDF_canSleep();
}
#else
us = FTDF_canSleep();
#endif
/* Try to sleep as much as needed (if sleepTime is 0, then sleep as much as possible).
* Otherwise, sleep as much as possible. */
if (explicit_request == FTDF_TRUE)
{
if (sleepTime && us > sleepTime)
{
us = sleepTime;
if ((!AD_FTDF_SLEEP_WHEN_IDLE && !explicit_request) || sleep_status != BLOCK_ACTIVE) {
return;
}
}
if (us > (WUP_LATENCY / 1000000) + AD_FTDF_SLEEP_COMPENSATION)
{
// Subtract sleep compensation from the sleep time, compensating for delays
us -= AD_FTDF_SLEEP_COMPENSATION;
ftdf_usec_t us;
blockSleep = FTDF_prepareForSleep(us);
if (blockSleep)
{
// FTDF ready to sleep, disable clocks
sleep_status = BLOCK_SLEEPING;
explicit_sleep = explicit_request;
ftdf_critical_var();
ftdf_enter_critical();
#ifdef FTDF_PHY_API
if (explicit_request && (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0)) {
/* clear a previous interrupt */
FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, LMACREADY4SLEEP_D);
/* Enable (unmask) interrupt */
REG_SET_BIT(FTDF, FTDF_LMAC_CONTROL_MASK_REG, LMACREADY4SLEEP_M);
us = 0;
} else {
us = ftdf_can_sleep();
}
#else
us = ftdf_can_sleep();
#endif
/* Try to sleep as much as needed (if sleep_time is 0, then sleep as much as possible).
* Otherwise, sleep as much as possible. */
if ( explicit_request == FTDF_TRUE ) {
if (sleep_time && us > sleep_time)
us = sleep_time;
}
if (us > ( WUP_LATENCY / 1000000) + AD_FTDF_SLEEP_COMPENSATION) {
// Subtract sleep compensation from the sleep time, compensating for delays
us -= AD_FTDF_SLEEP_COMPENSATION;
block_sleep = ftdf_prepare_for_sleep(us);
if (block_sleep) {
// FTDF ready to sleep, disable clocks
sleep_status = BLOCK_SLEEPING;
explicit_sleep = explicit_request;
#if FTDF_USE_SLEEP_DURING_BACKOFF
FTDF_sdbFsmSleep();
ftdf_sdb_fsm_sleep();
#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */
#if dg_configUSE_FTDF_DDPHY == 1
FTDF_ddphySave();
ftdf_ddphy_save();
#endif /* dg_configUSE_FTDF_DDPHY */
ad_ftdf_sleep();
}
else
{
ad_ftdf_sleep();
} else {
#if FTDF_USE_SLEEP_DURING_BACKOFF
FTDF_sdbFsmAbortSleep();
ftdf_sdb_fsm_abort_sleep();
#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */
}
}
ftdf_exit_critical();
if (block_sleep) {
#if dg_configRF_ADAPTER
ad_rf_request_off(false);
#else
hw_rf_request_off(false);
#endif
}
}
FTDF_exitCritical();
if (blockSleep)
{
ad_rf_request_off(false);
}
}
/**
@@ -241,76 +233,109 @@ void sleep_when_possible(uint8_t explicit_request, uint32_t sleepTime)
*/
void ad_ftdf_init(void)
{
/* Wake up power domains */
REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up
/* Wake up power domains */
GLOBAL_INT_DISABLE();
REG_CLR_BIT(CRG_TOP, PMU_CTRL_REG, FTDF_SLEEP); // go wake up
GLOBAL_INT_RESTORE();
while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) // don't go-go before I sleep
{
}
// don't go-go before I sleep
while (REG_GETF(CRG_TOP, SYS_STAT_REG, FTDF_IS_UP) == 0x0) {
}
#if FTDF_DBG_BLOCK_SLEEP_ENABLE
hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true);
hw_gpio_configure_pin(FTDF_DBG_BLOCK_SLEEP_GPIO_PORT, FTDF_DBG_BLOCK_SLEEP_GPIO_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true);
#endif
REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_ENABLE); // on
REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_DIV, 0); // divide by 1
GLOBAL_INT_DISABLE();
REG_SET_BIT(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_ENABLE); // on
REG_SETF(CRG_TOP, CLK_RADIO_REG, FTDF_MAC_DIV, 0); // divide by 1
GLOBAL_INT_RESTORE();
/* Power on and configure RF */
ad_rf_request_on(false);
/* Power on and configure RF */
#if dg_configRF_ADAPTER
ad_rf_request_on(false);
#else
hw_rf_request_on(false);
#endif
/* Apply trim values */
sys_tcs_apply(tcs_ftdf);
/* Apply trim values */
sys_tcs_apply(tcs_ftdf);
ad_rf_request_recommended_settings();
#if dg_configRF_ADAPTER
ad_rf_request_recommended_settings();
#else
hw_rf_request_recommended_settings();
#endif
FTDF_setSleepAttributes(AD_FTDF_LP_CLOCK_CYCLE,
AD_FTDF_WUP_LATENCY);
ftdf_set_sleep_attributes( AD_FTDF_LP_CLOCK_CYCLE, AD_FTDF_WUP_LATENCY );
#ifdef FTDF_PHY_API
ad_ftdf_init_phy_api();
ad_ftdf_init_phy_api();
#else
ad_ftdf_init_mac_api();
ad_ftdf_init_mac_api();
#endif
}
void ad_ftdf_sleepCb(FTDF_USec sleepTime)
void ad_ftdf_sleep_cb(ftdf_usec_t sleep_time )
{
sleep_when_possible(FTDF_TRUE, sleepTime);
sleep_when_possible( FTDF_TRUE, sleep_time );
}
#if FTDF_DBG_BUS_ENABLE
void ad_ftdf_dbgBusGpioConfig(void)
void ad_ftdf_dbg_bus_gpio_config(void)
{
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_4, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
#if FTDF_DBG_BUS_USE_PORT_4 == 1
hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_0, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_1, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_2, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_4, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_4, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
#else
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_4, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_5, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
#if FTDF_DBG_BUS_USE_SWDIO_PIN
/*
* Note that this pin has a conflict with SWD. Disable the debugger in order to use this
* pin.
*/
hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
/*
* Note that this pin has a conflict with SWD. Disable the debugger in order to use this
* pin.
*/
hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_6, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
#endif
hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_0, HW_GPIO_PIN_7, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
#if FTDF_DBG_BUS_USE_GPIO_P1_3_P2_2
/*
* Note that these pins have a conflict with the pins used for UART by default. Configure
* UART on different pins if you would like to use the pins below for diagnostics.
*/
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
/*
* Note that these pins have a conflict with the pins used for UART by default. Configure
* UART on different pins if you would like to use the pins below for diagnostics.
*/
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_FTDF_DIAG);
#endif
#endif /* FTDF_DBG_BUS_USE_PORT_4 == 1 */
}
#endif /* FTDF_DBG_BUS_ENABLE */
#endif
third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf.h
Vendored
+7 -6
View File
@@ -7,6 +7,7 @@
/**
****************************************************************************************
*
* @file ad_ftdf.h
*
* @brief FTDF Adapter internal header file
@@ -53,11 +54,11 @@
typedef enum {
BLOCK_ACTIVE = 0, BLOCK_SLEEPING, BLOCK_WAKING_UP
} eSleepStatus;
} sleep_status_t;
extern eSleepStatus sleep_status;
extern FTDF_ExtAddress uExtAddress;
extern FTDF_Boolean explicit_sleep;
extern sleep_status_t sleep_status;
extern ftdf_ext_address_t u_ext_address;
extern ftdf_boolean_t explicit_sleep;
void ad_ftdf_init_mac_api(void);
void ad_ftdf_init_phy_api(void);
@@ -65,7 +66,7 @@ void ad_ftdf_init_phy_api(void);
void ad_ftdf_wake_up_async(void);
void ad_ftdf_wake_up_sync(void);
void sleep_when_possible( uint8_t explicit_request, uint32_t sleepTime );
void sleep_when_possible( uint8_t explicit_request, uint32_t sleep_time );
#if FTDF_DBG_BUS_ENABLE
/**
@@ -82,7 +83,7 @@ void sleep_when_possible( uint8_t explicit_request, uint32_t sleepTime );
* bit 6: HW_GPIO_PORT_1, HW_GPIO_PIN_3
* bit 7: HW_GPIO_PORT_2, HW_GPIO_PIN_3
*/
void ad_ftdf_dbgBusGpioConfig(void);
void ad_ftdf_dbg_bus_gpio_config(void);
#endif /* FTDF_DBG_BUS_ENABLE */
#endif /* AD_FTDF_H */
third_party/dialog/DialogSDK/interfaces/ftdf/src/ad_ftdf_phy_api.c
Vendored
+70 -77
View File
@@ -1,7 +1,7 @@
/**
****************************************************************************************
*
* @file ftdf.c
* @file ad_ftdf_phy_api.c
*
* @brief FTDF FreeRTOS Adapter
*
@@ -50,122 +50,115 @@
#ifndef OS_FREERTOS
static unsigned long uxCriticalNesting = 0xaaaaaaaa;
void vPortEnterCritical(void)
void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
__asm volatile("dsb");
__asm volatile("isb");
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
__asm volatile( "dsb" );
__asm volatile( "isb" );
}
/*-----------------------------------------------------------*/
void vPortExitCritical(void)
void vPortExitCritical( void )
{
uxCriticalNesting--;
if (uxCriticalNesting == 0)
{
portENABLE_INTERRUPTS();
}
uxCriticalNesting--;
if ( uxCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
}
#endif /* !OS_FREERTOS */
/**
* @brief ftdf_gen_irq interrupt service routine
*/
void FTDF_GEN_Handler(void)
void FTDF_GEN_Handler( void)
{
FTDF_confirmLmacInterrupt();
FTDF_eventHandler();
ftdf_confirm_lmac_interrupt();
ftdf_event_handler();
}
/**
* @brief ftdf_wakup_irq interrupt service routine
*/
void FTDF_WAKEUP_Handler(void)
void FTDF_WAKEUP_Handler( void)
{
ad_ftdf_wake_up_async();
}
void ad_ftdf_setExtAddress(FTDF_ExtAddress address)
{
uExtAddress = address;
}
FTDF_ExtAddress ad_ftdf_getExtAddress(void)
{
return uExtAddress;
}
void ad_ftdf_wakeUpReady(void)
{
}
FTDF_Status ad_ftdf_send_frame_simple(FTDF_DataLength frameLength,
FTDF_Octet *frame,
FTDF_ChannelNumber channel,
FTDF_PTI pti,
FTDF_Boolean csmaSuppress)
{
FTDF_criticalVar();
FTDF_enterCritical();
if (FTDF_txInProgress == FTDF_TRUE)
{
FTDF_exitCritical();
return FTDF_TRANSPARENT_OVERFLOW;
}
FTDF_txInProgress = FTDF_TRUE;
FTDF_exitCritical();
if (sleep_status == BLOCK_SLEEPING)
{
/* Wake-up the block */
ad_ftdf_wake_up_async();
#if FTDF_DBG_BUS_ENABLE
FTDF_checkDbgMode();
#endif /* FTDF_DBG_BUS_ENABLE */
sleep_status = BLOCK_ACTIVE;
}
}
return FTDF_sendFrameSimple(frameLength, frame, channel, pti, csmaSuppress);
void ad_ftdf_set_ext_address( ftdf_ext_address_t address)
{
u_ext_address = address;
}
ftdf_ext_address_t ad_ftdf_get_ext_address( void)
{
return u_ext_address;
}
void ad_ftdf_wake_up_ready( void)
{
}
ftdf_status_t ad_ftdf_send_frame_simple( ftdf_data_length_t frameLength,
ftdf_octet_t *frame,
ftdf_channel_number_t channel,
ftdf_pti_t pti,
ftdf_boolean_t csmaSuppress)
{
ftdf_critical_var();
ftdf_enter_critical();
if (ftdf_tx_in_progress == FTDF_TRUE) {
ftdf_exit_critical();
return FTDF_TRANSPARENT_OVERFLOW;
}
ftdf_tx_in_progress = FTDF_TRUE;
ftdf_exit_critical();
if (sleep_status == BLOCK_SLEEPING) {
/* Wake-up the block */
ad_ftdf_wake_up_async();
#if FTDF_DBG_BUS_ENABLE
ftdf_check_dbg_mode();
#endif /* FTDF_DBG_BUS_ENABLE */
sleep_status = BLOCK_ACTIVE;
}
return ftdf_send_frame_simple(frameLength, frame, channel, pti, csmaSuppress);
}
void ad_ftdf_sleep_when_possible(FTDF_Boolean allow_deferred_sleep)
void ad_ftdf_sleep_when_possible( ftdf_boolean_t allow_deferred_sleep)
{
sleep_when_possible(allow_deferred_sleep, 0);
sleep_when_possible(allow_deferred_sleep, 0);
}
void ad_ftdf_wake_up(void)
{
if (sleep_status == BLOCK_SLEEPING)
{
/* Wake-up the block */
ad_ftdf_wake_up_async();
if (sleep_status == BLOCK_SLEEPING) {
/* Wake-up the block */
ad_ftdf_wake_up_async();
#if FTDF_DBG_BUS_ENABLE
FTDF_checkDbgMode();
ftdf_check_dbg_mode();
#endif /* FTDF_DBG_BUS_ENABLE */
sleep_status = BLOCK_ACTIVE;
}
sleep_status = BLOCK_ACTIVE;
}
}
void ad_ftdf_init_phy_api(void)
{
NVIC_ClearPendingIRQ(FTDF_WAKEUP_IRQn);
NVIC_EnableIRQ(FTDF_WAKEUP_IRQn);
NVIC_ClearPendingIRQ(FTDF_WAKEUP_IRQn);
NVIC_EnableIRQ(FTDF_WAKEUP_IRQn);
NVIC_ClearPendingIRQ(FTDF_GEN_IRQn); // Disable ftdf interrupts
NVIC_EnableIRQ(FTDF_GEN_IRQn); // ftdf will be handled by poiling
sleep_status = BLOCK_ACTIVE;
NVIC_ClearPendingIRQ(FTDF_GEN_IRQn);
NVIC_EnableIRQ(FTDF_GEN_IRQn);
sleep_status = BLOCK_ACTIVE;
#ifndef OS_FREERTOS
uxCriticalNesting = 0;
uxCriticalNesting = 0;
#endif
FTDF_reset(1);
ftdf_reset(1);
}
#endif /* FTDF_PHY_API */
#endif
third_party/dialog/DialogSDK/interfaces/ftdf/src/common.c
Vendored
+4209 -4591
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/interfaces/ftdf/src/data.c
Vendored
+446 -560
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/interfaces/ftdf/src/ftdfInfo.h
Vendored
+2 -2
View File
@@ -9,7 +9,7 @@
#define FTDF_BRANCH_VERSION 0
#define FTDF_LOAD_VERSION 32
const char* FTDF_getUmacRelName( void );
const char* FTDF_getUmacBuildTime( void );
const char *ftdf_get_umac_rel_name( void );
const char *ftdf_get_umac_build_time( void );
#endif /* FTDFINFO_H_ */
third_party/dialog/DialogSDK/interfaces/ftdf/src/internal.h
Vendored
+507 -528
View File
File diff suppressed because it is too large Load Diff
third_party/dialog/DialogSDK/interfaces/ftdf/src/main.c
Vendored
+190 -229
View File
@@ -37,295 +37,256 @@
#include <string.h>
#include "internal.h"
#include "regmap.h"
#include "ftdfInfo.h"
void FTDF_getReleaseInfo(char **lmacRelName, char **lmacBuildTime, char **umacRelName, char **umacBuildTime)
void ftdf_get_release_info(char **lmac_rel_name, char **lmac_build_time, char **umac_rel_name,
char **umac_build_time)
{
static char lrelName[ 16 ];
static char lbldTime[ 16 ];
static char urelName[ 16 ];
static char ubldTime[ 16 ];
uint8_t i;
static char lrel_name[16];
static char lbld_time[16];
static char urel_name[16];
static char ubld_time[16];
uint8_t i;
volatile uint32_t *ptr = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_REL_NAME);
uint32_t *chrPtr = (uint32_t *)lrelName;
volatile uint32_t *ptr = &FTDF->FTDF_REL_NAME_0_REG;
uint32_t *chr_ptr = (uint32_t*)lrel_name;
for (i = 0; i < FTDF_ON_OFF_REGMAP_REL_NAME_NUM; i++)
{
*chrPtr++ = *ptr++;
}
ptr = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_BUILDTIME);
chrPtr = (uint32_t *)lbldTime;
for (i = 0; i < FTDF_ON_OFF_REGMAP_BUILDTIME_NUM; i++)
{
*chrPtr++ = *ptr++;
}
const char *umacVPtr = FTDF_getUmacRelName();
for (i = 0; i < 16; i++)
{
urelName[ i ] = umacVPtr[ i ];
if (umacVPtr[ i ] == '\0')
{
break;
for (i = 0; i < 4; i++) {
*chr_ptr++ = *ptr++;
}
}
umacVPtr = FTDF_getUmacBuildTime();
ptr = &FTDF->FTDF_BUILDTIME_0_REG;
chr_ptr = (uint32_t*)lbld_time;
for (i = 0; i < 16; i++)
{
ubldTime[ i ] = umacVPtr[ i ];
if (umacVPtr[ i ] == '\0')
{
break;
for (i = 0; i < 4; i++) {
*chr_ptr++ = *ptr++;
}
}
lrelName[ 15 ] = '\0';
lbldTime[ 15 ] = '\0';
urelName[ 15 ] = '\0';
ubldTime[ 15 ] = '\0';
const char* umac_v_ptr = ftdf_get_umac_rel_name();
*lmacRelName = lrelName;
*lmacBuildTime = lbldTime;
*umacRelName = urelName;
*umacBuildTime = ubldTime;
for (i = 0; i < 16; i++) {
urel_name[i] = umac_v_ptr[i];
if (umac_v_ptr[i] == '\0') {
break;
}
}
umac_v_ptr = ftdf_get_umac_build_time();
for (i = 0; i < 16; i++) {
ubld_time[i] = umac_v_ptr[i];
if (umac_v_ptr[i] == '\0') {
break;
}
}
lrel_name[15] = '\0';
lbld_time[15] = '\0';
urel_name[15] = '\0';
ubld_time[15] = '\0';
*lmac_rel_name = lrel_name;
*lmac_build_time = lbld_time;
*umac_rel_name = urel_name;
*umac_build_time = ubld_time;
}
void FTDF_confirmLmacInterrupt(void)
void ftdf_confirm_lmac_interrupt(void)
{
volatile uint32_t *ftdfCm = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_FTDF_CM);
*ftdfCm = 0;
REG_SETF(FTDF, FTDF_FTDF_CM_REG, FTDF_CM, 0);
}
void FTDF_eventHandler(void)
void ftdf_event_handler(void)
{
volatile uint32_t ftdfCe = *FTDF_GET_REG_ADDR(ON_OFF_REGMAP_FTDF_CE);
volatile uint32_t ftdf_ce = FTDF->FTDF_FTDF_CE_REG;
if (ftdfCe & FTDF_MSK_RX_CE)
{
FTDF_processRxEvent();
}
if (ftdf_ce & FTDF_MSK_RX_CE) {
ftdf_process_rx_event();
}
if (ftdfCe & FTDF_MSK_TX_CE)
{
FTDF_processTxEvent();
}
if (ftdf_ce & FTDF_MSK_TX_CE) {
ftdf_process_tx_event();
}
if (ftdfCe & FTDF_MSK_SYMBOL_TMR_CE)
{
FTDF_processSymbolTimerEvent();
}
if (ftdf_ce & FTDF_MSK_SYMBOL_TMR_CE) {
ftdf_process_symbol_timer_event();
}
#ifndef FTDF_LITE
#ifndef FTDF_NO_CSL
if (ftdf_pib.le_enabled) {
ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG,
SYMBOLTIMESNAPSHOTVAL);
if (FTDF_pib.leEnabled)
{
FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL);
FTDF_Time delta = curTime - FTDF_rzTime;
ftdf_time_t delta = cur_time - ftdf_rz_time;
if (delta < 0x80000000)
{
// RZ has passed check if a send frame is pending
if (FTDF_sendFramePending != 0xfffe)
{
FTDF_Time wakeupStartTime;
FTDF_Period wakeupPeriod;
if (delta < 0x80000000) {
/* RZ has passed check if a send frame is pending */
if (ftdf_send_frame_pending != 0xfffe) {
ftdf_time_t wakeup_start_time;
ftdf_period_t wakeup_period;
FTDF_criticalVar();
FTDF_enterCritical();
ftdf_critical_var();
ftdf_enter_critical();
FTDF_getWakeupParams(FTDF_sendFramePending, &wakeupStartTime, &wakeupPeriod);
ftdf_get_wakeup_params(ftdf_send_frame_pending, &wakeup_start_time,
&wakeup_period);
FTDF_txInProgress = FTDF_TRUE;
FTDF_SET_FIELD(ON_OFF_REGMAP_MACCSLSTARTSAMPLETIME, wakeupStartTime);
FTDF_SET_FIELD(ON_OFF_REGMAP_MACWUPERIOD, wakeupPeriod);
ftdf_tx_in_progress = FTDF_TRUE;
REG_SETF(FTDF, FTDF_LMAC_CONTROL_8_REG, MACCSLSTARTSAMPLETIME,
wakeup_start_time);
REG_SETF(FTDF, FTDF_LMAC_CONTROL_7_REG, MACWUPERIOD, wakeup_period);
volatile uint32_t *txFlagSet = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_TX_FLAG_SET);
*txFlagSet |= ((1 << FTDF_TX_DATA_BUFFER) | (1 << FTDF_TX_WAKEUP_BUFFER));
REG_SETF(FTDF, FTDF_TX_SET_OS_REG, TX_FLAG_SET,
((1 << FTDF_TX_DATA_BUFFER) |
(1 << FTDF_TX_WAKEUP_BUFFER)));
FTDF_sendFramePending = 0xfffe;
ftdf_send_frame_pending = 0xfffe;
FTDF_exitCritical();
}
ftdf_exit_critical();
}
if (FTDF_txInProgress == FTDF_FALSE)
{
FTDF_setCslSampleTime();
}
if (ftdf_tx_in_progress == FTDF_FALSE) {
ftdf_set_csl_sample_time();
}
}
}
}
#endif /* FTDF_NO_CSL */
#endif /* !FTDF_LITE */
volatile uint32_t *ftdfCm = FTDF_GET_REG_ADDR(ON_OFF_REGMAP_FTDF_CM);
*ftdfCm = FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE;
REG_SETF(FTDF, FTDF_FTDF_CM_REG, FTDF_CM,
(FTDF_MSK_TX_CE | FTDF_MSK_RX_CE | FTDF_MSK_SYMBOL_TMR_CE));
}
#ifndef FTDF_PHY_API
void FTDF_sndMsg(FTDF_MsgBuffer *msgBuf)
void ftdf_snd_msg(ftdf_msg_buffer_t* msg_buf)
{
switch (msgBuf->msgId)
{
switch (msg_buf->msg_id) {
#ifndef FTDF_LITE
case FTDF_DATA_REQUEST:
FTDF_processDataRequest((FTDF_DataRequest *) msgBuf);
break;
case FTDF_PURGE_REQUEST:
FTDF_processPurgeRequest((FTDF_PurgeRequest *) msgBuf);
break;
case FTDF_ASSOCIATE_REQUEST:
FTDF_processAssociateRequest((FTDF_AssociateRequest *) msgBuf);
break;
case FTDF_ASSOCIATE_RESPONSE:
FTDF_processAssociateResponse((FTDF_AssociateResponse *) msgBuf);
break;
case FTDF_DISASSOCIATE_REQUEST:
FTDF_processDisassociateRequest((FTDF_DisassociateRequest *) msgBuf);
break;
case FTDF_DATA_REQUEST:
ftdf_process_data_request((ftdf_data_request_t*)msg_buf);
break;
case FTDF_PURGE_REQUEST:
ftdf_process_purge_request((ftdf_purge_request_t*)msg_buf);
break;
case FTDF_ASSOCIATE_REQUEST:
ftdf_process_associate_request((ftdf_associate_request_t*)msg_buf);
break;
case FTDF_ASSOCIATE_RESPONSE:
ftdf_process_associate_response((ftdf_associate_response_t*)msg_buf);
break;
case FTDF_DISASSOCIATE_REQUEST:
ftdf_process_disassociate_request((ftdf_disassociate_request_t*)msg_buf);
break;
#endif /* !FTDF_LITE */
case FTDF_GET_REQUEST:
FTDF_processGetRequest((FTDF_GetRequest *) msgBuf);
break;
case FTDF_SET_REQUEST:
FTDF_processSetRequest((FTDF_SetRequest *) msgBuf);
break;
case FTDF_GET_REQUEST:
ftdf_process_get_request((ftdf_get_request_t*)msg_buf);
break;
case FTDF_SET_REQUEST:
ftdf_process_set_request((ftdf_set_request_t*)msg_buf);
break;
#ifndef FTDF_LITE
case FTDF_ORPHAN_RESPONSE:
FTDF_processOrphanResponse((FTDF_OrphanResponse *) msgBuf);
break;
case FTDF_ORPHAN_RESPONSE:
ftdf_process_orphan_response((ftdf_orphan_response_t*)msg_buf);
break;
#endif /* !FTDF_LITE */
case FTDF_RESET_REQUEST:
FTDF_processResetRequest((FTDF_ResetRequest *) msgBuf);
break;
case FTDF_RX_ENABLE_REQUEST:
FTDF_processRxEnableRequest((FTDF_RxEnableRequest *) msgBuf);
break;
case FTDF_RESET_REQUEST:
ftdf_process_reset_request((ftdf_reset_request_t*)msg_buf);
break;
case FTDF_RX_ENABLE_REQUEST:
ftdf_process_rx_enable_request((ftdf_rx_enable_request_t*)msg_buf);
break;
#ifndef FTDF_LITE
case FTDF_SCAN_REQUEST:
FTDF_processScanRequest((FTDF_ScanRequest *) msgBuf);
break;
case FTDF_START_REQUEST:
FTDF_processStartRequest((FTDF_StartRequest *) msgBuf);
break;
case FTDF_POLL_REQUEST:
FTDF_processPollRequest((FTDF_PollRequest *) msgBuf);
break;
case FTDF_SCAN_REQUEST:
ftdf_process_scan_request((ftdf_scan_request_t*)msg_buf);
break;
case FTDF_START_REQUEST:
ftdf_process_start_request((ftdf_start_request_t*)msg_buf);
break;
case FTDF_POLL_REQUEST:
ftdf_process_poll_request((ftdf_poll_request_t*)msg_buf);
break;
#ifndef FTDF_NO_TSCH
case FTDF_SET_SLOTFRAME_REQUEST:
FTDF_processSetSlotframeRequest((FTDF_SetSlotframeRequest *) msgBuf);
break;
case FTDF_SET_LINK_REQUEST:
FTDF_processSetLinkRequest((FTDF_SetLinkRequest *) msgBuf);
break;
case FTDF_TSCH_MODE_REQUEST:
FTDF_processTschModeRequest((FTDF_TschModeRequest *) msgBuf);
break;
case FTDF_KEEP_ALIVE_REQUEST:
FTDF_processKeepAliveRequest((FTDF_KeepAliveRequest *) msgBuf);
break;
case FTDF_SET_SLOTFRAME_REQUEST:
ftdf_process_set_slotframe_request((ftdf_set_slotframe_request_t*)msg_buf);
break;
case FTDF_SET_LINK_REQUEST:
ftdf_process_set_link_request((ftdf_set_link_request_t*)msg_buf);
break;
case FTDF_TSCH_MODE_REQUEST:
ftdf_process_tsch_mode_request((ftdf_tsch_mode_request_t*)msg_buf);
break;
case FTDF_KEEP_ALIVE_REQUEST:
ftdf_process_keep_alive_request((ftdf_keep_alive_request_t*)msg_buf);
break;
#endif /* FTDF_NO_TSCH */
case FTDF_BEACON_REQUEST:
FTDF_processBeaconRequest((FTDF_BeaconRequest *) msgBuf);
break;
case FTDF_BEACON_REQUEST:
ftdf_process_beacon_request((ftdf_beacon_request_t*)msg_buf);
break;
#endif /* !FTDF_LITE */
case FTDF_TRANSPARENT_ENABLE_REQUEST:
FTDF_enableTransparentMode(((FTDF_TransparentEnableRequest *) msgBuf)->enable,
((FTDF_TransparentEnableRequest *) msgBuf)->options);
FTDF_REL_MSG_BUFFER(msgBuf);
break;
case FTDF_TRANSPARENT_REQUEST:
FTDF_processTransparentRequest((FTDF_TransparentRequest *) msgBuf);
break;
case FTDF_SLEEP_REQUEST:
FTDF_SLEEP_CALLBACK(((FTDF_SleepRequest *)msgBuf)->sleepTime);
FTDF_REL_MSG_BUFFER(msgBuf);
break;
case FTDF_TRANSPARENT_ENABLE_REQUEST:
ftdf_enable_transparent_mode(((ftdf_transparent_enable_request_t*)msg_buf)->enable,
((ftdf_transparent_enable_request_t*)msg_buf)->options);
FTDF_REL_MSG_BUFFER(msg_buf);
break;
case FTDF_TRANSPARENT_REQUEST:
ftdf_process_transparent_request((ftdf_transparent_request_t*)msg_buf);
break;
case FTDF_SLEEP_REQUEST:
FTDF_SLEEP_CALLBACK(((ftdf_sleep_request_t*)msg_buf)->sleep_time);
FTDF_REL_MSG_BUFFER(msg_buf);
break;
#ifndef FTDF_LITE
case FTDF_REMOTE_REQUEST:
FTDF_processRemoteRequest((FTDF_RemoteRequest *)msgBuf);
break;
case FTDF_REMOTE_REQUEST:
ftdf_process_remote_request((ftdf_remote_request_t*)msg_buf);
break;
#endif /* !FTDF_LITE */
#if FTDF_DBG_BUS_ENABLE
case FTDF_DBG_MODE_SET_REQUEST:
FTDF_setDbgMode(((FTDF_DbgModeSetRequest *) msgBuf)->dbgMode);
FTDF_REL_MSG_BUFFER(msgBuf);
break;
case FTDF_DBG_MODE_SET_REQUEST:
ftdf_set_dbg_mode(((ftdf_dbg_mode_set_request_t *) msg_buf)->dbg_mode);
FTDF_REL_MSG_BUFFER(msg_buf);
break;
#endif /* FTDF_DBG_BUS_ENABLE */
#if dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A
case FTDF_FPPR_MODE_SET_REQUEST:
FTDF_fpprSetMode(((FTDF_FpprModeSetRequest *) msgBuf)->matchFp,
((FTDF_FpprModeSetRequest *) msgBuf)->fpOverride,
((FTDF_FpprModeSetRequest *) msgBuf)->fpForce);
FTDF_REL_MSG_BUFFER(msgBuf);
break;
#endif /* dg_configBLACK_ORCA_IC_REV != BLACK_ORCA_IC_REV_A */
default:
// Silenty release the message buffer
FTDF_REL_MSG_BUFFER(msgBuf);
break;
}
case FTDF_FPPR_MODE_SET_REQUEST:
ftdf_fppr_set_mode(((ftdf_fppr_mode_set_request_t *) msg_buf)->match_fp,
((ftdf_fppr_mode_set_request_t *) msg_buf)->fp_override,
((ftdf_fppr_mode_set_request_t *) msg_buf)->fp_force);
FTDF_REL_MSG_BUFFER(msg_buf);
break;
default:
// Silenty release the message buffer
FTDF_REL_MSG_BUFFER(msg_buf);
break;
}
}
void FTDF_sendFrameTransparentConfirm(void *handle,
FTDF_Bitmap32 status)
void ftdf_send_frame_transparent_confirm(void *handle, ftdf_bitmap32_t status)
{
FTDF_TransparentConfirm *confirm =
(FTDF_TransparentConfirm *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_TransparentConfirm));
ftdf_transparent_confirm_t* confirm =
(ftdf_transparent_confirm_t*) FTDF_GET_MSG_BUFFER(
sizeof(ftdf_transparent_confirm_t));
confirm->msgId = FTDF_TRANSPARENT_CONFIRM;
confirm->handle = handle;
confirm->status = status;
confirm->msg_id = FTDF_TRANSPARENT_CONFIRM;
confirm->handle = handle;
confirm->status = status;
FTDF_RCV_MSG((FTDF_MsgBuffer *) confirm);
FTDF_RCV_MSG((ftdf_msg_buffer_t*)confirm);
}
void FTDF_rcvFrameTransparent(FTDF_DataLength frameLength,
FTDF_Octet *frame,
FTDF_Bitmap32 status)
void ftdf_rcv_frame_transparent(ftdf_data_length_t frame_length, ftdf_octet_t *frame,
ftdf_bitmap32_t status, ftdf_link_quality_t link_quality)
{
FTDF_TransparentIndication *indication =
(FTDF_TransparentIndication *) FTDF_GET_MSG_BUFFER(sizeof(FTDF_TransparentIndication));
ftdf_transparent_indication_t *indication =
(ftdf_transparent_indication_t*) FTDF_GET_MSG_BUFFER(
sizeof(ftdf_transparent_indication_t));
indication->msgId = FTDF_TRANSPARENT_INDICATION;
indication->frameLength = frameLength;
indication->status = status;
indication->frame = FTDF_GET_DATA_BUFFER(frameLength);
memcpy(indication->frame, frame, frameLength);
indication->msg_id = FTDF_TRANSPARENT_INDICATION;
indication->frame_length = frame_length;
indication->status = status;
indication->frame = FTDF_GET_DATA_BUFFER(frame_length);
memcpy(indication->frame, frame, frame_length);
FTDF_RCV_MSG((FTDF_MsgBuffer *) indication);
FTDF_RCV_MSG((ftdf_msg_buffer_t*)indication);
}
#endif /* !FTDF_PHY_API */
third_party/dialog/DialogSDK/interfaces/ftdf/src/power.c
Vendored
+187 -231
View File
@@ -35,337 +35,293 @@
#include <stdlib.h>
#include <ftdf.h>
#include "internal.h"
#include "regmap.h"
#include "sdk_defs.h"
static FTDF_PSec FTDF_lowPowerClockCycle __attribute__((section(".retention")));
static FTDF_PSec FTDF_wakeUpLatency __attribute__((section(".retention")));
#ifdef CONFIG_USE_FTDF
static ftdf_psec_t ftdf_low_power_clock_cycle __attribute__ ((section(".retention")));
static ftdf_psec_t ftdf_wake_up_latency __attribute__ ((section(".retention")));
/* Pre-calculated value for optimization. */
static FTDF_USec FTDF_lowPowerClockCycleUSec __attribute__((section(".retention")));
static ftdf_usec_t ftdf_low_power_clock_cycle_u_sec __attribute__ ((section(".retention")));
/* Pre-calculated value for optimization. */
static FTDF_USec FTDF_wakeUpLatencyUSec __attribute__((section(".retention")));
static ftdf_usec_t ftdf_wake_up_latency_u_sec __attribute__ ((section(".retention")));
/* Pre-calculated value for optimization. */
static FTDF_NrLowPowerClockCycles FTDF_csmacaWakeupThr __attribute__((section(".retention")));
static ftdf_nr_low_power_clock_cycles_t ftdf_csmaca_wakeup_thr __attribute__ ((section(".retention")));
#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH)
static uint32_t FTDF_eventCurrVal __attribute__((section(".retention")));
static uint32_t FTDF_timeStampCurrVal __attribute__((section(".retention")));
static uint32_t FTDF_timeStampCurrPhaseVal __attribute__((section(".retention")));
static uint32_t ftdf_event_curr_val __attribute__ ((section(".retention")));
static uint32_t ftdf_time_stamp_curr_val __attribute__ ((section(".retention")));
static uint32_t ftdf_time_stamp_curr_phase_val __attribute__ ((section(".retention")));
#endif
#ifndef FTDF_NO_CSL
FTDF_Boolean FTDF_wakeUpEnableLe __attribute__((section(".retention")));
ftdf_boolean_t ftdf_wake_up_enable_le __attribute__ ((section(".retention")));
#endif /* FTDF_NO_CSL */
#ifndef FTDF_NO_TSCH
FTDF_Boolean FTDF_wakeUpEnableTsch;
ftdf_boolean_t ftdf_wake_up_enable_tsch;
#endif /* FTDF_NO_TSCH */
void FTDF_setSleepAttributes(FTDF_PSec lowPowerClockCycle,
FTDF_NrLowPowerClockCycles wakeUpLatency)
void ftdf_set_sleep_attributes(ftdf_psec_t low_power_clock_cycle,
ftdf_nr_low_power_clock_cycles_t wake_up_latency)
{
FTDF_lowPowerClockCycle = lowPowerClockCycle;
FTDF_wakeUpLatency = (uint64_t)wakeUpLatency * lowPowerClockCycle;
FTDF_lowPowerClockCycleUSec = FTDF_lowPowerClockCycle / 1000000;
FTDF_wakeUpLatencyUSec = FTDF_wakeUpLatency / 1000000;
FTDF_csmacaWakeupThr = (FTDF_NrLowPowerClockCycles)
(((FTDF_PSec) 0xffffffff * 1000000 - FTDF_wakeUpLatency) / FTDF_lowPowerClockCycle);
ftdf_low_power_clock_cycle = low_power_clock_cycle;
ftdf_wake_up_latency = (ftdf_psec_t)wake_up_latency * low_power_clock_cycle;
ftdf_low_power_clock_cycle_u_sec = ftdf_low_power_clock_cycle / 1000000;
ftdf_wake_up_latency_u_sec = ftdf_wake_up_latency / 1000000;
ftdf_csmaca_wakeup_thr = (ftdf_nr_low_power_clock_cycles_t)
(((ftdf_psec_t) 0xffffffff * 1000000 - ftdf_wake_up_latency) / ftdf_low_power_clock_cycle);
}
FTDF_USec FTDF_canSleep(void)
ftdf_usec_t ftdf_can_sleep(void)
{
#ifdef FTDF_PHY_API
if (FTDF_txInProgress || FTDF_pib.keepPhyEnabled)
{
return 0;
}
if (ftdf_tx_in_progress || ftdf_pib.keep_phy_enabled) {
return 0;
}
#else
#if FTDF_USE_SLEEP_DURING_BACKOFF
if (FTDF_pib.keepPhyEnabled)
if (ftdf_pib.keep_phy_enabled)
#else
if (FTDF_reqCurrent || FTDF_pib.keepPhyEnabled)
if (ftdf_req_current || ftdf_pib.keep_phy_enabled)
#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */
{
return 0;
}
{
return 0;
}
#endif
#if FTDF_USE_SLEEP_DURING_BACKOFF
if (FTDF_GET_FIELD(ON_OFF_REGMAP_SECBUSY) == 1)
if (REG_GETF(FTDF, FTDF_SECURITY_STATUS_REG, SECBUSY) == 1)
#else /* FTDF_USE_SLEEP_DURING_BACKOFF */
if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0 ||
FTDF_GET_FIELD(ON_OFF_REGMAP_SECBUSY) == 1)
if ((REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) ||
(REG_GETF(FTDF, FTDF_SECURITY_STATUS_REG, SECBUSY) == 1))
#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */
{
return 0;
}
{
return 0;
}
#ifndef FTDF_NO_CSL
if (FTDF_pib.leEnabled)
{
if (ftdf_pib.le_enabled) {
#if FTDF_USE_SLEEP_DURING_BACKOFF
/* Abort sleep when LMAC is busy. */
if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0)
{
return 0;
}
/* Abort sleep when LMAC is busy. */
if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) {
return 0;
}
#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */
if (ftdf_tx_in_progress == FTDF_FALSE) {
ftdf_time_t cur_time = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG,
SYMBOLTIMESNAPSHOTVAL);
ftdf_time_t delta = cur_time - ftdf_start_csl_sample_time;
if (FTDF_txInProgress == FTDF_FALSE)
{
FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL);
FTDF_Time delta = curTime - FTDF_startCslSampleTime;
/* A delta larger than 0x80000000 is assumed to be negative */
/* Do not return a sleep value when CSL sample time is in the past */
if (delta < 0x80000000) {
return 0;
}
// A delta larger than 0x80000000 is assumed to be negative
// Do not return a sleep value when CSL sample time is in the past
if (delta < 0x80000000)
{
return 0;
}
return (FTDF_startCslSampleTime - curTime) * 16;
return (ftdf_start_csl_sample_time - cur_time) * 16;
} else {
return 0;
}
}
else
{
return 0;
}
}
#endif /* FTDF_NO_CSL */
#ifndef FTDF_NO_TSCH
if (FTDF_pib.tschEnabled)
{
if (ftdf_pib.tsch_enabled) {
#if FTDF_USE_SLEEP_DURING_BACKOFF
/* Abort sleep when LMAC is busy. */
if (FTDF_GET_FIELD(ON_OFF_REGMAP_LMACREADY4SLEEP) == 0)
{
return 0;
}
/* Abort sleep when LMAC is busy. */
if (REG_GETF(FTDF, FTDF_LMAC_CONTROL_STATUS_REG, LMACREADY4SLEEP) == 0) {
return 0;
}
#endif
FTDF_Time64 curTime64 = FTDF_getCurTime64();
FTDF_Time64 delta = curTime64 - FTDF_tschSlotTime;
ftdf_time64_t curTime64 = ftdf_get_cur_time64();
ftdf_time64_t delta = curTime64 - ftdf_tsch_slot_time;
// A delta larger than 0x8000000000000000 is assumed to be negative
// Do not return a sleep value when TSCH slot time is in the past
if (delta < 0x8000000000000000ULL)
{
return 0;
/* A delta larger than 0x8000000000000000 is assumed to be negative */
/* Do not return a sleep value when TSCH slot time is in the past */
if (delta < 0x8000000000000000ULL) {
return 0;
}
ftdf_usec_t sleep_time = (ftdf_usec_t)(ftdf_tsch_slot_time - curTime64);
ftdf_time_t pend_list_time;
ftdf_time_t curTime = REG_GETF(FTDF, FTDF_SYMBOLTIMESNAPSHOTVAL_REG, SYMBOLTIMESNAPSHOTVAL);
ftdf_boolean_t pending = ftdf_get_tx_pending_timer_head(&pend_list_time);
if (pending) {
/* A delta larger than 0x80000000 is assumed to be negative */
/* Do not return a sleep value when pending timer time is in the past */
if (curTime - pend_list_time < 0x80000000) {
return 0;
}
ftdf_usec_t tmp_sleep_time = (ftdf_usec_t)(pend_list_time - curTime);
if (tmp_sleep_time < sleep_time) {
sleep_time = tmp_sleep_time;
}
}
if (sleep_time < FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME) {
return 0;
}
return (sleep_time - (FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME)) * 16;
}
FTDF_USec sleepTime = (FTDF_USec)(FTDF_tschSlotTime - curTime64);
FTDF_Time pendListTime;
FTDF_Time curTime = FTDF_GET_FIELD(ON_OFF_REGMAP_SYMBOLTIMESNAPSHOTVAL);
FTDF_Boolean pending = FTDF_getTxPendingTimerHead(&pendListTime);
if (pending)
{
// A delta larger than 0x80000000 is assumed to be negative
// Do not return a sleep value when pending timer time is in the past
if (curTime - pendListTime < 0x80000000)
{
return 0;
}
FTDF_USec tmpSleepTime = (FTDF_USec)(pendListTime - curTime);
if (tmpSleepTime < sleepTime)
{
sleepTime = tmpSleepTime;
}
}
if (sleepTime < FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME)
{
return 0;
}
return (sleepTime - (FTDF_TSCH_MAX_PROCESS_REQUEST_TIME + FTDF_TSCH_MAX_SCHEDULE_TIME)) * 16;
}
#endif /* FTDF_NO_TSCH */
#ifndef FTDF_LITE
// Normal mode
int n;
/* Normal mode */
int n;
for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++)
{
if (FTDF_txPendingList[ n ].addrMode != FTDF_NO_ADDRESS)
{
return 0;
for (n = 0; n < FTDF_NR_OF_REQ_BUFFERS; n++) {
if (ftdf_tx_pending_list[n].addr_mode != FTDF_NO_ADDRESS) {
return 0;
}
}
}
#endif /* !FTDF_LITE */
#if FTDF_USE_SLEEP_DURING_BACKOFF
return FTDF_sdbGetSleepTime();
return ftdf_sdb_get_sleep_time();
#else /* FTDF_USE_SLEEP_DURING_BACKOFF */
return 0xffffffff;
return 0xffffffff;
#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */
}
FTDF_Boolean FTDF_prepareForSleep(FTDF_USec sleepTime)
ftdf_boolean_t ftdf_prepare_for_sleep(ftdf_usec_t sleep_time)
{
#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH)
if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) {
if (sleep_time < (2 * ftdf_low_power_clock_cycle_u_sec)) {
return FTDF_FALSE;
}
if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled)
{
if (sleepTime < 2 * FTDF_lowPowerClockCycleUSec)
{
return FTDF_FALSE;
// Correct sleeptime with the inaccuracy of this function
sleep_time -= (2 * ftdf_low_power_clock_cycle_u_sec);
if (sleep_time < (ftdf_wake_up_latency_u_sec + 500)) {
return FTDF_FALSE;
}
}
// Correct sleeptime with the inaccuracy of this function
sleepTime -= 2 * FTDF_lowPowerClockCycleUSec;
if (sleepTime < FTDF_wakeUpLatencyUSec + 500)
{
return FTDF_FALSE;
}
}
#endif
FTDF_criticalVar();
FTDF_enterCritical();
ftdf_critical_var();
ftdf_enter_critical();
#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH)
// Capture the current value of both the event generator and the timestamp generator
// and phase on the rising edge of LP_CLK
FTDF_SET_FIELD(ON_OFF_REGMAP_GETGENERATORVAL, 1);
/* Capture the current value of both the event generator and the timestamp generator
and phase on the rising edge of LP_CLK */
REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, GETGENERATORVAL, 1);
#endif
// Save current LMAC PM counters
FTDF_lmacCounters.fcsErrorCnt += FTDF_GET_FIELD(ON_OFF_REGMAP_MACFCSERRORCOUNT);
FTDF_lmacCounters.txStdAckCnt += FTDF_GET_FIELD(ON_OFF_REGMAP_MACTXSTDACKFRMCNT);
FTDF_lmacCounters.rxStdAckCnt += FTDF_GET_FIELD(ON_OFF_REGMAP_MACRXSTDACKFRMOKCNT);
/* Save current LMAC PM counters */
ftdf_lmac_counters.fcs_error_cnt += REG_GETF(FTDF, FTDF_MACFCSERRORCOUNT_REG, MACFCSERRORCOUNT);
ftdf_lmac_counters.tx_std_ack_cnt += REG_GETF(FTDF, FTDF_MACTXSTDACKFRMCNT_REG, MACTXSTDACKFRMCNT);
ftdf_lmac_counters.rx_std_ack_cnt += REG_GETF(FTDF, FTDF_MACRXSTDACKFRMOKCNT_REG, MACRXSTDACKFRMOKCNT);
#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH)
volatile uint32_t *getGeneratorValE = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_GETGENERATORVAL_E);
// Wait until data is ready
while ((*getGeneratorValE & MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E) == 0)
{ }
/* Wait until data is ready */
while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E) == 0) {}
FTDF_eventCurrVal = FTDF_GET_FIELD(ON_OFF_REGMAP_EVENTCURRVAL);
FTDF_timeStampCurrVal = FTDF_GET_FIELD(ON_OFF_REGMAP_TIMESTAMPCURRVAL);
FTDF_timeStampCurrPhaseVal = FTDF_GET_FIELD(ON_OFF_REGMAP_TIMESTAMPCURRPHASEVAL);
ftdf_event_curr_val = REG_GETF(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL);
ftdf_time_stamp_curr_val = REG_GETF(FTDF, FTDF_TIMESTAMPCURRVAL_REG, TIMESTAMPCURRVAL);
ftdf_time_stamp_curr_phase_val = REG_GETF(FTDF, FTDF_TIMESTAMPCURRPHASEVAL_REG, TIMESTAMPCURRPHASEVAL);
#ifdef SIMULATOR
*getGeneratorValE &= ~MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E;
REG_CLR_FIELD(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E, FTDF->FTDF_LMAC_CONTROL_DELTA_REG);
#else
*getGeneratorValE = MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E;
FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E);
#endif
uint64_t nextWakeUpThr;
uint64_t next_wake_up_thr;
#if FTDF_USE_SLEEP_DURING_BACKOFF
uint64_t picoSleepTime = (uint64_t)sleepTime * 1000000;
nextWakeUpThr = (picoSleepTime - FTDF_wakeUpLatency) / FTDF_lowPowerClockCycle;
uint64_t pico_sleep_time = (uint64_t)sleep_time * 1000000;
next_wake_up_thr = ( pico_sleep_time - ftdf_wake_up_latency ) / ftdf_low_power_clock_cycle;
#else /* FTDF_USE_SLEEP_DURING_BACKOFF */
if (FTDF_pib.leEnabled || FTDF_pib.tschEnabled)
{
uint64_t picoSleepTime = (uint64_t)sleepTime * 1000000;
nextWakeUpThr = (picoSleepTime - FTDF_wakeUpLatency) / FTDF_lowPowerClockCycle;
}
else
{
nextWakeUpThr = FTDF_csmacaWakeupThr;
}
if (ftdf_pib.le_enabled || ftdf_pib.tsch_enabled) {
uint64_t picoSleepTime = (uint64_t)sleep_time * 1000000;
next_wake_up_thr = (picoSleepTime - ftdf_wake_up_latency) / ftdf_low_power_clock_cycle;
} else {
next_wake_up_thr = ftdf_csmaca_wakeup_thr;
}
#endif /* FTDF_USE_SLEEP_DURING_BACKOFF */
// Set wake up threshold
uint32_t wakeUpIntThr = FTDF_eventCurrVal + nextWakeUpThr;
// Note that for IC revs other than A the size of WAKEUPINTTHR is 25 bits.
FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPINTTHR, wakeUpIntThr);
FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPENABLE, 1);
/* Set wake up threshold */
uint32_t wake_up_int_thr = ftdf_event_curr_val + next_wake_up_thr;
/* Note that for IC revs other than A the size of WAKEUPINTTHR is 25 bits. */
REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPINTTHR, wake_up_int_thr);
REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPENABLE, 1);
#endif
FTDF_exitCritical();
ftdf_exit_critical();
return FTDF_TRUE;
return FTDF_TRUE;
}
void FTDF_wakeUp(void)
void ftdf_wakeup(void)
{
#ifndef FTDF_PHY_API
FTDF_criticalVar();
FTDF_enterCritical();
ftdf_critical_var();
ftdf_enter_critical();
FTDF_SET_FIELD(ALWAYS_ON_REGMAP_WAKEUPENABLE, 0);
REG_SETF(FTDF, FTDF_WAKEUP_CONTROL_REG, WAKEUPENABLE, 0);
#if !defined(FTDF_NO_CSL) || !defined(FTDF_NO_TSCH)
// Capture the current value of both the event generator and the timestamp generator
// and phase on the rising edge of LP_CLK
FTDF_SET_FIELD(ON_OFF_REGMAP_GETGENERATORVAL, 1);
/* Capture the current value of both the event generator and the timestamp generator
and phase on the rising edge of LP_CLK */
REG_SETF(FTDF, FTDF_LMAC_CONTROL_OS_REG, GETGENERATORVAL, 1);
volatile uint32_t *getGeneratorValE = FTDF_GET_FIELD_ADDR(ON_OFF_REGMAP_GETGENERATORVAL_E);
/* Wait until data is ready */
while (REG_GETF(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E) == 0) {}
// Wait until data is ready
while ((*getGeneratorValE & MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E) == 0)
{ }
uint32_t eventNewCurrVal = FTDF_GET_FIELD(ON_OFF_REGMAP_EVENTCURRVAL);
uint32_t event_new_curr_val = REG_GETF(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL);
#ifdef SIMULATOR
*getGeneratorValE &= ~MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E;
REG_CLR_FIELD(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E);
#else
*getGeneratorValE = MSK_F_FTDF_ON_OFF_REGMAP_GETGENERATORVAL_E;
FTDF->FTDF_LMAC_CONTROL_DELTA_REG = REG_MSK(FTDF, FTDF_LMAC_CONTROL_DELTA_REG, GETGENERATORVAL_E);
#endif
// Backward calculate the time slept
//FTDF_PSec sleepTime = ( (uint64_t)( eventNewCurrVal - FTDF_eventCurrVal ) * FTDF_lowPowerClockCycle ) + FTDF_wakeUpLatency;
/* Backward calculate the time slept */
/* ftdf_psec_t sleep_time = ((uint64_t)(event_new_curr_val - ftdf_event_curr_val) *
ftdf_low_power_clock_cycle) + ftdf_wake_up_latency; */
FTDF_PSec sleepTime;
ftdf_psec_t sleep_time;
if (event_new_curr_val >= ftdf_event_curr_val) { /* Check for wraps. */
sleep_time = (event_new_curr_val - ftdf_event_curr_val) * ftdf_low_power_clock_cycle +
ftdf_wake_up_latency;
} else {
sleep_time = (event_new_curr_val +
(REG_MSK(FTDF, FTDF_EVENTCURRVAL_REG, EVENTCURRVAL) - ftdf_event_curr_val)) *
ftdf_low_power_clock_cycle + ftdf_wake_up_latency;
}
/* Calculate sync values */
uint64_t new_sync_vals = ((uint64_t)ftdf_time_stamp_curr_val << 8) |
(ftdf_time_stamp_curr_phase_val & 0xff);
if (eventNewCurrVal >= FTDF_eventCurrVal) /* Check for wraps. */
{
sleepTime = (eventNewCurrVal - FTDF_eventCurrVal) * FTDF_lowPowerClockCycle +
FTDF_wakeUpLatency;
}
else
{
sleepTime = (eventNewCurrVal +
(MSK_R_FTDF_ON_OFF_REGMAP_EVENTCURRVAL - FTDF_eventCurrVal)) *
FTDF_lowPowerClockCycle + FTDF_wakeUpLatency;
}
new_sync_vals += (sleep_time / 62500) + 1;
// Calculate sync values
uint64_t newSyncVals = ((uint64_t)FTDF_timeStampCurrVal << 8) | (FTDF_timeStampCurrPhaseVal & 0xff);
newSyncVals += (sleepTime / 62500) + 1;
uint32_t sync_timestamp_thr = ftdf_event_curr_val + (sleep_time / ftdf_low_power_clock_cycle);
uint32_t sync_timestamp_val = (new_sync_vals & 0xffffffff00) >> 8;
uint32_t sync_timestamp_phase_val = (new_sync_vals & 0xff);
uint32_t syncTimestampThr = FTDF_eventCurrVal + (sleepTime / FTDF_lowPowerClockCycle);
uint32_t syncTimestampVal = (newSyncVals & 0xffffffff00) >> 8;
uint32_t syncTimestampPhaseVal = (newSyncVals & 0xff);
// Set values
FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPTHR, syncTimestampThr);
FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPVAL, syncTimestampVal);
FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPPHASEVAL, syncTimestampPhaseVal);
FTDF_SET_FIELD(ON_OFF_REGMAP_SYNCTIMESTAMPENA, 1);
/* Set values */
REG_SETF(FTDF, FTDF_SYNCTIMESTAMPTHR_REG, SYNCTIMESTAMPTHR, sync_timestamp_thr);
REG_SETF(FTDF, FTDF_SYNCTIMESTAMPVAL_REG, SYNCTIMESTAMPVAL, sync_timestamp_val);
REG_SETF(FTDF, FTDF_SYNCTIMESTAMPPHASEVAL_REG, SYNCTIMESTAMPPHASEVAL, sync_timestamp_phase_val);
REG_SETF(FTDF, FTDF_TIMER_CONTROL_1_REG, SYNCTIMESTAMPENA, 1);
#endif
FTDF_exitCritical();
ftdf_exit_critical();
#ifndef FTDF_NO_CSL
FTDF_wakeUpEnableLe = FTDF_pib.leEnabled;
FTDF_pib.leEnabled = FTDF_FALSE;
ftdf_wake_up_enable_le = ftdf_pib.le_enabled;
ftdf_pib.le_enabled = FTDF_FALSE;
#endif /* FTDF_NO_CSL */
#ifndef FTDF_NO_TSCH
FTDF_wakeUpEnableTsch = FTDF_pib.tschEnabled;
FTDF_pib.tschEnabled = FTDF_FALSE;
ftdf_wake_up_enable_tsch = ftdf_pib.tsch_enabled;
ftdf_pib.tsch_enabled = FTDF_FALSE;
#endif /* FTDF_NO_TSCH */
#endif /* ! FTDF_PHY_API */
// Init LMAC
FTDF_initLmac();
/* Init LMAC */
ftdf_init_lmac();
}
#endif /* CONFIG_USE_FTDF */
third_party/dialog/DialogSDK/interfaces/ftdf/src/regmap.h
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