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[cc13x2,cc26x2] update CC13X2 CC26X2 driverlib (#3888)

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This commit is contained in:
Seth Rickard
2019-06-04 15:04:46 -07:00
committed by Jonathan Hui
parent f51598ea6c
commit b9d20b590e
137 changed files with 9449 additions and 8098 deletions
Download Patch File Download Diff File Expand all files Collapse all files
examples/platforms/cc1352/radio.c
+4 -36
View File
@@ -58,8 +58,6 @@
#include <inc/hw_memmap.h>
#include <inc/hw_prcm.h>
#include <rf_patches/rf_patch_cpe_ieee_802_15_4.h>
#include <rf_patches/rf_patch_mce_ieee_802_15_4.h>
#include <rf_patches/rf_patch_rfe_ieee_802_15_4.h>
enum
{
@@ -81,38 +79,10 @@ static output_config_t const *sCurrentOutputPower = &(rgOutputPower[0]);
/* Overrides from SmartRF Studio 7 2.10.0#94 */
static uint32_t sIEEEOverrides[] = {
// override_ieee_802_15_4.xml
// PHY: Use MCE RAM patch, RFE ROM bank 1
MCE_RFE_OVERRIDE(1, 0, 0, 0, 1, 0),
// Synth: Use 48 MHz crystal, enable extra PLL filtering
(uint32_t)0x02400403,
// Synth: Configure extra PLL filtering
(uint32_t)0x001C8473,
// Synth: Configure synth hardware
(uint32_t)0x00088433,
// Synth: Set minimum RTRIM to 3
(uint32_t)0x00038793,
// Synth: Configure faster calibration
HW32_ARRAY_OVERRIDE(0x4004, 1),
// Synth: Configure faster calibration
(uint32_t)0x1C0C0618,
// Synth: Configure faster calibration
(uint32_t)0xC00401A1,
// Synth: Configure faster calibration
(uint32_t)0x00010101,
// Synth: Configure faster calibration
(uint32_t)0xC0040141,
// Synth: Configure faster calibration
(uint32_t)0x00214AD3,
// Synth: Decrease synth programming time-out (0x0298 RAT ticks = 166 us)
(uint32_t)0x02980243,
// DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). In Rx, use DCDCCTL5[3:0]=0xC
// (DITHER_EN=1 and IPEAK=4).
(uint32_t)0xFCFC08C3,
// DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x3 (DITHER_EN=0 and IPEAK=3).
(uint32_t)0x00F388D3,
// Rx: Set LNA bias current offset to +15 to saturate trim to max (default: 0)
(uint32_t)0x000F8883,
// override_frontend_id.xml
(uint32_t)0xFFFFFFFF,
};
(uint32_t)0x000F8883, (uint32_t)0xFFFFFFFF};
/*
* Number of retry counts left to the currently transmitting frame.
@@ -919,13 +889,11 @@ static void rfCorePowerOff(void)
}
/**
* Applies CPE, RFE, and MCE patches to the radio.
* Applies CPE patche to the radio.
*/
static void rfCoreApplyPatch(void)
{
rf_patch_cpe_ieee_802_15_4();
rf_patch_mce_ieee_802_15_4();
rf_patch_rfe_ieee_802_15_4();
/* disable ram bus clocks */
RFCDoorbellSendTo(CMDR_DIR_CMD_2BYTE(CC1352_RF_CMD0, 0));
examples/platforms/cc2652/radio.c
+5 -36
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@@ -57,8 +57,6 @@
#include <inc/hw_prcm.h>
#include <inc/hw_rfc_pwr.h>
#include <rf_patches/rf_patch_cpe_ieee_802_15_4.h>
#include <rf_patches/rf_patch_mce_ieee_802_15_4.h>
#include <rf_patches/rf_patch_rfe_ieee_802_15_4.h>
enum
{
@@ -80,38 +78,10 @@ static output_config_t const *sCurrentOutputPower = &(rgOutputPower[0]);
/* Overrides from SmartRF Studio 7 2.10.0#94 */
static uint32_t sIEEEOverrides[] = {
// override_ieee_802_15_4.xml
// PHY: Use MCE RAM patch, RFE ROM bank 1
MCE_RFE_OVERRIDE(1, 0, 0, 0, 1, 0),
// Synth: Use 48 MHz crystal, enable extra PLL filtering
(uint32_t)0x02400403,
// Synth: Configure extra PLL filtering
(uint32_t)0x001C8473,
// Synth: Configure synth hardware
(uint32_t)0x00088433,
// Synth: Set minimum RTRIM to 3
(uint32_t)0x00038793,
// Synth: Configure faster calibration
HW32_ARRAY_OVERRIDE(0x4004, 1),
// Synth: Configure faster calibration
(uint32_t)0x1C0C0618,
// Synth: Configure faster calibration
(uint32_t)0xC00401A1,
// Synth: Configure faster calibration
(uint32_t)0x00010101,
// Synth: Configure faster calibration
(uint32_t)0xC0040141,
// Synth: Configure faster calibration
(uint32_t)0x00214AD3,
// Synth: Decrease synth programming time-out (0x0298 RAT ticks = 166 us)
(uint32_t)0x02980243,
// DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). In Rx, use DCDCCTL5[3:0]=0xC
// (DITHER_EN=1 and IPEAK=4).
(uint32_t)0xFCFC08C3,
// DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x3 (DITHER_EN=0 and IPEAK=3).
(uint32_t)0x00F388D3,
// Rx: Set LNA bias current offset to +15 to saturate trim to max (default: 0)
(uint32_t)0x000F8883,
// override_frontend_id.xml
(uint32_t)0xFFFFFFFF,
};
(uint32_t)0x000F8883, (uint32_t)0xFFFFFFFF};
/*
* Number of retry counts left to the currently transmitting frame.
@@ -918,13 +888,11 @@ static void rfCorePowerOff(void)
}
/**
* Applies CPE, RFE, and MCE patches to the radio.
* Applies CPE patche to the radio.
*/
static void rfCoreApplyPatch(void)
{
rf_patch_cpe_ieee_802_15_4();
rf_patch_mce_ieee_802_15_4();
rf_patch_rfe_ieee_802_15_4();
/* disable ram bus clocks */
RFCDoorbellSendTo(CMDR_DIR_CMD_2BYTE(CC2652_RF_CMD0, 0));
@@ -1415,6 +1383,7 @@ otError otPlatRadioSleep(otInstance *aInstance)
else
{
sState = cc2652_stateSleep;
error = OT_ERROR_NONE;
}
}
third_party/ti/README.md
Vendored
+4 -7
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@@ -1,11 +1,10 @@
#CC26XXware
## URL
<!-- TODO: UPDATE THIS for CC2650 / CC1352 / CC2652 --!>
http://www.ti.com/tool/simplelink-cc26x2-sdk
http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk
## Version
`driverlib_cc13xx_cc26xx_3_30_03_00`
`driverlib_cc13xx_cc26xx_3_05_06_18894`
## License
@@ -18,7 +17,7 @@ BSD-3-Clause
## Documentation
This version of cc26xxware is copied from the [SimpleLink CC26x2 Software
Development Kit](http://www.ti.com/tool/simplelink-cc26x2-sdk). Modifications
Development Kit](http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk). Modifications
were made to the software package to support the GCC Automake pedantic build.
Also see: release_notes_driverlib_cc13xx_cc26xx.html
@@ -31,9 +30,7 @@ Also see: release_notes_driverlib_cc13xx_cc26xx.html
| `device/cc13x52_cc26x2/linker_files/cc26x2r1f.lds` | `end` symbol added for GCC stdlib |
Documentation can be found within the [SimpleLink CC26x2 Software Development
Kit](http://www.ti.com/tool/simplelink-cc26x2-sdk).
**TODO** Update above link
Kit](http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk).
## Description
third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.c
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+3 -2
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@@ -1,7 +1,8 @@
/******************************************************************************
* Filename: crypto.c
* Revised: 2018-05-08 10:29:36 +0200 (Tue, 08 May 2018)
* Revision: 51973
* Revised: 2019-01-25 13:11:50 +0100 (Fri, 25 Jan 2019)
* Revision: 54285
*
* Description: Driver for the aes functions of the crypto module
*
third_party/ti/devices/cc13x2_cc26x2/driverlib/aes.h
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+15 -2
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@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: aes.h
* Revised: 2018-04-17 14:54:06 +0200 (Tue, 17 Apr 2018)
* Revision: 51890
* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019)
* Revision: 54287
*
* Description: AES header file.
*
@@ -583,6 +583,19 @@ __STATIC_INLINE void AESSetAuthLength(uint32_t length)
HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length;
}
//*****************************************************************************
//
//! \brief Reset the accelerator and cancel ongoing operations
//!
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void AESReset(void)
{
HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001;
}
//*****************************************************************************
//
//! \brief Enable individual crypto interrupt sources.
third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/ccs/driverlib.lib
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third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/ccs/makefile
Vendored
+3 -1
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@@ -73,6 +73,8 @@ all :
@ $(COMPILER_TOOL) --silicon_version=7M4 --float_support=FPv4SPD16 --code_state=16 --abi=eabi -me --opt_level=4 --opt_for_speed=0 --include_path=$(COMPILER_INCL) -g --gcc --define=ccs --display_error_number --diag_warning=225 --gen_func_subsections=on --preproc_with_compile "$(MAKEFILE_DIR)../../../driverlib/pwr_ctrl.c"
@ echo CCS: Compile rfc.c
@ $(COMPILER_TOOL) --silicon_version=7M4 --float_support=FPv4SPD16 --code_state=16 --abi=eabi -me --opt_level=4 --opt_for_speed=0 --include_path=$(COMPILER_INCL) -g --gcc --define=ccs --display_error_number --diag_warning=225 --gen_func_subsections=on --preproc_with_compile "$(MAKEFILE_DIR)../../../driverlib/rfc.c"
@ echo CCS: Compile rom_crypto.c
@ $(COMPILER_TOOL) --silicon_version=7M4 --float_support=FPv4SPD16 --code_state=16 --abi=eabi -me --opt_level=4 --opt_for_speed=0 --include_path=$(COMPILER_INCL) -g --gcc --define=ccs --display_error_number --diag_warning=225 --gen_func_subsections=on --preproc_with_compile "$(MAKEFILE_DIR)../../../driverlib/rom_crypto.c"
@ echo CCS: Compile setup.c
@ $(COMPILER_TOOL) --silicon_version=7M4 --float_support=FPv4SPD16 --code_state=16 --abi=eabi -me --opt_level=4 --opt_for_speed=0 --include_path=$(COMPILER_INCL) -g --gcc --define=ccs --display_error_number --diag_warning=225 --gen_func_subsections=on --preproc_with_compile "$(MAKEFILE_DIR)../../../driverlib/setup.c"
@ echo CCS: Compile setup_rom.c
@@ -104,7 +106,7 @@ all :
@ echo CCS: Compile watchdog.c
@ $(COMPILER_TOOL) --silicon_version=7M4 --float_support=FPv4SPD16 --code_state=16 --abi=eabi -me --opt_level=4 --opt_for_speed=0 --include_path=$(COMPILER_INCL) -g --gcc --define=ccs --display_error_number --diag_warning=225 --gen_func_subsections=on --preproc_with_compile "$(MAKEFILE_DIR)../../../driverlib/watchdog.c"
@ echo CCS: Archive driverlib.lib
@ $(ARCHIVER_TOOL) r "driverlib.lib" "$(MAKEFILE_DIR)adi.obj" "$(MAKEFILE_DIR)aes.obj" "$(MAKEFILE_DIR)aon_batmon.obj" "$(MAKEFILE_DIR)aon_event.obj" "$(MAKEFILE_DIR)aon_ioc.obj" "$(MAKEFILE_DIR)aon_pmctl.obj" "$(MAKEFILE_DIR)aon_rtc.obj" "$(MAKEFILE_DIR)aux_adc.obj" "$(MAKEFILE_DIR)aux_smph.obj" "$(MAKEFILE_DIR)aux_sysif.obj" "$(MAKEFILE_DIR)aux_tdc.obj" "$(MAKEFILE_DIR)ccfgread.obj" "$(MAKEFILE_DIR)chipinfo.obj" "$(MAKEFILE_DIR)cpu.obj" "$(MAKEFILE_DIR)crypto.obj" "$(MAKEFILE_DIR)ddi.obj" "$(MAKEFILE_DIR)debug.obj" "$(MAKEFILE_DIR)driverlib_release.obj" "$(MAKEFILE_DIR)event.obj" "$(MAKEFILE_DIR)flash.obj" "$(MAKEFILE_DIR)gpio.obj" "$(MAKEFILE_DIR)i2c.obj" "$(MAKEFILE_DIR)i2s.obj" "$(MAKEFILE_DIR)interrupt.obj" "$(MAKEFILE_DIR)ioc.obj" "$(MAKEFILE_DIR)osc.obj" "$(MAKEFILE_DIR)pka.obj" "$(MAKEFILE_DIR)prcm.obj" "$(MAKEFILE_DIR)pwr_ctrl.obj" "$(MAKEFILE_DIR)rfc.obj" "$(MAKEFILE_DIR)setup.obj" "$(MAKEFILE_DIR)setup_rom.obj" "$(MAKEFILE_DIR)sha2.obj" "$(MAKEFILE_DIR)smph.obj" "$(MAKEFILE_DIR)ssi.obj" "$(MAKEFILE_DIR)sw_chacha.obj" "$(MAKEFILE_DIR)sw_poly1305-donna.obj" "$(MAKEFILE_DIR)systick.obj" "$(MAKEFILE_DIR)sys_ctrl.obj" "$(MAKEFILE_DIR)timer.obj" "$(MAKEFILE_DIR)trng.obj" "$(MAKEFILE_DIR)uart.obj" "$(MAKEFILE_DIR)udma.obj" "$(MAKEFILE_DIR)vims.obj" "$(MAKEFILE_DIR)watchdog.obj"
@ $(ARCHIVER_TOOL) r "driverlib.lib" "$(MAKEFILE_DIR)adi.obj" "$(MAKEFILE_DIR)aes.obj" "$(MAKEFILE_DIR)aon_batmon.obj" "$(MAKEFILE_DIR)aon_event.obj" "$(MAKEFILE_DIR)aon_ioc.obj" "$(MAKEFILE_DIR)aon_pmctl.obj" "$(MAKEFILE_DIR)aon_rtc.obj" "$(MAKEFILE_DIR)aux_adc.obj" "$(MAKEFILE_DIR)aux_smph.obj" "$(MAKEFILE_DIR)aux_sysif.obj" "$(MAKEFILE_DIR)aux_tdc.obj" "$(MAKEFILE_DIR)ccfgread.obj" "$(MAKEFILE_DIR)chipinfo.obj" "$(MAKEFILE_DIR)cpu.obj" "$(MAKEFILE_DIR)crypto.obj" "$(MAKEFILE_DIR)ddi.obj" "$(MAKEFILE_DIR)debug.obj" "$(MAKEFILE_DIR)driverlib_release.obj" "$(MAKEFILE_DIR)event.obj" "$(MAKEFILE_DIR)flash.obj" "$(MAKEFILE_DIR)gpio.obj" "$(MAKEFILE_DIR)i2c.obj" "$(MAKEFILE_DIR)i2s.obj" "$(MAKEFILE_DIR)interrupt.obj" "$(MAKEFILE_DIR)ioc.obj" "$(MAKEFILE_DIR)osc.obj" "$(MAKEFILE_DIR)pka.obj" "$(MAKEFILE_DIR)prcm.obj" "$(MAKEFILE_DIR)pwr_ctrl.obj" "$(MAKEFILE_DIR)rfc.obj" "$(MAKEFILE_DIR)rom_crypto.obj" "$(MAKEFILE_DIR)setup.obj" "$(MAKEFILE_DIR)setup_rom.obj" "$(MAKEFILE_DIR)sha2.obj" "$(MAKEFILE_DIR)smph.obj" "$(MAKEFILE_DIR)ssi.obj" "$(MAKEFILE_DIR)sw_chacha.obj" "$(MAKEFILE_DIR)sw_poly1305-donna.obj" "$(MAKEFILE_DIR)systick.obj" "$(MAKEFILE_DIR)sys_ctrl.obj" "$(MAKEFILE_DIR)timer.obj" "$(MAKEFILE_DIR)trng.obj" "$(MAKEFILE_DIR)uart.obj" "$(MAKEFILE_DIR)udma.obj" "$(MAKEFILE_DIR)vims.obj" "$(MAKEFILE_DIR)watchdog.obj"
@ rm -f $(MAKEFILE_DIR)*.obj
# Deletes previous output and temporary files
third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/gcc/driverlib.a
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third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/gcc/makefile
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+3 -1
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@@ -73,6 +73,8 @@ all :
@ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "pwr_ctrl.o" $(MAKEFILE_DIR)../../../driverlib/pwr_ctrl.c
@ echo GCC: Compile rfc.c
@ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "rfc.o" $(MAKEFILE_DIR)../../../driverlib/rfc.c
@ echo GCC: Compile rom_crypto.c
@ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "rom_crypto.o" $(MAKEFILE_DIR)../../../driverlib/rom_crypto.c
@ echo GCC: Compile setup.c
@ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "setup.o" $(MAKEFILE_DIR)../../../driverlib/setup.c
@ echo GCC: Compile setup_rom.c
@@ -104,7 +106,7 @@ all :
@ echo GCC: Compile watchdog.c
@ $(COMPILER_TOOL) -mthumb -march=armv7e-m -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -Os -Wall -fno-strict-aliasing -gstrict-dwarf -pedantic -ffunction-sections -fdata-sections -std=c99 -c --asm -g -o "watchdog.o" $(MAKEFILE_DIR)../../../driverlib/watchdog.c
@ echo GCC: Archive driverlib.lib
@ $(ARCHIVER_TOOL) rcs $(MAKEFILE_DIR)driverlib.lib $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o
@ $(ARCHIVER_TOOL) rcs $(MAKEFILE_DIR)driverlib.lib $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)rom_crypto.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o
@ rm -f $(MAKEFILE_DIR)*.o
# Deletes previous output and temporary files
third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/driverlib.lib
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third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/iar/makefile
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@@ -108,6 +108,9 @@ all :
@ echo IAR: Compile rfc.c
@ $(COMPILER_TOOL) $(MAKEFILE_DIR)../../../driverlib/rfc.c -D nDEBUG $(ADD_PARAM) -o $(MAKEFILE_DIR)rfc.o --no_clustering --debug --endian=little --cpu=Cortex-M4 -e --fpu=FPv4_sp -Ohz --require_prototypes --silent
@ $(OBJ_MANIP_TOOL) --remove_file_path --remove_section ".comment" --silent $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)rfc.o
@ echo IAR: Compile rom_crypto.c
@ $(COMPILER_TOOL) $(MAKEFILE_DIR)../../../driverlib/rom_crypto.c -D nDEBUG $(ADD_PARAM) -o $(MAKEFILE_DIR)rom_crypto.o --no_clustering --debug --endian=little --cpu=Cortex-M4 -e --fpu=FPv4_sp -Ohz --require_prototypes --silent
@ $(OBJ_MANIP_TOOL) --remove_file_path --remove_section ".comment" --silent $(MAKEFILE_DIR)rom_crypto.o $(MAKEFILE_DIR)rom_crypto.o
@ echo IAR: Compile setup.c
@ $(COMPILER_TOOL) $(MAKEFILE_DIR)../../../driverlib/setup.c -D nDEBUG $(ADD_PARAM) -o $(MAKEFILE_DIR)setup.o --no_clustering --debug --endian=little --cpu=Cortex-M4 -e --fpu=FPv4_sp -Ohz --require_prototypes --silent
@ $(OBJ_MANIP_TOOL) --remove_file_path --remove_section ".comment" --silent $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup.o
@@ -154,7 +157,7 @@ all :
@ $(COMPILER_TOOL) $(MAKEFILE_DIR)../../../driverlib/watchdog.c -D nDEBUG $(ADD_PARAM) -o $(MAKEFILE_DIR)watchdog.o --no_clustering --debug --endian=little --cpu=Cortex-M4 -e --fpu=FPv4_sp -Ohz --require_prototypes --silent
@ $(OBJ_MANIP_TOOL) --remove_file_path --remove_section ".comment" --silent $(MAKEFILE_DIR)watchdog.o $(MAKEFILE_DIR)watchdog.o
@ echo IAR: Archive driverlib.lib
@ $(ARCHIVER_TOOL) $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o --create -o $(MAKEFILE_DIR)driverlib.lib
@ $(ARCHIVER_TOOL) $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)rom_crypto.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o --create -o $(MAKEFILE_DIR)driverlib.lib
@ rm -f $(MAKEFILE_DIR)*.o
# Deletes previous output and temporary files
third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/keil/driverlib.lib
Vendored
BIN
View File
Binary file not shown.
third_party/ti/devices/cc13x2_cc26x2/driverlib/bin/keil/makefile
Vendored
+3 -1
View File
@@ -73,6 +73,8 @@ all :
@ $(COMPILER_TOOL) -c --cpu=Cortex-M4.fp.sp --fpu=FPv4-SP -D__EVAL --li -O3 -Ospace --apcs=interwork --c99 --reduce_paths -Drvmdk -o "pwr_ctrl.o" $(MAKEFILE_DIR)../../../driverlib/pwr_ctrl.c
@ echo KEIL: Compile rfc.c
@ $(COMPILER_TOOL) -c --cpu=Cortex-M4.fp.sp --fpu=FPv4-SP -D__EVAL --li -O3 -Ospace --apcs=interwork --c99 --reduce_paths -Drvmdk -o "rfc.o" $(MAKEFILE_DIR)../../../driverlib/rfc.c
@ echo KEIL: Compile rom_crypto.c
@ $(COMPILER_TOOL) -c --cpu=Cortex-M4.fp.sp --fpu=FPv4-SP -D__EVAL --li -O3 -Ospace --apcs=interwork --c99 --reduce_paths -Drvmdk -o "rom_crypto.o" $(MAKEFILE_DIR)../../../driverlib/rom_crypto.c
@ echo KEIL: Compile setup.c
@ $(COMPILER_TOOL) -c --cpu=Cortex-M4.fp.sp --fpu=FPv4-SP -D__EVAL --li -O3 -Ospace --apcs=interwork --c99 --reduce_paths -Drvmdk -o "setup.o" $(MAKEFILE_DIR)../../../driverlib/setup.c
@ echo KEIL: Compile setup_rom.c
@@ -104,7 +106,7 @@ all :
@ echo KEIL: Compile watchdog.c
@ $(COMPILER_TOOL) -c --cpu=Cortex-M4.fp.sp --fpu=FPv4-SP -D__EVAL --li -O3 -Ospace --apcs=interwork --c99 --reduce_paths -Drvmdk -o "watchdog.o" $(MAKEFILE_DIR)../../../driverlib/watchdog.c
@ echo KEIL: Archive driverlib.lib
@ $(ARCHIVER_TOOL) --create $(MAKEFILE_DIR)driverlib.lib $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o
@ $(ARCHIVER_TOOL) --create $(MAKEFILE_DIR)driverlib.lib $(MAKEFILE_DIR)adi.o $(MAKEFILE_DIR)aes.o $(MAKEFILE_DIR)aon_batmon.o $(MAKEFILE_DIR)aon_event.o $(MAKEFILE_DIR)aon_ioc.o $(MAKEFILE_DIR)aon_pmctl.o $(MAKEFILE_DIR)aon_rtc.o $(MAKEFILE_DIR)aux_adc.o $(MAKEFILE_DIR)aux_smph.o $(MAKEFILE_DIR)aux_sysif.o $(MAKEFILE_DIR)aux_tdc.o $(MAKEFILE_DIR)ccfgread.o $(MAKEFILE_DIR)chipinfo.o $(MAKEFILE_DIR)cpu.o $(MAKEFILE_DIR)crypto.o $(MAKEFILE_DIR)ddi.o $(MAKEFILE_DIR)debug.o $(MAKEFILE_DIR)driverlib_release.o $(MAKEFILE_DIR)event.o $(MAKEFILE_DIR)flash.o $(MAKEFILE_DIR)gpio.o $(MAKEFILE_DIR)i2c.o $(MAKEFILE_DIR)i2s.o $(MAKEFILE_DIR)interrupt.o $(MAKEFILE_DIR)ioc.o $(MAKEFILE_DIR)osc.o $(MAKEFILE_DIR)pka.o $(MAKEFILE_DIR)prcm.o $(MAKEFILE_DIR)pwr_ctrl.o $(MAKEFILE_DIR)rfc.o $(MAKEFILE_DIR)rom_crypto.o $(MAKEFILE_DIR)setup.o $(MAKEFILE_DIR)setup_rom.o $(MAKEFILE_DIR)sha2.o $(MAKEFILE_DIR)smph.o $(MAKEFILE_DIR)ssi.o $(MAKEFILE_DIR)sw_chacha.o $(MAKEFILE_DIR)sw_poly1305-donna.o $(MAKEFILE_DIR)systick.o $(MAKEFILE_DIR)sys_ctrl.o $(MAKEFILE_DIR)timer.o $(MAKEFILE_DIR)trng.o $(MAKEFILE_DIR)uart.o $(MAKEFILE_DIR)udma.o $(MAKEFILE_DIR)vims.o $(MAKEFILE_DIR)watchdog.o
@ rm -f $(MAKEFILE_DIR)*.o
# Deletes previous output and temporary files
third_party/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c
Vendored
+12 -8
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: chipinfo.c
* Revised: 2018-01-29 18:45:34 +0100 (Mon, 29 Jan 2018)
* Revision: 51355
* Revised: 2018-08-17 09:28:06 +0200 (Fri, 17 Aug 2018)
* Revision: 52354
*
* Description: Collection of functions returning chip information.
*
@@ -55,8 +55,8 @@
#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily
#undef ChipInfo_GetHwRevision
#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision
#undef ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated
#define ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated
#undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#endif
//*****************************************************************************
@@ -183,6 +183,9 @@ ChipInfo_GetHwRevision( void )
case 2 : // CC13x2, CC26x2 - PG1.1 (or later)
hwRev = (HwRevision_t)(((uint32_t)HWREV_1_1 ) + minorHwRev );
break;
case 3 : // CC13x2, CC26x2 - PG2.1 (or later)
hwRev = (HwRevision_t)(((uint32_t)HWREV_2_1 ) + minorHwRev );
break;
}
}
@@ -190,16 +193,17 @@ ChipInfo_GetHwRevision( void )
}
//*****************************************************************************
// ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated()
// ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated()
//*****************************************************************************
void
ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated( void )
ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void )
{
if ( ! ChipInfo_ChipFamilyIs_CC13x2_CC26x2() )
if (( ! ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) ||
( ! ChipInfo_HwRevisionIs_GTEQ_2_0() ) )
{
while(1)
{
// This driverlib version is for the CC13x2/CC26x2 chips.
// This driverlib version is for the CC13x2/CC26x2 PG2.0 and later chips.
// Do nothing - stay here forever
}
}
third_party/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h
Vendored
+8 -8
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: chipinfo.h
* Revised: 2018-05-01 11:59:00 +0200 (Tue, 01 May 2018)
* Revision: 51944
* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018)
* Revision: 52189
*
* Description: Collection of functions returning chip information.
*
@@ -84,7 +84,7 @@ extern "C"
#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType
#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily
#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision
#define ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated
#define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#endif
//*****************************************************************************
@@ -624,12 +624,12 @@ ChipInfo_HwRevisionIs_GTEQ_2_4( void )
//*****************************************************************************
//
//! \brief Verifies that current chip is CC13x2 or CC26x2 and never returns if violated.
//! \brief Verifies that current chip is CC13x2 or CC26x2 PG2.0 or later and never returns if violated.
//!
//! \return None
//
//*****************************************************************************
extern void ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated( void );
extern void ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void );
//*****************************************************************************
//
@@ -659,9 +659,9 @@ extern void ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated( void );
#undef ChipInfo_GetHwRevision
#define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision
#endif
#ifdef ROM_ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated
#undef ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated
#define ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated ROM_ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated
#ifdef ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
#endif
#endif
third_party/ti/devices/cc13x2_cc26x2/driverlib/cpu.h
Vendored
+4 -4
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: cpu.h
* Revised: 2017-08-21 13:20:52 +0200 (Mon, 21 Aug 2017)
* Revision: 49618
* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
* Revision: 52111
*
* Description: Defines and prototypes for the CPU instruction wrapper
* functions.
@@ -145,7 +145,7 @@ extern uint32_t CPUbasepriGet(void);
//*****************************************************************************
//
//! \brief Provide a small delay using a simple loop counter.
//! \brief Provide a small non-zero delay using a simple loop counter.
//!
//! This function provides means for generating a constant length delay. It
//! is written in assembly to keep the delay consistent across tool chains,
@@ -171,7 +171,7 @@ extern uint32_t CPUbasepriGet(void);
//! Example: 250 us delay with code in flash and with cache and prefetch enabled:
//! - ui32Count = 250 * 48 / 4 = 3000
//!
//! \param ui32Count is the number of delay loop iterations to perform.
//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero.
//!
//! \return None
//
third_party/ti/devices/cc13x2_cc26x2/driverlib/ddi.c
Vendored
+3 -3
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: ddi.c
* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
* Revision: 48852
* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
* Revision: 52111
*
* Description: Driver for the DDI master interface
*
@@ -110,7 +110,7 @@ DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg,
//*****************************************************************************
//
// Write a bitfield via the DDI using 16-bit maskable write
// Write a bit field via the DDI using 16-bit maskable write
//
//*****************************************************************************
void
third_party/ti/devices/cc13x2_cc26x2/driverlib/ddi.h
Vendored
+13 -47
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: ddi.h
* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
* Revision: 47343
* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
* Revision: 52111
*
* Description: Defines and prototypes for the DDI master interface.
*
@@ -151,9 +151,6 @@ DDIBaseValid(uint32_t ui32Base)
//! This function will read a register in the analog domain and return
//! the value as an \c uint32_t.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is DDI base address.
//! \param ui32Reg is the 32 bit register to read.
//!
@@ -182,9 +179,6 @@ DDI32RegRead(uint32_t ui32Base, uint32_t ui32Reg)
//! DDI slave. Only bits in the selected register are affected by the
//! operation.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is DDI base address.
//! \param ui32Reg is the base register to assert the bits in.
//! \param ui32Val is the 32 bit one-hot encoded value specifying which
@@ -216,9 +210,6 @@ DDI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
//!
//! This function will clear bits in a register in the analog domain.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is DDI base address.
//! \param ui32Reg is the base registers to clear the bits in.
//! \param ui32Val is the 32 bit one-hot encoded value specifying which
@@ -252,14 +243,11 @@ DDI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg,
//! This function allows byte (8 bit access) to the DDI slave registers.
//!
//! Use this function to write any value in the range 0-7 bits aligned on a
//! byte boundary. Fx. for writing the value 0b101 to bits 1-3 set
//! byte boundary. For example, for writing the value 0b101 to bits 1-3 set
//! <tt>ui16Val = 0x0A</tt> and <tt>ui16Mask = 0x0E</tt>. Bits 0 and 5-7 will
//! not be affected by the operation, as long as the corresponding bits are
//! not set in the \c ui16Mask.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is the Least Significant Register in the DDI slave that
//! will be affected by the write operation.
@@ -300,14 +288,11 @@ DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte,
//! This function allows 16 bit masked access to the DDI slave registers.
//!
//! Use this function to write any value in the range 0-15 bits aligned on a
//! half-word boundary. Fx. for writing the value 0b101 to bits 1-3 set
//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set
//! <tt>ui32Val = 0x000A</tt> and <tt>ui32Mask = 0x000E</tt>. Bits 0 and 5-15 will not be
//! affected by the operation, as long as the corresponding bits are not set
//! in the \c ui32Mask.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is register to access.
//! \param bWriteHigh defines which part of the register to write in.
@@ -350,9 +335,6 @@ DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh,
//! conservation of the previous value of the register will be kept (i.e. this
//! is NOT read-modify-write on the register).
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is DDI base address.
//! \param ui32Reg is the register to write.
//! \param ui32Val is the 32 bit value to write to the register.
@@ -368,15 +350,10 @@ extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
//!
//! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is register to access.
//! \param ui32Mask is the mask defining which of the 16 bit that should be
//! overwritten. The mask must be defined in the lower half of the 32 bits.
//! \param ui32WrData is the value to write. The value must be defined in the lower
//! half of the 32 bits.
//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten.
//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits.
//!
//! \return None
//
@@ -389,17 +366,13 @@ extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg,
//
//! \brief Write a bit field via the DDI using 16-bit maskable write.
//!
//! Requires that bitfields not space the low/high word boundary.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//! Requires that entire bit field is within the half word boundary.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is register to access.
//! \param ui32Mask is the mask defining which of the 16 bits that should be
//! overwritten. The mask must be defined in the lower half of the 32 bits.
//! \param ui32Shift
//! \param ui32Data
//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten.
//! \param ui32Shift is the shift value for the bit field.
//! \param ui32Data is the data aligned to bit 0.
//!
//! \return None
//
@@ -412,9 +385,6 @@ extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg,
//
//! \brief Read a bit via the DDI using 16-bit read.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//!
//! \param ui32Base is the base address of the DDI module.
//! \param ui32Reg is the register to read.
//! \param ui32Mask defines the bit which should be read.
@@ -427,17 +397,13 @@ extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg,
//*****************************************************************************
//
//! \brief Read a bitfield via the DDI using 16-bit read.
//! \brief Read a bit field via the DDI using 16-bit read.
//!
//! Requires that bit fields do not space the low/high word boundary.
//!
//! \note Both the AUX module and the clock for the AUX SMPH module must be
//! enabled before calling this function.
//! Requires that entire bit field is within the half word boundary.
//!
//! \param ui32Base is the base address of the DDI port.
//! \param ui32Reg is register to access.
//! \param ui32Mask is the mask defining which of the 16 bits that should be
//! overwritten. The mask must be defined in the lower half of the 32 bits.
//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten.
//! \param ui32Shift defines the required shift of the data to align with bit 0.
//!
//! \return Returns data aligned to bit 0.
third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c
Vendored
+1 -1
View File
@@ -42,4 +42,4 @@
/// Declare the current DriverLib release
DRIVERLIB_DECLARE_RELEASE(0, 51995);
DRIVERLIB_DECLARE_RELEASE(0, 54539);
third_party/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h
Vendored
+3 -3
View File
@@ -63,7 +63,7 @@ extern "C"
/// DriverLib release group number
#define DRIVERLIB_RELEASE_GROUP 0
/// DriverLib release build number
#define DRIVERLIB_RELEASE_BUILD 51995
#define DRIVERLIB_RELEASE_BUILD 54539
@@ -83,7 +83,7 @@ extern "C"
const volatile uint8_t driverlib_release_##group##_##build
/// External declaration of the DriverLib release locking object
extern DRIVERLIB_DECLARE_RELEASE(0, 51995);
extern DRIVERLIB_DECLARE_RELEASE(0, 54539);
@@ -135,7 +135,7 @@ extern DRIVERLIB_DECLARE_RELEASE(0, 51995);
//
//*****************************************************************************
#define DRIVERLIB_ASSERT_CURR_RELEASE() \
DRIVERLIB_ASSERT_RELEASE(0, 51995)
DRIVERLIB_ASSERT_RELEASE(0, 54539)
third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s.h
Vendored
+533 -18
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: i2s.h
* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
* Revision: 49048
* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018)
* Revision: 53356
*
* Description: Defines and prototypes for the I2S.
*
@@ -97,6 +97,8 @@ extern "C"
//! \brief A structure that defines an audio control table. Note: Memory for this
//! structure \b must be initialized by user application. See detailed description!
//!
//! \deprecated This structure will be removed in a future release.
//!
//! These fields are used by the I2S and normally it is not necessary for
//! software to directly read or write fields in the table.
//!
@@ -113,6 +115,7 @@ extern "C"
//!
//
//*****************************************************************************
#ifndef DEPRECATED
typedef struct
{
uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples.
@@ -125,6 +128,7 @@ typedef struct
uint32_t ui32OutBase; //!< Base address of the output buffer.
uint32_t ui32OutOffset; //!< Value of the current output pointer offset.
} I2SControlTable;
#endif
//*****************************************************************************
//
@@ -137,42 +141,51 @@ typedef struct
// g_pControlTable = &g_controlTable;
//
//*****************************************************************************
#ifndef DEPRECATED
extern I2SControlTable *g_pControlTable;
#endif
//*****************************************************************************
//
// Defines for the I2S DMA buffer sizes
//
//*****************************************************************************
#ifndef DEPRECATED
#define I2S_DMA_BUF_SIZE_64 0x00000040
#define I2S_DMA_BUF_SIZE_128 0x00000080
#define I2S_DMA_BUF_SIZE_256 0x00000100
#endif
//*****************************************************************************
//
// Defines for the I2S audio clock configuration
//
//*****************************************************************************
#ifndef DEPRECATED
#define I2S_EXT_WCLK 0x00000001
#define I2S_INT_WCLK 0x00000002
#define I2S_INVERT_WCLK 0x00000004
#define I2S_NORMAL_WCLK 0x00000000
#endif
//*****************************************************************************
//
// Defines for the audio data line input/output configuration
//
//*****************************************************************************
#ifndef DEPRECATED
#define I2S_LINE_UNUSED 0x00000000
#define I2S_LINE_INPUT 0x00000001
#define I2S_LINE_OUTPUT 0x00000002
#define I2S_LINE_MASK 0x00000003
#endif
//*****************************************************************************
//
// Defines for activating an audio channel.
//
//*****************************************************************************
#ifndef DEPRECATED
#define I2S_CHAN0_ACT 0x00000100
#define I2S_CHAN1_ACT 0x00000200
#define I2S_CHAN2_ACT 0x00000400
@@ -184,6 +197,16 @@ extern I2SControlTable *g_pControlTable;
#define I2S_MONO_MODE 0x00000100
#define I2S_STEREO_MODE 0x00000300
#define I2S_CHAN_CFG_MASK 0x0000FF00
#endif
#define I2S_CHAN0_MASK 0x00000001
#define I2S_CHAN1_MASK 0x00000002
#define I2S_CHAN2_MASK 0x00000004
#define I2S_CHAN3_MASK 0x00000008
#define I2S_CHAN4_MASK 0x00000010
#define I2S_CHAN5_MASK 0x00000020
#define I2S_CHAN6_MASK 0x00000040
#define I2S_CHAN7_MASK 0x00000080
//*****************************************************************************
//
@@ -205,8 +228,10 @@ extern I2SControlTable *g_pControlTable;
// Defines for the sample stamp counters
//
//*****************************************************************************
#ifndef DEPRECATED
#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0
#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1
#endif
#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when
// calculating the sample stamp
@@ -255,6 +280,8 @@ I2SBaseValid(uint32_t ui32Base)
//
//! \brief Enables the I2S module for operation.
//!
//! \deprecated This function will be removed in a future release.
//!
//! \note The module should only be enabled after configuration. When the
//! module is disabled, no data or clocks will be generated on the I2S signals.
//!
@@ -268,12 +295,16 @@ I2SBaseValid(uint32_t ui32Base)
//! \return None
//
//*****************************************************************************
#ifndef DEPRECATED
extern void I2SEnable(uint32_t ui32Base);
#endif
//*****************************************************************************
//
//! \brief Disables the I2S module for operation.
//!
//! \deprecated This function will be removed in a future release.
//!
//! This function will immediately disable the I2S module. To ensure that
//! all buffer operations are completed before shutting down, the correct
//! procedure is:
@@ -288,6 +319,7 @@ extern void I2SEnable(uint32_t ui32Base);
//! \return None
//
//*****************************************************************************
#ifndef DEPRECATED
__STATIC_INLINE void
I2SDisable(uint32_t ui32Base)
{
@@ -297,11 +329,14 @@ I2SDisable(uint32_t ui32Base)
// Disable the I2S module.
HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x0;
}
#endif
//*****************************************************************************
//
//! \brief Configures the I2S module.
//!
//! \deprecated This function will be removed in a future release.
//!
//! The word length defines the size of the word transmitted on the data
//! lines. For single phased formats \c I2S_WORD_LENGTH_x is the exact number
//! of bits per word. In dual phased format this is the maximum number of bits
@@ -337,13 +372,17 @@ I2SDisable(uint32_t ui32Base)
//! \sa \ref I2SChannelConfigure()
//
//*****************************************************************************
#ifndef DEPRECATED
extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg,
uint32_t ui32BitClkDelay);
#endif
//****************************************************************************
//
//! \brief Setup the audio channel configuration.
//!
//! \deprecated This function will be removed in a future release.
//!
//! The channel configuration is a bitwise OR of the input/output mode of each
//! data line and the active audio channels within a specific audio frame.
//!
@@ -380,13 +419,17 @@ extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg,
//! \sa \ref I2SAudioFormatConfigure()
//
//****************************************************************************
#ifndef DEPRECATED
extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg,
uint32_t ui32Chan1Cfg);
#endif
//****************************************************************************
//
//! \brief Configure the I2S frame clock.
//!
//! \deprecated This function will be removed in a future release.
//!
//! Configure I2S clock to be either internal or external and either normal
//! or inverted.
//!
@@ -407,6 +450,7 @@ extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg,
//! \return None
//
//****************************************************************************
#ifndef DEPRECATED
__STATIC_INLINE void
I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig)
{
@@ -418,11 +462,14 @@ I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig)
(I2S_AIFWCLKSRC_WCLK_INV_M |
I2S_AIFWCLKSRC_WCLK_SRC_M);
}
#endif
//****************************************************************************
//
//! \brief Set the input buffer pointers.
//!
//! \deprecated This function will be removed in a future release.
//!
//! The next pointer should always be written while the DMA is using the
//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will
//! occur and all outputs will be disabled.
@@ -439,14 +486,18 @@ I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig)
//! \return None
//
//****************************************************************************
#ifndef DEPRECATED
extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase,
uint32_t ui32OutBufBase, uint16_t ui16DMABufSize,
uint16_t ui16ChanBufSize);
#endif
//****************************************************************************
//
//! \brief Update the buffer pointers.
//!
//! \deprecated This function will be removed in a future release.
//!
//! The next pointer should always be written while the DMA is using the
//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur
//! and all outputs will be disabled. Nothing is preventing the pointers from
@@ -466,12 +517,16 @@ extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase,
//! \sa \ref I2SPointerSet()
//
//****************************************************************************
#ifndef DEPRECATED
extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput);
#endif
//****************************************************************************
//
//! \brief Set a buffer pointer (input or output) directly.
//!
//! \deprecated This function will be removed in a future release.
//!
//! This function allows bypassing of the pointers in the global control table.
//!
//! The next pointer should always be written while the DMA is using the
@@ -494,12 +549,16 @@ extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput);
//! \sa \ref I2SPointerUpdate()
//
//****************************************************************************
#ifndef DEPRECATED
extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer);
#endif
//*****************************************************************************
//
//! \brief Registers an interrupt handler for an I2S interrupt in the dynamic interrupt table.
//!
//! \deprecated This function will be removed in a future release.
//!
//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
//!
//! This function registers a function as the interrupt handler for a specific
@@ -518,6 +577,7 @@ extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer);
//! handlers.
//
//*****************************************************************************
#ifndef DEPRECATED
__STATIC_INLINE void
I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
{
@@ -530,11 +590,14 @@ I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
// Enable the I2S interrupt.
IntEnable(INT_I2S_IRQ);
}
#endif
//*****************************************************************************
//
//! \brief Unregisters an interrupt handler for a I2S interrupt in the dynamic interrupt table.
//!
//! \deprecated This function will be removed in a future release.
//!
//! This function does the actual unregistering of the interrupt handler. It
//! clears the handler to be called when an I2S interrupt occurs. This
//! function also masks off the interrupt in the interrupt controller so that
@@ -548,6 +611,7 @@ I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
//! handlers.
//
//*****************************************************************************
#ifndef DEPRECATED
__STATIC_INLINE void
I2SIntUnregister(uint32_t ui32Base)
{
@@ -560,6 +624,27 @@ I2SIntUnregister(uint32_t ui32Base)
// Unregister the interrupt handler.
IntUnregister(INT_I2S_IRQ);
}
#endif
//*****************************************************************************
//
//! \brief Configure the sample stamp generator.
//!
//! \deprecated This function will be removed in a future release.
//!
//! Use this function to configure the sample stamp generator.
//!
//! \param ui32Base is the base address of the I2S module.
//! \param bInput enables triggering of the sample stamp generator on input.
//! \param bOutput enables triggering of the sample stamp generator on output.
//!
//! \return None
//
//*****************************************************************************
#ifndef DEPRECATED
extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput,
bool bOutput);
#endif
//*****************************************************************************
//
@@ -732,6 +817,9 @@ I2SIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
__STATIC_INLINE void
I2SSampleStampEnable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Set the enable bit.
HWREG(I2S0_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMP_EN;
}
@@ -749,27 +837,14 @@ I2SSampleStampEnable(uint32_t ui32Base)
__STATIC_INLINE void
I2SSampleStampDisable(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Clear the enable bit.
HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0;
}
//*****************************************************************************
//
//! \brief Configure the sample stamp generator.
//!
//! Use this function to configure the sample stamp generator.
//!
//! \param ui32Base is the base address of the I2S module.
//! \param bInput enables triggering of the sample stamp generator on input.
//! \param bOutput enables triggering of the sample stamp generator on output.
//!
//! \return None
//
//*****************************************************************************
extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput,
bool bOutput);
//*****************************************************************************
//
//! \brief Get the current value of a sample stamp counter.
@@ -782,6 +857,446 @@ extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput,
//*****************************************************************************
extern uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel);
//*****************************************************************************
//
//! \brief Starts the I2S.
//!
//! I2S must be configured before it is started.
//!
//! \note Immediately after enabling the module the programmer must update
//! the DMA data pointer registers using \ref I2SInPointerSet() and
//! \ref I2SOutPointerSet() to ensure a new pointer is written before the DMA
//! transfer completes. Failure to update the pointer in time will result in
//! an \ref I2S_INT_PTR_ERR.
//!
//! \param ui32Base is the I2S module base address.
//! \param ui8FixDMALength is the length of the DMA buffer: this will allow
//! the DMA to read ui8FixDMALength between to pointer refreshes.
//!
//! \return None
//!
//! \sa \ref I2SStop()
//
//*****************************************************************************
__STATIC_INLINE void I2SStart(uint32_t ui32Base, uint8_t ui8FixDMALength)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Enable the I2S module.
HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = ui8FixDMALength;
}
//*****************************************************************************
//
//! \brief Stops the I2S module for operation.
//!
//! This function will immediately disable the I2S module. To ensure that
//! all buffer operations are completed before shutting down, the correct
//! procedure is:
//! 1. Do not update the data pointers using \ref I2SInPointerSet() and
//! \ref I2SOutPointerSet().
//! 2. Await that values returned by \ref I2SInPointerNextGet(),
//! \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and \ref I2SOutPointerGet()
//! are zero.
//! 3. Disable the I2S using \ref I2SStop() and clear the pointer
//! error using \ref I2SIntClear().
//! 4. Disable bit clock source (done externally).
//!
//! \param ui32Base is the I2S module base address.
//!
//! \return None
//!
//! \sa \ref I2SStart()
//
//*****************************************************************************
__STATIC_INLINE void I2SStop(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Disable the I2S module.
HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x00;
}
//*****************************************************************************
//
//! \brief Configure the serial format of the I2S module.
//!
//! The word length defines the size of the word transmitted on the data
//! lines. For single phased formats \c ui8BitsPerSample is the exact number
//! of bits per word. In dual phased format this is the maximum number of bits
//! per word.
//!
//! \param ui32Base is the I2S module base address.
//! \param ui8iDataDelay is the number of BCLK periods between the first WCLK
//! edge and the MSB of the first audio channel data transferred during
//! the phase.
//! \param ui8iMemory24Bits selects if the samples in memory are coded on 16 bits
//! or 24 bits. Possible values are:
//! - \ref I2S_MEM_LENGTH_16
//! - \ref I2S_MEM_LENGTH_24
//! \param ui8iSamplingEdge selects if sampling on falling or rising edges.
//! Possible values are:
//! - \ref I2S_NEG_EDGE
//! - \ref I2S_POS_EDGE
//! \param boolDualPhase must be set to true for dual phase and to false for
//! single phase and user-defined phase.
//! \param ui8BitsPerSample is the number of bits transmitted for each sample.
//! If this number does not match with the memory length selected
//! (16 bits or24 bits), samples will be truncated or padded.
//! \param ui16transmissionDelay is the number of WCLK periods before the first
//! transmission.
//!
//! \return None
//!
//! \sa \ref I2SFrameConfigure()
//
//*****************************************************************************
__STATIC_INLINE void
I2SFormatConfigure(uint32_t ui32Base,
uint8_t ui8iDataDelay,
uint8_t ui8iMemory24Bits,
uint8_t ui8iSamplingEdge,
bool boolDualPhase,
uint8_t ui8BitsPerSample,
uint16_t ui16transmissionDelay)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
ASSERT(ui8BitsPerSample <= I2S_AIFFMTCFG_WORD_LEN_MAX);
ASSERT(ui8BitsPerSample >= I2S_AIFFMTCFG_WORD_LEN_MIN);
// Setup register AIFFMTCFG Source.
HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) =
(ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) |
(ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) |
(ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) |
(boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) |
(ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S );
// Number of WCLK periods before the first read / write
HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay;
}
//****************************************************************************
//
//! \brief Setup the two interfaces SD0 and SD1 (also called AD0 and AD1).
//!
//! This function sets interface's direction and activated channels.
//!
//! \param ui32Base is base address of the I2S module.
//! \param ui8StatusAD0 defines the usage of AD0
//! 0x00: AD0 is disabled
//! 0x01, AD0 is an input
//! 0x02, AD0 is an output
//! \param ui8ChanAD0 defines the channel mask for AD0.
//! Use a bitwise OR'ed combination of:
//! - \ref I2S_CHAN0_MASK
//! - \ref I2S_CHAN1_MASK
//! - \ref I2S_CHAN2_MASK
//! - \ref I2S_CHAN3_MASK
//! - \ref I2S_CHAN4_MASK
//! - \ref I2S_CHAN5_MASK
//! - \ref I2S_CHAN6_MASK
//! - \ref I2S_CHAN7_MASK
//! \param ui8StatusAD1 defines the usage of AD1
//! 0x00: AD1 is disabled
//! 0x10, AD1 is an input
//! 0x20, AD1 is an output
//! \param ui8ChanAD1 defines the channel mask for AD1.
//! Use a bitwise OR'ed combination of:
//! - \ref I2S_CHAN0_MASK
//! - \ref I2S_CHAN1_MASK
//! - \ref I2S_CHAN2_MASK
//! - \ref I2S_CHAN3_MASK
//! - \ref I2S_CHAN4_MASK
//! - \ref I2S_CHAN5_MASK
//! - \ref I2S_CHAN6_MASK
//! - \ref I2S_CHAN7_MASK
//!
//! \return None
//!
//! \sa \ref I2SFormatConfigure()
//
//****************************************************************************
__STATIC_INLINE void
I2SFrameConfigure(uint32_t ui32Base,
uint8_t ui8StatusAD0, uint8_t ui8ChanAD0,
uint8_t ui8StatusAD1, uint8_t ui8ChanAD1)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Configure input/output channels.
HWREGB(I2S0_BASE + I2S_O_AIFDIRCFG) = (ui8StatusAD0 | ui8StatusAD1);
// Configure the valid channel mask.
HWREGB(I2S0_BASE + I2S_O_AIFWMASK0) = ui8ChanAD0;
HWREGB(I2S0_BASE + I2S_O_AIFWMASK1) = ui8ChanAD1;
}
//****************************************************************************
//
//! \brief Configure the I2S frame clock (also called WCLK or WS).
//!
//! Configure WCLK clock to be either internal (master) or external (slave).
//! Configure WCLK clock either normal or inverted.
//!
//! \note The bit clock configuration is done externally, but the internal/
//! external setting must match what is chosen internally in the I2S module
//! for the frame clock.
//!
//! \param ui32Base is the base address of the I2S module.
//! \param boolMaster false: the device is a slave (external clock)
//! true: the device is a master (internal clock)
//! \param boolWCLKInvert false: WCLK is not inverted
//! true: WCLK is internally inverted
//!
//! \return None
//
//****************************************************************************
__STATIC_INLINE void
I2SWclkConfigure(uint32_t ui32Base,
bool boolMaster,
bool boolWCLKInvert)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
ASSERT(ui8ClkSource < I2S_AIFWCLKSRC_WCLK_SRC_RESERVED);
// if(boolMaster == 0) then ui8ClkSource = 1
// if(boolMaster == 1) then ui8ClkSource = 2
uint8_t ui8ClkSource = (uint8_t)boolMaster + 0x01;
// Setup register WCLK Source.
HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) =
((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) |
(boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S ));
}
//****************************************************************************
//
//! \brief Set the input buffer pointer.
//!
//! The next pointer should always be written while the DMA is using the
//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR
//! will occur and all inputs and outputs will be disabled.
//! This function relies on pointer is pointing to a valid address.
//!
//! \note It is recommended that the pointer update is done in an interrupt context
//! to ensure that the update is performed before the buffer is full.
//!
//! \param ui32Base is the base address of the I2S module.
//! \param ui32NextPointer is the adress of the data
//!
//! \return None
//!
//! \sa \ref I2SOutPointerSet()
//
//****************************************************************************
__STATIC_INLINE void
I2SInPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = ui32NextPointer;
}
//****************************************************************************
//
//! \brief Set the output buffer pointer.
//!
//! The next pointer should always be written while the DMA is using the
//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR
//! will occur and all inputs and outputs will be disabled.
//! This function relies on pointer is pointing to a valid address.
//!
//! \note It is recommended that the pointer update is done in an interrupt context
//! to ensure that the update is performed before the buffer is full.
//!
//! \param ui32Base is the base address of the I2S module.
//! \param ui32NextPointer is the adress of the data
//!
//! \return None
//!
//! \sa \ref I2SInPointerSet()
//
//****************************************************************************
__STATIC_INLINE void
I2SOutPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = ui32NextPointer;
}
//****************************************************************************
//
//! \brief Get value stored in PTR NEXT IN register
//!
//! \param ui32Base is the base address of the I2S module.
//!
//! \return the value of PTR NEXT IN.
//
//****************************************************************************
__STATIC_INLINE uint32_t
I2SInPointerNextGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT));
}
//****************************************************************************
//
//! \brief Get value stored in PTR NEXT OUT register
//!
//! \param ui32Base is the base address of the I2S module.
//!
//! \return the value of PTR NEXT OUT.
//
//****************************************************************************
__STATIC_INLINE uint32_t
I2SOutPointerNextGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT));
}
//****************************************************************************
//
//! \brief Get value stored in PTR IN register
//!
//! \param ui32Base is the base address of the I2S module.
//!
//! \return the value of PTR IN.
//
//****************************************************************************
__STATIC_INLINE uint32_t
I2SInPointerGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
return (HWREG(I2S0_BASE + I2S_O_AIFINPTR));
}
//****************************************************************************
//
//! \brief Get value stored in PTR OUT register
//!
//! \param ui32Base is the base address of the I2S module.
//!
//! \return the value of PTR OUT.
//
//****************************************************************************
__STATIC_INLINE uint32_t
I2SOutPointerGet(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTR));
}
//*****************************************************************************
//
//! \brief Configure the IN sample stamp generator.
//!
//! Use this function to configure the sample stamp generator.
//!
//! \param ui32Base is the base address of the I2S module.
//! \param ui16TrigValue value used to set the trigger.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2SSampleStampInConfigure(uint32_t ui32Base, uint16_t ui16TrigValue)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Setup the sample stamp trigger for input streams.
HWREGH(I2S0_BASE + I2S_O_STMPINTRIG) = ui16TrigValue;
}
//*****************************************************************************
//
//! \brief Configure the OUT sample stamp generator.
//!
//! Use this function to configure the sample stamp generator.
//!
//! \param ui32Base is the base address of the I2S module.
//! \param ui16TrigValue value used to set the trigger.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2SSampleStampOutConfigure(uint32_t ui32Base, uint16_t ui16TrigValue)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
// Setup the sample stamp trigger for output streams.
HWREGH(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui16TrigValue;
}
//*****************************************************************************
//
//! \brief Add the specified value to the WCLK count.
//!
//! \param ui32Base is the base address of the I2S module.
//! \param i16Value is the offset to add to the counter (this value can be negative)
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2SWclkCounterConfigure(uint32_t ui32Base, int16_t i16Value)
{
uint16_t ui16MinusValue;
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
if (i16Value >= 0)
{
HWREGH(I2S0_BASE + I2S_O_STMPWADD) = i16Value;
}
else
{
ui16MinusValue = (uint16_t)(-i16Value);
HWREGH(I2S0_BASE + I2S_O_STMPWADD) = HWREGH(I2S0_BASE + I2S_O_STMPWPER) - ui16MinusValue;
}
}
//*****************************************************************************
//
//! \brief Reset the WCLK count.
//!
//! \param ui32Base is the base address of the I2S module.
//!
//! \return None
//
//*****************************************************************************
__STATIC_INLINE void
I2SWclkCounterReset(uint32_t ui32Base)
{
// Check the arguments.
ASSERT(I2SBaseValid(ui32Base));
HWREGH(I2S0_BASE + I2S_O_STMPWSET) = 0;
}
//*****************************************************************************
//
// Support for DriverLib in ROM:
third_party/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h
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+141
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@@ -0,0 +1,141 @@
/******************************************************************************
* Filename: i2s_doc.h
* Revised: $$
* Revision: $$
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
//! \addtogroup i2s_api
//! @{
//! \section sec_i2s Introduction
//!
//! The I2S API provides a set of functions for using the I2S module.
//! This module provides a standardized serial interface to transfer
//! audio samples from and to external audio devices such as a codec,
//! DAC, or ADC.
//!
//! The I2S module has the following features:
//! - Audio clock signals are internally generated by the PRCM module
//! or externally by another device.
//! - One or two data pins, which can be configured independently as
//! input or output
//! - Various data formats according to the settings of the module
//! - Up to two channels per data pin for dual phase formats and up
//! to eight channels per data pin for single phase formats
//! - DMA with double-buffered pointers
//! - Error detection for DMA and audio clock signal integrity
//! - A Samplestamp generator that allows maintaining of constant
//! audio latency
//!
//! The I2S module is configured through the functions \ref I2SFormatConfigure(),
//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure().
//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using
//! \ref I2SStop(). Please note that a specific procedure exists in order
//! to disable transfers without losing data (refer to \ref I2SStop()).
//!
//! Data are transmitted using the two double-buffered pointers.
//! For each interface, two registers are set with the address of the data to
//! transfer. These registers are named INPTR and INPTRNEXT for the input
//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed,
//! the hardware copies the content of PTRNEXT into PTR and the next transfer
//! begins.
//! The address of the next value to write or to read in memory (i.e. to receive
//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet().
//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using
//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and
//! \ref I2SOutPointerGet() functions.
//!
//! Interrupts can help the user to refresh pointers on time. Interrupts can also
//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable()
//! activate and deactivate interrupt(s). Interrupt status can be read through
//! \ref I2SIntStatus() and a pending interrupt can be acquitted by
//! \ref I2SIntClear() function.
//!
//! The sample stamps generator can be configured to slightly delay the
//! emission or the reception of the data (based on the number of WCLK
//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(),
//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp
//! can be computed using \ref I2SSampleStampGet().
//! To finish, the sample stamps generator can be enable and disable using
//! the following functions: \ref I2SSampleStampEnable() and
//! \ref I2SSampleStampDisable().
//! The sample stamps generator must be enabled prior to any transfer.
//!
//! Note: Other functions contained in the PRCM API are required to handle I2S.
//!
//! \section sec_i2s_api API
//!
//! Two APIs are coexisting.
//! It is recommended to only use the new API as the old one is deprecated and
//! will be removed soon.
//!
//! New API:
//! Functions to perform I2S configuration:
//! - \ref I2SStart()
//! - \ref I2SStop()
//! - \ref I2SFormatConfigure()
//! - \ref I2SFrameConfigure()
//! - \ref I2SWclkConfigure()
//!
//! Functions to perform transfers:
//! - \ref I2SInPointerSet()
//! - \ref I2SOutPointerSet()
//! - \ref I2SInPointerGet()
//! - \ref I2SOutPointerGet()
//! - \ref I2SInPointerNextGet()
//! - \ref I2SOutPointerNextGet()
//!
//! Functions to handle interruptions:
//! - \ref I2SIntEnable()
//! - \ref I2SIntDisable()
//! - \ref I2SIntStatus()
//! - \ref I2SIntClear()
//!
//! Functions to handle sample stamps
//! - \ref I2SSampleStampEnable()
//! - \ref I2SSampleStampDisable()
//! - \ref I2SSampleStampInConfigure()
//! - \ref I2SSampleStampOutConfigure()
//! - \ref I2SSampleStampGet()
//! - \ref I2SWclkCounterConfigure()
//! - \ref I2SWclkCounterReset()
//!
//! Old API:
//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(),
//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(),
//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(),
//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(),
//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(),
//! \ref I2SPointerSet (), \ref I2SPointerUpdate(),
//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(),
//! \ref I2SIntUnregister()
//!
//! @}
third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.c
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+186 -13
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@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: osc.c
* Revised: 2017-09-01 10:21:01 +0200 (Fri, 01 Sep 2017)
* Revision: 49677
* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019)
* Revision: 54539
*
* Description: Driver for setting up the system Oscillators
*
@@ -67,14 +67,32 @@
#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude
#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude
#define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
#undef OSC_HPOSC_Debug_InitFreqOffsetParams
#define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams
#undef OSC_HPOSCInitializeFrequencyOffsetParameters
#define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters
#undef OSC_HPOSCRelativeFrequencyOffsetGet
#define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet
#undef OSC_AdjustXoscHfCapArray
#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray
#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#undef OSC_HPOSCRtcCompensate
#define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate
#endif
//*****************************************************************************
//
// Global HPOSC curve fitting polynomials
// Parameters found/calculated when calling function
// OSC_HPOSCInitializeFrequencyOffsetParameters()
// (or OSC_HPOSC_Debug_InitFreqOffsetParams() used for debugging only)
// These global variables must be updated before using HPOSC
//
//*****************************************************************************
static int16_t _hpOscPolynomials[ 4 ];
//*****************************************************************************
//
// OSCHF switch time calculator defines and globals
@@ -311,6 +329,132 @@ OSC_AdjustXoscHfCapArray( int32_t capArrDelta )
DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ));
}
//*****************************************************************************
//
// Initialize the frequency offset curve fitting parameters
// These are either picked diretly from FCFG1:FREQ_OFFSET & FCFG1:MISC_CONF_2 or
// calculated based on the FCFG1:HPOSC_MEAS_x parameters.
//
//*****************************************************************************
// Using the following hardcoded constants (Using temporary constants for now)
#define D1OFFSET_p25C -24
#define D2OFFSET_p85C -36
#define D3OFFSET_m40C 18
#define P3_POLYNOMIAL -47
#define N_INSERTIONS 3
typedef struct {
int32_t dFreq ;
int32_t temp ;
} insertion_t ;
static void
InitializeMeasurmentSet( insertion_t * pInsertion, uint32_t registerAddress, int32_t deltaOffset, int32_t p3PolOffset )
{
// Doing the following adjustment to the deltaFrequence before finding the polynomials P0, P1, P2
// Dx = Dx + DxOFFSET - ((P3*Tx^3)/2^18)
uint32_t insertionData = HWREG( registerAddress );
pInsertion->dFreq = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W - FCFG1_HPOSC_MEAS_1_HPOSC_D1_S )))
>> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W ));
pInsertion->temp = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W - FCFG1_HPOSC_MEAS_1_HPOSC_T1_S )))
>> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W ));
pInsertion->dFreq = pInsertion->dFreq + deltaOffset - (( p3PolOffset * pInsertion->temp * pInsertion->temp * pInsertion->temp ) >> 18 );
}
static void
FindPolynomialsAndUpdateGlobals( insertion_t * pMeasurment )
{
uint32_t loopCount ;
int32_t polynomial_0 ;
int32_t polynomial_1 ;
int32_t polynomial_2 ;
int32_t Syi_ = 0 ;
int32_t Sxi_ = 0 ;
int32_t Sxi2_ = 0 ;
int32_t Sxiyi_ = 0 ;
int32_t Sxi2yi_ = 0 ;
int32_t Sxi3_ = 0 ;
int32_t Sxi4_ = 0 ;
for ( loopCount = 0 ; loopCount < N_INSERTIONS ; loopCount++ ) {
int32_t x ;
int32_t x2 ;
int32_t y ;
x = pMeasurment[ loopCount ].temp ;
x2 = ( x * x );
y = pMeasurment[ loopCount ].dFreq ;
Syi_ += ( y );
Sxi_ += ( x );
Sxi2_ += ( x2 );
Sxiyi_ += ( x * y );
Sxi2yi_ += ( x2 * y );
Sxi3_ += ( x2 * x );
Sxi4_ += ( x2 * x2 );
}
int32_t Sxx_ = ( Sxi2_ * N_INSERTIONS ) - ( Sxi_ * Sxi_ );
int32_t Sxy_ = ( Sxiyi_ * N_INSERTIONS ) - ( Sxi_ * Syi_ );
int32_t Sxx2_ = ( Sxi3_ * N_INSERTIONS ) - ( Sxi_ * Sxi2_ );
int32_t Sx2y_ = ( Sxi2yi_ * N_INSERTIONS ) - ( Sxi2_ * Syi_ );
int32_t Sx2x2_ = ( Sxi4_ * N_INSERTIONS ) - ( Sxi2_ * Sxi2_ );
int32_t divisor = ((((int64_t) Sxx_ * Sx2x2_ ) - ((int64_t) Sxx2_ * Sxx2_ )) + (1<<9)) >> 10 ;
if ( divisor == 0 ) {
polynomial_2 = 0 ;
polynomial_1 = 0 ;
} else {
polynomial_2 = (((int64_t) Sx2y_ * Sxx_ ) - ((int64_t) Sxy_ * Sxx2_ )) / divisor ;
polynomial_1 = (((int64_t) Sxy_ * Sx2x2_ ) - ((int64_t) Sx2y_ * Sxx2_ )) / divisor ;
}
polynomial_0 = ( Syi_ - (((( polynomial_1 * Sxi_ ) + ( polynomial_2 * Sxi2_ )) + (1<<9)) >> 10 )) / N_INSERTIONS ;
polynomial_1 = ( polynomial_1 + (1<<6)) >> 7 ;
_hpOscPolynomials[ 0 ] = polynomial_0 ;
_hpOscPolynomials[ 1 ] = polynomial_1 ;
_hpOscPolynomials[ 2 ] = polynomial_2 ;
_hpOscPolynomials[ 3 ] = P3_POLYNOMIAL ;
}
//*****************************************************************************
// Degub function to calculate the HPOSC polynomials for experimental data sets.
//*****************************************************************************
void
OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData )
{
// Calculate the curve fitting parameters from temp insertion measurements
// But first adjust the measurements with constants found in characterization
insertion_t pMeasurment[ 3 ];
InitializeMeasurmentSet( &pMeasurment[ 0 ], (uint32_t)&pDebugData->meas_1, pDebugData->offsetD1, pDebugData->polyP3 );
InitializeMeasurmentSet( &pMeasurment[ 1 ], (uint32_t)&pDebugData->meas_2, pDebugData->offsetD2, pDebugData->polyP3 );
InitializeMeasurmentSet( &pMeasurment[ 2 ], (uint32_t)&pDebugData->meas_3, pDebugData->offsetD3, pDebugData->polyP3 );
FindPolynomialsAndUpdateGlobals( pMeasurment );
}
//*****************************************************************************
// The general HPOSC initialization function - Must always be called before using HPOSC
//*****************************************************************************
void
OSC_HPOSCInitializeFrequencyOffsetParameters( void )
{
{
// Calculate the curve fitting parameters from temp insertion measurements
// But first adjust the measurements with constants found in characterization
insertion_t pMeasurment[ 3 ];
InitializeMeasurmentSet( &pMeasurment[ 0 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_1, D1OFFSET_p25C, P3_POLYNOMIAL );
InitializeMeasurmentSet( &pMeasurment[ 1 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_2, D2OFFSET_p85C, P3_POLYNOMIAL );
InitializeMeasurmentSet( &pMeasurment[ 2 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_3, D3OFFSET_m40C, P3_POLYNOMIAL );
FindPolynomialsAndUpdateGlobals( pMeasurment );
}
}
//*****************************************************************************
//
// Calculate the temperature dependent relative frequency offset of HPOSC
@@ -320,17 +464,11 @@ int32_t
OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC )
{
// Estimate HPOSC frequency, using temperature and curve fitting parameters
uint32_t fitParams = HWREG(FCFG1_BASE + FCFG1_O_FREQ_OFFSET);
// Extract the P0,P1,P2 params, and sign extend them via shifting up/down
int32_t paramP0 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S))
>> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W));
int32_t paramP1 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S))
>> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W));
int32_t paramP2 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S))
>> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W));
int32_t paramP3 = ((((int32_t) HWREG(FCFG1_BASE + FCFG1_O_MISC_CONF_2))
<< (32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S))
>> (32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W));
int32_t paramP0 = _hpOscPolynomials[ 0 ];
int32_t paramP1 = _hpOscPolynomials[ 1 ];
int32_t paramP2 = _hpOscPolynomials[ 2 ];
int32_t paramP3 = _hpOscPolynomials[ 3 ];
// Now we can find the HPOSC freq offset, given as a signed variable d, expressed by:
//
@@ -395,6 +533,41 @@ OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffs
return ( rfCoreFreqOffset );
}
//*****************************************************************************
//
// Compensate the RTC increment based on the relative frequency offset of HPOSC
//
//*****************************************************************************
void
OSC_HPOSCRtcCompensate( int32_t relFreqOffset )
{
uint32_t rtcSubSecInc;
uint32_t lfClkFrequency;
uint32_t hfFreq;
int64_t calcFactor;
// Calculate SCLK_HF frequency, defined as:
// hfFreq = 48000000 * (1 + relFreqOffset/(2^22))
if( relFreqOffset >= 0 )
{
calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) + 0x200000 ) / 0x400000;
}
else
{
calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) - 0x200000 ) / 0x400000;
}
hfFreq = 48000000 + calcFactor;
// Calculate SCLK_LF frequency, defined as SCLK_LF_FREQ = SCLK_HF_FREQ / 1536
lfClkFrequency = ( hfFreq + 768 ) / 1536;
// Calculate SUBSECINC, defined as: SUBSECINC = 2^38 / SCLK_LF_FREQ
rtcSubSecInc = 0x4000000000 / lfClkFrequency;
/* Update SUBSECINC value */
SetupSetAonRtcSubSecInc(rtcSubSecInc);
}
//*****************************************************************************
//
// Get crystal amplitude (assuming crystal is running).
third_party/ti/devices/cc13x2_cc26x2/driverlib/osc.h
Vendored
+181 -6
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@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: osc.h
* Revised: 2018-04-18 15:47:09 +0200 (Wed, 18 Apr 2018)
* Revision: 51907
* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019)
* Revision: 54539
*
* Description: Defines and prototypes for the system oscillator control.
*
@@ -62,6 +62,8 @@ extern "C"
#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_aon_pmctl.h"
#include "../inc/hw_ccfg.h"
#include "../inc/hw_fcfg1.h"
#include "../inc/hw_types.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_ddi.h"
@@ -92,9 +94,12 @@ extern "C"
#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc
#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude
#define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
#define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams
#define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters
#define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet
#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray
#define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate
#endif
//*****************************************************************************
@@ -208,9 +213,9 @@ OSCClockLossEventDisable( void )
//! Use this function to set the oscillator source for one or more of the
//! system source clocks.
//!
//! When selecting the high frequency clock source, this function will not do
//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do
//! the actual switch. Enabling the high frequency XTAL can take several hundred
//! micro seconds, so the actual switch is split into a separate function,
//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(),
//! leaving System CPU free to perform other tasks as the XTAL starts up.
//!
//! \note The High Frequency (\ref OSC_SRC_CLK_HF) can only be derived from the
@@ -232,7 +237,7 @@ OSCClockLossEventDisable( void )
//! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF)
//! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF)
//!
//! \sa OSCClockSourceGet()
//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch()
//!
//! \return None
//
@@ -292,7 +297,7 @@ OSCHfSourceReady(void)
//!
//! When switching the HF clock source the clock period might be prolonged
//! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that
//! this does not coincide with a read access to the Flash potentially
//! this does not coincide with a read access to the Flash, potentially
//! freezing the device, the HF clock source switch must be executed from ROM.
//!
//! \note This function will not return until the clock source has been
@@ -307,8 +312,82 @@ OSCHfSourceReady(void)
__STATIC_INLINE void
OSCHfSourceSwitch(void)
{
// Read target clock (lower half of the 32-bit CTL0 register)
uint16_t hfSrc = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0) & DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M;
// If target clock source is RCOSC, change clock source for DCDC to RCOSC
if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC)
{
// Force DCDC to use RCOSC before switching SCLK_HF to RCOSC
HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16);
// Dummy read to ensure that the write has propagated
HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
}
// Switch the HF clock source
HapiHFSourceSafeSwitch();
// If target clock source is XOSC, change clock source for DCDC to "auto"
if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC)
{
// Set DCDC clock source back to "auto" after SCLK_HF was switched to XOSC
HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M;
}
}
//*****************************************************************************
//
//! \brief Identifies if HPOSC is enabled.
//!
//! This function checks if the device supports HPOSC and that HPOSC is selected
//! as HF oscillator for use when the radio is active.
//!
//! \return Returns status of HPOSC functionality:
//! - \c true : HPOSC is enabled.
//! - \c false : HPOSC is not enabled.
//
//*****************************************************************************
__STATIC_INLINE bool
OSC_IsHPOSCEnabled(void)
{
bool enabled = false;
if((( HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) &&
(( HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0))
{
enabled = true;
}
return (enabled);
}
//*****************************************************************************
//
//! \brief Identifies if HPOSC is enabled and that SCLK_LF is derived from XOSC_HF.
//!
//! This function checks if the device supports HPOSC and that HPOSC is selected
//! as HF oscillator for use when the radio is active and also that SCLK_LF is
//! derived from XOSC_HF.
//!
//! \return Returns status of HPOSC and SCLK_LF configuration:
//! - \c true : HPOSC is enabled and SCLK_LF is derived from XOSC_HF.
//! - \c false : Either HPOSC not enabled or SCLK_LF is not derived from XOSC_HF.
//
//*****************************************************************************
__STATIC_INLINE bool
OSC_IsHPOSCEnabledWithHfDerivedLfClock(void)
{
bool enabled = false;
// Check configuration by reading lower half of the 32-bit CTL0 register
uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
if( ( ( regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M ) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF ) &&
( ( regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M ) == DDI_0_OSC_CTL0_HPOSC_MODE_EN ) )
{
enabled = true;
}
return (enabled);
}
//*****************************************************************************
@@ -402,6 +481,53 @@ extern uint32_t OSCHF_DebugGetCrystalAmplitude( void );
//*****************************************************************************
extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void );
//*****************************************************************************
//
//! \brief Data structure for experimental HPOSC polynomials calculation.
//!
//! The structure of the meas_1, meas_2 and meas_3 parameter is
//! as defined in FCFG1_O_HPOSC_MEAS_1, 2 and 3.
//!
//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams()
//
//*****************************************************************************
typedef struct {
uint32_t meas_1 ; //!< Measurement set 1 (typically at room temp)
uint32_t meas_2 ; //!< Measurement set 2 (typically at high temp)
uint32_t meas_3 ; //!< Measurement set 3 (typically at low temp)
int32_t offsetD1 ; //!< Offset to measurement set 1
int32_t offsetD2 ; //!< Offset to measurement set 2
int32_t offsetD3 ; //!< Offset to measurement set 3
int32_t polyP3 ; //!< The P3 polynomial
} HposcDebugData_t;
//*****************************************************************************
//
//! \brief Debug function to calculate the HPOSC polynomials for experimental data sets.
//!
//! \param pDebugData pointer to the input data collected in \ref HposcDebugData_t
//!
//! \return None
//!
//! \sa OSC_HPOSCInitializeFrequencyOffsetParameters()
//
//*****************************************************************************
extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData );
//*****************************************************************************
//
//! \brief HPOSC initialization function. Must always be called before using HPOSC.
//!
//! Calculates the fitting curve parameters (polynomials) to used by the
//! HPOSC temperature compensation.
//!
//! \return None
//!
//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams()
//
//*****************************************************************************
extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void );
//*****************************************************************************
//
//! \brief Calculate the temperature dependent relative frequency offset of HPOSC
@@ -481,6 +607,43 @@ extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta );
//*****************************************************************************
extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset );
//*****************************************************************************
//
//! \brief Compensate the RTC increment based on the relative frequency offset of HPOSC
//!
//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature.
//! This variation forces the RTC increment to be compensated if SCLK_LF is configured
//! to be derived from the HF clock of HPOSC.
//! This function must only be called if SCLK_LF is configured to be derived from
//! the HF clock of HPOSC. The status of this configuration can be determined
//! by calling the \ref OSC_IsHPOSCEnabledWithHfDerivedLfClock() function.
//!
//! This function first calculates the HPOSC frequency, defined as:
//! <pre>
//! F_HPOSC = F_nom * (1 + d/(2^22))
//! </pre>
//! where
//! - F_HPOSC is the current HPOSC frequency.
//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz.
//! - d is the relative frequency offset given by the input argument relFreqOffset.
//! Then the SCLK_LF frequency is calculated, defined as:
//! <pre>
//! F_SCLK_LF = F_HPOSC / 1536
//! </pre>
//! Then the RTC increment SUBSECINC is calculated, defined as;
//! <pre>
//! SUBSECINC = (2^38) / F_SCLK_LF
//! </pre>
//! Finally the RTC module is updated with the calculated SUBSECINC value.
//!
//! \param relFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet()
//!
//! \return None
//!
//
//*****************************************************************************
extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset );
//*****************************************************************************
//
// Support for DriverLib in ROM:
@@ -521,6 +684,14 @@ extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HP
#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude
#define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
#endif
#ifdef ROM_OSC_HPOSC_Debug_InitFreqOffsetParams
#undef OSC_HPOSC_Debug_InitFreqOffsetParams
#define OSC_HPOSC_Debug_InitFreqOffsetParams ROM_OSC_HPOSC_Debug_InitFreqOffsetParams
#endif
#ifdef ROM_OSC_HPOSCInitializeFrequencyOffsetParameters
#undef OSC_HPOSCInitializeFrequencyOffsetParameters
#define OSC_HPOSCInitializeFrequencyOffsetParameters ROM_OSC_HPOSCInitializeFrequencyOffsetParameters
#endif
#ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet
#undef OSC_HPOSCRelativeFrequencyOffsetGet
#define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet
@@ -533,6 +704,10 @@ extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HP
#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
#endif
#ifdef ROM_OSC_HPOSCRtcCompensate
#undef OSC_HPOSCRtcCompensate
#define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate
#endif
#endif
//*****************************************************************************
third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.c
Vendored
+29 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: pka.c
* Revised: 2018-05-08 10:58:47 +0200 (Tue, 08 May 2018)
* Revision: 51975
* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018)
* Revision: 52294
*
* Description: Driver for the PKA module
*
@@ -45,6 +45,8 @@
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef PKAClearPkaRam
#define PKAClearPkaRam NOROM_PKAClearPkaRam
#undef PKAGetOpsStatus
#define PKAGetOpsStatus NOROM_PKAGetOpsStatus
#undef PKAArrayAllZeros
@@ -102,6 +104,8 @@
//
//*****************************************************************************
#if !defined(DOXYGEN)
#undef PKAClearPkaRam
#define PKAClearPkaRam NOROM_PKAClearPkaRam
#undef PKAGetOpsStatus
#define PKAGetOpsStatus NOROM_PKAGetOpsStatus
#undef PKAArrayAllZeros
@@ -569,6 +573,29 @@ const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}};
//*****************************************************************************
//
// Zeroize PKA RAM. Not threadsafe.
//
//*****************************************************************************
void PKAClearPkaRam(void){
// Get initial state
uint32_t secdmaclkgr = HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR);
// OR in zeroize bit
secdmaclkgr |= PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N;
// Start zeroization
HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr;
// Wait 256 cycles for PKA RAM to be cleared
CPUdelay(256 / 4);
// Turn off zeroization
HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr & (~PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N);
}
//*****************************************************************************
//
// Write a PKA parameter to the PKA module, set required registers, and add an offset.
third_party/ti/devices/cc13x2_cc26x2/driverlib/pka.h
Vendored
+16 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: pka.h
* Revised: 2018-03-02 10:51:37 +0100 (Fri, 02 Mar 2018)
* Revision: 51635
* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018)
* Revision: 52294
*
* Description: PKA header file.
*
@@ -83,6 +83,7 @@ extern "C"
//
//*****************************************************************************
#if !defined(DOXYGEN)
#define PKAClearPkaRam NOROM_PKAClearPkaRam
#define PKAGetOpsStatus NOROM_PKAGetOpsStatus
#define PKAArrayAllZeros NOROM_PKAArrayAllZeros
#define PKAZeroOutArray NOROM_PKAZeroOutArray
@@ -603,6 +604,15 @@ extern const PKA_EccParam256 Curve25519_order;
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Zeroizes PKA RAM.
//!
//! This function uses the zeroization function in PRCM to clear the PKA RAM.
//
//*****************************************************************************
extern void PKAClearPkaRam(void);
//*****************************************************************************
//
//! \brief Gets the PKA operation status.
@@ -1323,6 +1333,10 @@ extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX
//*****************************************************************************
#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
#include "../driverlib/rom.h"
#ifdef ROM_PKAClearPkaRam
#undef PKAClearPkaRam
#define PKAClearPkaRam ROM_PKAClearPkaRam
#endif
#ifdef ROM_PKAGetOpsStatus
#undef PKAGetOpsStatus
#define PKAGetOpsStatus ROM_PKAGetOpsStatus
third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.c
Vendored
+64 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: prcm.c
* Revised: 2017-07-19 10:58:53 +0200 (Wed, 19 Jul 2017)
* Revision: 49363
* Revised: 2018-10-18 17:33:32 +0200 (Thu, 18 Oct 2018)
* Revision: 52954
*
* Description: Driver for the PRCM.
*
@@ -53,6 +53,10 @@
#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet
#undef PRCMAudioClockConfigSetOverride
#define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride
#undef PRCMAudioClockInternalSource
#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource
#undef PRCMAudioClockExternalSource
#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource
#undef PRCMPowerDomainOn
#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn
#undef PRCMPowerDomainOff
@@ -350,6 +354,64 @@ PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
}
//*****************************************************************************
//
// Configure the audio clocks for I2S module
//
//*****************************************************************************
void
PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge,
uint8_t ui8WCLKPhase,
uint32_t ui32MstDiv,
uint32_t ui32BitDiv,
uint32_t ui32WordDiv)
{
// Check the arguments.
ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE
|| ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE
|| ui8BitsPerSample == PRCM_WCLK_USER_DEF);
// Make sure the audio clock generation is disabled before reconfiguring.
PRCMAudioClockDisable();
// Make sure to compensate the Frame clock division factor if using single
// phase format.
if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE)
{
ui32WordDiv -= 1;
}
// Write the clock division factors.
HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
// Configure the Word clock format and polarity and enable it.
HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) |
(ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) |
(1 << PRCM_I2SCLKCTL_EN_S );
}
//*****************************************************************************
//
// Configure the clocks as "internally generated".
//
//*****************************************************************************
void PRCMAudioClockInternalSource(void)
{
HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1;
}
//*****************************************************************************
//
// Configure the clocks as "externally generated".
//
//*****************************************************************************
void PRCMAudioClockExternalSource(void)
{
HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0;
}
//*****************************************************************************
//
// Turn power on in power domains in the MCU domain
third_party/ti/devices/cc13x2_cc26x2/driverlib/prcm.h
Vendored
+80 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: prcm.h
* Revised: 2017-12-11 16:44:38 +0100 (Mon, 11 Dec 2017)
* Revision: 50602
* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018)
* Revision: 52979
*
* Description: Defines and prototypes for the PRCM
*
@@ -71,6 +71,7 @@ extern "C"
#include "debug.h"
#include "cpu.h"
//*****************************************************************************
//
// Support for DriverLib in ROM:
@@ -89,6 +90,8 @@ extern "C"
#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet
#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet
#define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride
#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource
#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource
#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn
#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff
#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable
@@ -169,6 +172,11 @@ extern "C"
#define PRCM_WCLK_SINGLE_PHASE 0x00000000
#define PRCM_WCLK_DUAL_PHASE 0x00000002
#define PRCM_WCLK_USER_DEF 0x00000004
#define PRCM_I2S_WCLK_NEG_EDGE 0
#define PRCM_I2S_WCLK_POS_EDGE 1
#define PRCM_I2S_WCLK_SINGLE_PHASE 0
#define PRCM_I2S_WCLK_DUAL_PHASE 1
#define PRCM_I2S_WCLK_USER_DEF 2
#define I2S_SAMPLE_RATE_16K 0x00000001
#define I2S_SAMPLE_RATE_24K 0x00000002
@@ -428,6 +436,8 @@ PRCMAudioClockDisable(void)
//
//! \brief Configure the audio clock generation.
//!
//! \deprecated This function will be removed in a future release.
//!
//! Use this function to set the sample rate when using internal audio clock
//! generation for the I2S module.
//!
@@ -455,13 +465,17 @@ PRCMAudioClockDisable(void)
//! \sa \ref PRCMAudioClockConfigSetOverride()
//
//*****************************************************************************
#ifndef DEPRECATED
extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig,
uint32_t ui32SampleRate);
#endif
//*****************************************************************************
//
//! \brief Configure the audio clock generation with manual setting of clock divider.
//!
//! \deprecated This function will be removed in a future release.
//!
//! Use this function to set the audio clock divider values manually.
//!
//! \note See hardware documentation before setting audio clock dividers manually.
@@ -483,8 +497,64 @@ extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig,
//! \sa \ref PRCMAudioClockConfigSet()
//
//*****************************************************************************
#ifndef DEPRECATED
extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
uint32_t ui32BitDiv, uint32_t ui32WordDiv);
#endif
//*****************************************************************************
//
//! \brief Configure the audio clocks for I2S module.
//!
//! \note See hardware documentation before setting audio clock dividers.
//! This is user's responsability to provide valid clock dividers.
//!
//! \param ui8SamplingEdge Define the clock polarity:
//! - \ref PRCM_I2S_WCLK_NEG_EDGE
//! - \ref PRCM_I2S_WCLK_POS_EDGE
//! \param ui8WCLKPhase Define I2S phase used
//! - PRCM_I2S_WCLK_SINGLE_PHASE
//! - PRCM_I2S_WCLK_DUAL_PHASE
//! - PRCM_I2S_WCLK_USER_DEF
//! \param ui32MstDiv is the desired master clock divider.
//! \param ui32BitDiv is the desired bit clock divider.
//! \param ui32WordDiv is the desired word clock divider.
//!
//! \return None
//!
//*****************************************************************************
extern void PRCMAudioClockConfigOverride
(uint8_t ui8SamplingEdge,
uint8_t ui8WCLKPhase,
uint32_t ui32MstDiv,
uint32_t ui32BitDiv,
uint32_t ui32WordDiv);
//*****************************************************************************
//
//! \brief Configure the audio clocks to be internally generated.
//!
//! Use this function to set the audio clocks as internal.
//!
//! \return None
//!
//! \sa \ref PRCMAudioClockExternalSource()
//
//*****************************************************************************
extern void PRCMAudioClockInternalSource(void);
//*****************************************************************************
//
//! \brief Configure the audio clocks to be externally generated.
//!
//! Use this function to set the audio clocks as external.
//!
//! \return None
//!
//! \sa \ref PRCMAudioClockInternalSource()
//
//*****************************************************************************
extern void PRCMAudioClockExternalSource(void);
//*****************************************************************************
//
@@ -1094,6 +1164,14 @@ PRCMCacheRetentionDisable( void )
#undef PRCMAudioClockConfigSetOverride
#define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride
#endif
#ifdef ROM_PRCMAudioClockInternalSource
#undef PRCMAudioClockInternalSource
#define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource
#endif
#ifdef ROM_PRCMAudioClockExternalSource
#undef PRCMAudioClockExternalSource
#define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource
#endif
#ifdef ROM_PRCMPowerDomainOn
#undef PRCMPowerDomainOn
#define PRCMPowerDomainOn ROM_PRCMPowerDomainOn
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h
Vendored
+93 -71
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_ble_cmd.h
* Revised: 2018-05-07 15:02:01 +0200 (Mon, 07 May 2018)
* Revision: 18438
* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018)
* Revision: 18572
*
* Description: CC13x2/CC26x2 API for Bluetooth Low Energy commands
*
@@ -203,9 +203,8 @@ struct __RFC_STRUCT rfc_ble5RadioOp_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
uint8_t* pParams; //!< Pointer to command specific parameter structure
uint8_t* pOutput; //!< Pointer to command specific output structure
} __RFC_STRUCT_ATTR;
@@ -258,12 +257,11 @@ struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
uint8_t* pParams; //!< Pointer to command specific parameter structure
uint8_t* pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -812,12 +810,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_ble5SlavePar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -875,12 +872,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_ble5MasterPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -938,12 +934,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_ble5AdvExtPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1001,12 +996,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_ble5AdvAuxPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1064,12 +1058,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_ble5ScannerPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1127,12 +1120,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_ble5InitiatorPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1190,12 +1182,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1253,12 +1244,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1316,12 +1306,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1379,12 +1368,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1442,12 +1430,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1505,12 +1492,11 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s {
uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
//!< 0x0000: Use default TX power<br>
//!< 0xFFFF: Use field <code>tx20Power</code> to set power for 20-dBm PA or to switch PA
//!< (command structure that includes <code>tx20Power</code> must be used; patch
//!< required)
//!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
//!< structure that includes <code>tx20Power</code> must be used)
rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF (patch required):<br>
uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
//!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
//!< overrides the one given in radio setup for the duration of the command. <br>
//!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
@@ -1760,9 +1746,9 @@ struct __RFC_STRUCT rfc_bleAdvPar_s {
uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
//!< 1: Discard messages with illegal length for the given packet type
uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2<br>
//!< 1: Report support of Channel Selection Algorithm #2 (patch required)
uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used (if patch is used)
//!< 1: Filter on bPrivIgn always (patch required)
//!< 1: Report support of Channel Selection Algorithm #2
uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used
//!< 1: Filter on bPrivIgn always
uint8_t rpaMode:1; //!< \brief Resolvable private address mode<br>
//!< 0: Normal operation<br>
//!< 1: Use white list for a received RPA regardless of filter policy
@@ -1777,7 +1763,12 @@ struct __RFC_STRUCT rfc_bleAdvPar_s {
rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed
//!< advertiser). If least significant bit is 1, the address type given by
//!< <code>advConfig.peerAddrType</code> is inverted.
uint16_t __dummy0;
struct {
uint8_t scanRspEndType:1; //!< \brief Command status at end if SCAN_RSP was sent:<br>
//!< 0: End with BLE_DONE_OK and result True<br>
//!< 1: End with BLE_DONE_SCAN_RSP and result False
} behConfig;
uint8_t __dummy0;
uint8_t __dummy1;
struct {
uint8_t triggerType:4; //!< The type of trigger
@@ -1897,7 +1888,7 @@ struct __RFC_STRUCT rfc_bleInitiatorPar_s {
uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
//!< 1: Discard messages with illegal length for the given packet type
uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2<br>
//!< 1: Report support of Channel Selection Algorithm #2 (patch required)
//!< 1: Report support of Channel Selection Algorithm #2
} initConfig;
uint8_t __dummy0;
uint8_t connectReqLen; //!< Size of connect request data
@@ -2171,13 +2162,17 @@ struct __RFC_STRUCT rfc_ble5AdvAuxPar_s {
//!< 1: Discard messages with illegal length for the given packet type
uint8_t bDirected:1; //!< \brief 0: Advertiser is undirected: pWhiteList points to a white list
//!< 1: Advertiser is directed: pWhiteList points to a single device address
uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used (if patch is used)
//!< 1: Filter on bPrivIgn always (patch required)
uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used
//!< 1: Filter on bPrivIgn always
uint8_t rpaMode:1; //!< \brief Resolvable private address mode<br>
//!< 0: Normal operation<br>
//!< 1: Use white list for a received RPA regardless of filter policy
} advConfig;
uint8_t __dummy0;
struct {
uint8_t scanRspEndType:1; //!< \brief Command status at end if AUX_SCAN_RSP was sent:<br>
//!< 0: End with BLE_DONE_OK and result True<br>
//!< 1: End with BLE_DONE_SCAN_RSP and result False
} behConfig;
uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types,
//!< but only TRIG_ABSTIME and TRIG_REL_* are allowed
ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points
@@ -2258,14 +2253,41 @@ struct __RFC_STRUCT rfc_ble5ScannerPar_s {
struct {
uint8_t bCheckAdi:1; //!< \brief 0: Do not perform ADI filtering<br>
//!< 1: Perform ADI filtering on packets where ADI is present
uint8_t bAutoAdiUpdate:1; //!< \brief 0: Do not update ADI entries in radio CPU<br>
//!< 1: Automatically update ADI entry for received packets with AuxPtr
uint8_t bApplyDuplicateFiltering:1;//!< \brief 0: Do not apply duplicate filtering based on device address for extended advertiser packets<br>
//!< 1: Apply duplicate filtering based on device address for extended advertiser packets with no ADI field
uint8_t bAutoAdiUpdate:1; //!< \brief 0: Do not update ADI entries in radio CPU using legacy mode (recommended)<br>
//!< 1: Legacy mode: Automatically update ADI entry for received packets with
//!< AdvDataInfo after first occurrence
uint8_t bApplyDuplicateFiltering:1;//!< \brief 0: Do not apply duplicate filtering based on device address for extended
//!< advertiser packets (recommended)<br>
//!< 1: Apply duplicate filtering based on device address for extended advertiser
//!< packets with no ADI field
uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for extended advertising packets<br>
//!< 1: Automatically set ignore bit in white list for extended advertising packets
uint8_t bAutoAdiProcess:1; //!< \brief 0: Do not use automatic ADI processing<br>
//!< 1: Automatically update ADI entry for received packets so that only the same
//!< ADI is accepted for the rest of the chain and the SID/DID combination is
//!< ignored after the entire chain is received.
uint8_t bExclusiveSid:1; //!< \brief 0: Set <code>adiStatus.state</code> to 0 when command starts so that all
//!< valid SIDs are accepted<br>
//!< 1: Do not modify adiStatus.state when command starts<br>
} extFilterConfig;
uint32_t __dummy0;
struct {
uint8_t lastAcceptedSid:4; //!< Indication of SID of last successfully received packet that was not ignored
uint8_t state:3; //!< \brief 0: No extended packet received, or last extended packet didn't have an ADI;
//!< <code>lastAcceptedSid</code> field is not valid<br>
//!< 1: A message with ADI has been received, but no chain is under reception;
//!< ADI filtering to be performed normally<br>
//!< 2: A message with SID as given in <code>lastAcceptedSid</code> has been
//!< received, and chained messages are still pending. Messages without this
//!< SID will be ignored<br>
//!< 3: An AUX_SCAN_RSP message has been received after receiving messages with SID
//!< as given in <code>lastAcceptedSid</code>, and chained messages are
//!< pending. Messages with an ADI field will be ignored.<br>
//!< 4: A message with no ADI has been received, and chained messages are still
//!< pending. Messages with an ADI field will be ignored.<br>
//!< Others: <i>Reserved</i>
} adiStatus;
uint8_t __dummy0;
uint16_t __dummy1;
uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device.
//!< If least significant bit is 1, the address type given by
//!< <code>scanConfig.deviceAddrType</code> is inverted.
@@ -2332,7 +2354,7 @@ struct __RFC_STRUCT rfc_ble5InitiatorPar_s {
uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
//!< 1: Discard messages with illegal length for the given packet type
uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2 in CONNECT_IND<br>
//!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND (patch required)
//!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND
} initConfig;
uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure
uint16_t backoffCount; //!< Parameter <i>backoffCount</i> used in backoff procedure, cf. Bluetooth spec
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h
Vendored
+3 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_ble_mailbox.h
* Revised: 2018-01-23 19:51:42 +0100 (Tue, 23 Jan 2018)
* Revision: 18189
* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018)
* Revision: 18171
*
* Description: Definitions for BLE interface
*
@@ -54,6 +54,7 @@
#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command
#define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead
#define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2
#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted
///@}
/// \name Operation finished with error
///@{
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h
Vendored
+27 -3
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_common_cmd.h
* Revised: 2018-05-07 15:02:01 +0200 (Mon, 07 May 2018)
* Revision: 18438
* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018)
* Revision: 18756
*
* Description: CC13x2/CC26x2 API for common/generic commands
*
@@ -103,9 +103,11 @@ typedef struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s rfc_CMD_DISARM_RAT_CH_t;
typedef struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s rfc_CMD_SET_TX_POWER_t;
typedef struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s rfc_CMD_SET_TX20_POWER_t;
typedef struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s rfc_CMD_CHANGE_PA_t;
typedef struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s rfc_CMD_UPDATE_HPOSC_FREQ_t;
typedef struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s rfc_CMD_UPDATE_FS_t;
typedef struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s rfc_CMD_MODIFY_FS_t;
typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t;
typedef struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s rfc_CMD_SET_CMD_START_IRQ_t;
//! \addtogroup command
//! @{
@@ -256,7 +258,7 @@ struct __RFC_STRUCT rfc_CMD_FS_s {
uint8_t bTxMode:1; //!< \brief 0: Start synth in RX mode<br>
//!< 1: Start synth in TX mode
uint8_t refFreq:6; //!< \brief 0: Use default reference frequency<br>
//!< Others: Use reference frequency 24 MHz/<code>refFreq</code>
//!< Others: Use reference frequency 48 MHz/<code>refFreq</code>
} synthConf;
uint8_t __dummy0; //!< <i>Reserved</i>, always write 0
uint8_t __dummy1; //!< <i>Reserved</i>
@@ -1020,6 +1022,17 @@ struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s {
//! @}
//! \addtogroup CMD_UPDATE_HPOSC_FREQ
//! @{
#define CMD_UPDATE_HPOSC_FREQ 0x0608
//! Set New Frequency Offset for HPOSC
struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s {
uint16_t commandNo; //!< The command ID number 0x0608
int16_t freqOffset; //!< Relative frequency offset, signed, scaled by 2<sup>-22</sup>
} __RFC_STRUCT_ATTR;
//! @}
//! \addtogroup CMD_UPDATE_FS
//! @{
#define CMD_UPDATE_FS 0x0011
@@ -1060,6 +1073,17 @@ struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s {
//! @}
//! \addtogroup CMD_SET_CMD_START_IRQ
//! @{
#define CMD_SET_CMD_START_IRQ 0x0411
//! Enable or disable generation of IRQ when a radio operation command starts
struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s {
uint16_t commandNo; //!< The command ID number 0x0411
uint8_t bEna; //!< 1 to enable interrupt generation; 0 to disable it
} __RFC_STRUCT_ATTR;
//! @}
//! @}
//! @}
#endif
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_data_entry.h
* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017)
* Revision: 18052
* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
* Revision: 18170
*
* Description: Definition of API for data exchange
*
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_hs_cmd.h
* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017)
* Revision: 18052
* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
* Revision: 18170
*
* Description: CC13x2/CC26x2 API for high-speed mode commands
*
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_hs_mailbox.h
* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017)
* Revision: 18032
* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018)
* Revision: 18171
*
* Description: Definitions for high-speed mode radio interface
*
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_ieee_cmd.h
* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017)
* Revision: 18052
* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
* Revision: 18170
*
* Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands
*
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h
Vendored
+20 -5
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_mailbox.h
* Revised: 2018-05-07 15:02:01 +0200 (Mon, 07 May 2018)
* Revision: 18438
* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018)
* Revision: 18756
*
* Description: Definitions for interface between system and radio CPU
*
@@ -83,6 +83,8 @@ typedef struct {
#define IRQN_TX_RETRANS 9 ///< Packet retransmitted
#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished
#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete
#define IRQN_COMMAND_STARTED 12 ///< A radio operation command has gone into active state
#define IRQN_FG_COMMAND_STARTED 13 ///< FG level radio operation command has gone into active state
#define IRQN_PA_CHANGED 14 ///< PA is changed
#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored
#define IRQN_RX_NOK 17 ///< Packet received with CRC error
@@ -117,6 +119,8 @@ typedef struct {
#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE)
#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED)
#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED)
#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED)
#define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED)
#define IRQ_RX_OK (1U << IRQN_RX_OK)
@@ -301,13 +305,19 @@ typedef struct {
(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16))
/// 8-bit SW register as defined in radio_par_def.txt
#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \
((uint32_t)(val) << 16))
(((uint32_t)(val) & 0xFF) << 16))
/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte.
#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \
(((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24))
#define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \
((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24))
#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \
((uint32_t)(length) << 16) | (1U << 30))
#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
#define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val))
#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \
((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30))
#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \
@@ -317,10 +327,15 @@ typedef struct {
((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \
((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \
(((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24))
#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x001B | ((flags & 0x07) << 9) | \
((((((12 * 24) << 20) / ((uint32_t) centerFreq)) + 1) / 2) << 12))
#define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16))
#define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10))
#define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10))
#define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \
(0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27))
#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \
((centerFreq) << 20))
#define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \
((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) )
#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \
(((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \
(((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_prop_cmd.h
* Revised: 2018-05-07 15:02:01 +0200 (Mon, 07 May 2018)
* Revision: 18438
* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018)
* Revision: 18572
*
* Description: CC13x2/CC26x2 API for Proprietary mode commands
*
third_party/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rf_prop_mailbox.h
* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017)
* Revision: 18032
* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018)
* Revision: 18171
*
* Description: Definitions for proprietary mode radio interface
*
third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.c
Vendored
+69 -6
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rfc.c
* Revised: 2018-01-30 17:42:58 +0100 (Tue, 30 Jan 2018)
* Revision: 51371
* Revised: 2018-08-08 11:04:37 +0200 (Wed, 08 Aug 2018)
* Revision: 52334
*
* Description: Driver for the RF Core.
*
@@ -61,9 +61,10 @@
#define RFCOverrideUpdate NOROM_RFCOverrideUpdate
#undef RFCHwIntGetAndClear
#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear
#undef RFCAnaDivTxOverride
#define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride
#endif
// Function is not complete
//*****************************************************************************
//
@@ -144,7 +145,8 @@ RFCSynthPowerDown(void)
// Reset previously patched CPE RAM to a state where it can be patched again
//
//*****************************************************************************
void RFCCpePatchReset(void)
void
RFCCpePatchReset(void)
{
// Function is not complete
}
@@ -174,15 +176,74 @@ RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint3
return 0xFF;
}
//*****************************************************************************
//
// Function to calculate the proper override run-time for the High Gain PA.
//
//*****************************************************************************
uint32_t
RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode)
{
uint16_t fsOnly;
uint16_t txSetting;
switch (loDivider)
{
case 0: fsOnly = 0x0502;
break;
case 2:
fsOnly = 0x0102;
break;
case 4:
case 6:
case 12:
fsOnly = 0xF101;
break;
case 5:
case 10:
case 15:
case 30:
fsOnly = 0x1101;
break;
default:
// Error, should not occur!
fsOnly = 0;
break;
}
if (frontEndMode == 255)
{
// Special value meaning 20 dBm PA
txSetting = (fsOnly | 0x00C0) & ~0x0400;
}
else if (frontEndMode == 0)
{
// Differential
txSetting = fsOnly | 0x0030;
}
else if (frontEndMode & 1)
{
// Single ended on RFP
txSetting = fsOnly | 0x0010;
}
else
{
// Single ended on RFN
txSetting = fsOnly | 0x0020;
}
return ((((uint32_t) txSetting) << 16) | RFC_FE_OVERRIDE_ADDRESS);
}
//*****************************************************************************
//
// Update the override list based on values stored in FCFG1
//
//*****************************************************************************
uint8_t RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams)
uint8_t
RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams)
{
// Function is not complete
// Function is left blank for compatibility reasons.
return 0;
}
@@ -227,6 +288,8 @@ RFCHwIntGetAndClear(uint32_t ui32Mask)
#define RFCOverrideUpdate NOROM_RFCOverrideUpdate
#undef RFCHwIntGetAndClear
#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear
#undef RFCAnaDivTxOverride
#define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride
#endif
// See rfc.h for implementation
third_party/ti/devices/cc13x2_cc26x2/driverlib/rfc.h
Vendored
+26 -10
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rfc.h
* Revised: 2018-04-25 22:52:33 +0200 (Wed, 25 Apr 2018)
* Revision: 51935
* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018)
* Revision: 52338
*
* Description: Defines and prototypes for the RF Core.
*
@@ -63,12 +63,12 @@ extern "C"
#include "../inc/hw_memmap.h"
#include "../inc/hw_rfc_pwr.h"
#include "../inc/hw_rfc_dbell.h"
#include "rf_common_cmd.h"
#include "rf_prop_cmd.h"
#include "rf_ble_cmd.h"
#include "../inc/hw_fcfg1.h"
#include "../inc/hw_adi_3_refsys.h"
#include "../inc/hw_adi.h"
#include "rf_common_cmd.h"
#include "rf_prop_cmd.h"
#include "rf_ble_cmd.h"
// Definition of RFTRIM container
typedef struct {
@@ -79,11 +79,14 @@ typedef struct {
} rfTrim_t;
// Definition of maximum search depth used by the RFCOverrideUpdate function
#define RFC_MAX_SEARCH_DEPTH 5
#define RFC_PA_TYPE_ADDRESS 0x21000345
#define RFC_PA_TYPE_MASK 0x04
#define RFC_PA_GAIN_ADDRESS 0x2100034C
#define RFC_PA_GAIN_MASK 0x003FFFFF
#define RFC_MAX_SEARCH_DEPTH 5
#define RFC_PA_TYPE_ADDRESS 0x21000345
#define RFC_PA_TYPE_MASK 0x04
#define RFC_PA_GAIN_ADDRESS 0x2100034C
#define RFC_PA_GAIN_MASK 0x003FFFFF
#define RFC_FE_MODE_ESCAPE_VALUE 0xFF
#define RFC_FE_OVERRIDE_ADDRESS 0x0703
#define RFC_FE_OVERRIDE_MASK 0x0000FFFF
//*****************************************************************************
//
@@ -106,6 +109,7 @@ typedef struct {
#define RFCOverrideSearch NOROM_RFCOverrideSearch
#define RFCOverrideUpdate NOROM_RFCOverrideUpdate
#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear
#define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride
#endif
//*****************************************************************************
@@ -392,6 +396,14 @@ RFCGetPaGain(void)
}
//*****************************************************************************
//
//! Function to calculate the proper override run-time for the High Gain PA.
//
//*****************************************************************************
extern uint32_t RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode);
//*****************************************************************************
//
// Support for DriverLib in ROM:
@@ -428,6 +440,10 @@ RFCGetPaGain(void)
#undef RFCHwIntGetAndClear
#define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear
#endif
#ifdef ROM_RFCAnaDivTxOverride
#undef RFCAnaDivTxOverride
#define RFCAnaDivTxOverride ROM_RFCAnaDivTxOverride
#endif
#endif
//*****************************************************************************
third_party/ti/devices/cc13x2_cc26x2/driverlib/rom.h
Vendored
+205 -59
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: rom.h
* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
* Revision: 47343
* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018)
* Revision: 53196
*
* Description: Prototypes for the ROM utility functions.
*
@@ -157,8 +157,8 @@ typedef struct
#define HapiSelectDACVref(a) P_HARD_API->SelectDACVref(a)
// Defines for input parameter to the HapiSelectCompAInput function.
// The define values can not be changed!
#define COMPA_IN_NC 0x00
// Defines used in CC13x0/CC26x0 devices
#define COMPA_IN_AUXIO7 0x09
#define COMPA_IN_AUXIO6 0x0A
#define COMPA_IN_AUXIO5 0x0B
@@ -167,14 +167,23 @@ typedef struct
#define COMPA_IN_AUXIO2 0x0E
#define COMPA_IN_AUXIO1 0x0F
#define COMPA_IN_AUXIO0 0x10
// Defines used in CC13x2/CC26x2 devices
#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7
#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6
#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5
#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4
#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3
#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2
#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1
#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0
// Defines for input parameter to the HapiSelectCompARef function.
// The define values can not be changed!
#define COMPA_REF_NC 0x00
#define COMPA_REF_DCOUPL 0x01
#define COMPA_REF_VSS 0x02
#define COMPA_REF_VDDS 0x03
#define COMPA_REF_ADCVREFP 0x04
// Defines used in CC13x0/CC26x0 devices
#define COMPA_REF_AUXIO7 0x09
#define COMPA_REF_AUXIO6 0x0A
#define COMPA_REF_AUXIO5 0x0B
@@ -183,13 +192,22 @@ typedef struct
#define COMPA_REF_AUXIO2 0x0E
#define COMPA_REF_AUXIO1 0x0F
#define COMPA_REF_AUXIO0 0x10
// Defines used in CC13x2/CC26x2 devices
#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7
#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6
#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5
#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4
#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3
#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2
#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1
#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0
// Defines for input parameter to the HapiSelectADCCompBInput function.
// The define values can not be changed!
#define ADC_COMPB_IN_NC 0x00
#define ADC_COMPB_IN_DCOUPL 0x03
#define ADC_COMPB_IN_VSS 0x04
#define ADC_COMPB_IN_VDDS 0x05
// Defines used in CC13x0/CC26x0 devices
#define ADC_COMPB_IN_AUXIO7 0x09
#define ADC_COMPB_IN_AUXIO6 0x0A
#define ADC_COMPB_IN_AUXIO5 0x0B
@@ -198,6 +216,15 @@ typedef struct
#define ADC_COMPB_IN_AUXIO2 0x0E
#define ADC_COMPB_IN_AUXIO1 0x0F
#define ADC_COMPB_IN_AUXIO0 0x10
// Defines used in CC13x2/CC26x2 devices
#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7
#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6
#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5
#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4
#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3
#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2
#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1
#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0
// Defines for input parameter to the HapiSelectDACVref function.
// The define values can not be changed!
@@ -243,6 +270,9 @@ typedef struct
#define ROM_API_SETUP_ROM_TABLE ((uint32_t*) (ROM_API_TABLE[28]))
#define ROM_API_I2S_TABLE ((uint32_t*) (ROM_API_TABLE[29]))
#define ROM_API_PWR_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[30]))
#define ROM_API_AES_TABLE ((uint32_t*) (ROM_API_TABLE[31]))
#define ROM_API_PKA_TABLE ((uint32_t*) (ROM_API_TABLE[32]))
#define ROM_API_SHA2_TABLE ((uint32_t*) (ROM_API_TABLE[33]))
// AON_EVENT FUNCTIONS
#define ROM_AONEventMcuWakeUpSet \
@@ -668,56 +698,6 @@ typedef struct
ROM_API_VIMS_TABLE[3])
// CRYPTO FUNCTIONS
#define ROM_CRYPTOAesEcb \
((uint32_t (*)(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)) \
ROM_API_CRYPTO_TABLE[0])
#define ROM_CRYPTOAesEcbStatus \
((uint32_t (*)(void)) \
ROM_API_CRYPTO_TABLE[1])
#define ROM_CRYPTOCcmAuthEncrypt \
((uint32_t (*)(bool bEncrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32PlainText, uint32_t ui32PlainTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)) \
ROM_API_CRYPTO_TABLE[3])
#define ROM_CRYPTOCcmAuthEncryptResultGet \
((uint32_t (*)(uint32_t ui32TagLength, uint32_t *pui32CcmTag)) \
ROM_API_CRYPTO_TABLE[4])
#define ROM_CRYPTOCcmAuthEncryptStatus \
((uint32_t (*)(void)) \
ROM_API_CRYPTO_TABLE[5])
#define ROM_CRYPTOCcmInvAuthDecrypt \
((uint32_t (*)(bool bDecrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)) \
ROM_API_CRYPTO_TABLE[6])
#define ROM_CRYPTOCcmInvAuthDecryptResultGet \
((uint32_t (*)(uint32_t ui32AuthLength, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32CcmTag)) \
ROM_API_CRYPTO_TABLE[7])
#define ROM_CRYPTOCcmInvAuthDecryptStatus \
((uint32_t (*)(void)) \
ROM_API_CRYPTO_TABLE[8])
#define ROM_CRYPTOAesCbc \
((uint32_t (*)(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, uint32_t *pui32Nonce, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)) \
ROM_API_CRYPTO_TABLE[9])
#define ROM_CRYPTOAesCbcStatus \
((uint32_t (*)(void)) \
ROM_API_CRYPTO_TABLE[10])
#define ROM_CRYPTODmaDisable \
((void (*)(uint32_t ui32Channels)) \
ROM_API_CRYPTO_TABLE[11])
#define ROM_CRYPTODmaEnable \
((void (*)(uint32_t ui32Channels)) \
ROM_API_CRYPTO_TABLE[12])
// OSC FUNCTIONS
#define ROM_OSCClockSourceGet \
((uint32_t (*)(uint32_t ui32SrcClk)) \
@@ -727,10 +707,6 @@ typedef struct
((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \
ROM_API_OSC_TABLE[1])
#define ROM_OSC_HPOSCRelativeFrequencyOffsetGet \
((int32_t (*)(int32_t tempDegC)) \
ROM_API_OSC_TABLE[2])
#define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \
((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \
ROM_API_OSC_TABLE[3])
@@ -807,6 +783,10 @@ typedef struct
// SETUP_ROM FUNCTIONS
#define ROM_SetupAfterColdResetWakeupFromShutDownCfg1 \
((void (*)(uint32_t ccfg_ModeConfReg)) \
ROM_API_SETUP_ROM_TABLE[0])
#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \
((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \
ROM_API_SETUP_ROM_TABLE[1])
@@ -879,6 +859,10 @@ typedef struct
((void (*)(void)) \
ROM_API_SETUP_ROM_TABLE[18])
#define ROM_SetupStepVddrTrimTo \
((void (*)(uint32_t toCode)) \
ROM_API_SETUP_ROM_TABLE[19])
// I2S FUNCTIONS
#define ROM_I2SPointerSet \
@@ -896,6 +880,168 @@ typedef struct
ROM_API_PWR_CTRL_TABLE[0])
// AES FUNCTIONS
#define ROM_AESConfigureCCMCtrl \
((void (*)(uint32_t nonceLength, uint32_t macLength, bool encrypt)) \
ROM_API_AES_TABLE[0])
#define ROM_AESReadFromKeyStore \
((uint32_t (*)(uint32_t keyStoreArea)) \
ROM_API_AES_TABLE[1])
#define ROM_AESReadTag \
((uint32_t (*)(uint8_t *tag, uint32_t tagLength)) \
ROM_API_AES_TABLE[2])
#define ROM_AESSetInitializationVector \
((void (*)(const uint32_t *initializationVector)) \
ROM_API_AES_TABLE[3])
#define ROM_AESStartDMAOperation \
((void (*)(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \
ROM_API_AES_TABLE[4])
#define ROM_AESVerifyTag \
((uint32_t (*)(const uint8_t *tag, uint32_t tagLength)) \
ROM_API_AES_TABLE[5])
#define ROM_AESWaitForIRQFlags \
((uint32_t (*)(uint32_t irqFlags)) \
ROM_API_AES_TABLE[6])
#define ROM_AESWriteCCMInitializationVector \
((void (*)(const uint8_t *nonce, uint32_t nonceLength)) \
ROM_API_AES_TABLE[7])
#define ROM_AESWriteToKeyStore \
((uint32_t (*)(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)) \
ROM_API_AES_TABLE[8])
// PKA FUNCTIONS
#define ROM_PKABigNumAddGetResult \
((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \
ROM_API_PKA_TABLE[0])
#define ROM_PKABigNumCmpGetResult \
((uint32_t (*)(void)) \
ROM_API_PKA_TABLE[1])
#define ROM_PKABigNumInvModGetResult \
((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \
ROM_API_PKA_TABLE[2])
#define ROM_PKABigNumModGetResult \
((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \
ROM_API_PKA_TABLE[3])
#define ROM_PKABigNumMultGetResult \
((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \
ROM_API_PKA_TABLE[4])
#define ROM_PKAEccAddGetResult \
((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \
ROM_API_PKA_TABLE[5])
#define ROM_PKAEccAddStart \
((uint32_t (*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \
ROM_API_PKA_TABLE[6])
#define ROM_PKAEccMultiplyGetResult \
((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \
ROM_API_PKA_TABLE[7])
#define ROM_PKAEccMultiplyStart \
((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \
ROM_API_PKA_TABLE[8])
#define ROM_PKAGetOpsStatus \
((uint32_t (*)(void)) \
ROM_API_PKA_TABLE[9])
#define ROM_PKABigNumAddStart \
((uint32_t (*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \
ROM_API_PKA_TABLE[10])
#define ROM_PKABigNumCmpStart \
((uint32_t (*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \
ROM_API_PKA_TABLE[11])
#define ROM_PKABigNumInvModStart \
((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \
ROM_API_PKA_TABLE[12])
#define ROM_PKABigNumModStart \
((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \
ROM_API_PKA_TABLE[13])
#define ROM_PKABigNumMultiplyStart \
((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \
ROM_API_PKA_TABLE[14])
#define ROM_PKABigNumSubGetResult \
((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \
ROM_API_PKA_TABLE[15])
#define ROM_PKABigNumSubStart \
((uint32_t (*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \
ROM_API_PKA_TABLE[16])
#define ROM_PKAArrayAllZeros \
((bool (*)(const uint8_t *array, uint32_t arrayLength)) \
ROM_API_PKA_TABLE[17])
#define ROM_PKABigNumDivideGetQuotient \
((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)) \
ROM_API_PKA_TABLE[18])
#define ROM_PKABigNumDivideGetRemainder \
((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr)) \
ROM_API_PKA_TABLE[19])
#define ROM_PKABigNumDivideStart \
((uint32_t (*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \
ROM_API_PKA_TABLE[20])
#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \
((uint32_t (*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \
ROM_API_PKA_TABLE[21])
#define ROM_PKAZeroOutArray \
((void (*)(const uint8_t *array, uint32_t arrayLength)) \
ROM_API_PKA_TABLE[22])
#define ROM_PKAEccMontgomeryMultiplyStart \
((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \
ROM_API_PKA_TABLE[23])
// SHA2 FUNCTIONS
#define ROM_SHA2ComputeFinalHash \
((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \
ROM_API_SHA2_TABLE[0])
#define ROM_SHA2ComputeHash \
((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \
ROM_API_SHA2_TABLE[1])
#define ROM_SHA2ComputeInitialHash \
((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \
ROM_API_SHA2_TABLE[2])
#define ROM_SHA2ComputeIntermediateHash \
((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \
ROM_API_SHA2_TABLE[3])
#define ROM_SHA2StartDMAOperation \
((void (*)(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \
ROM_API_SHA2_TABLE[4])
#define ROM_SHA2WaitForIRQFlags \
((uint32_t (*)(uint32_t irqFlags)) \
ROM_API_SHA2_TABLE[5])
//*****************************************************************************
//
third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c
Vendored
+159
View File
@@ -0,0 +1,159 @@
/*******************************************************************************
* Filename: rom_crypto.c
* Revised: 2018-09-17 08:57:21 +0200 (Mon, 17 Sep 2018)
* Revision: 52619
*
* Description: This is the implementation for the API to the ECC functions
* built into ROM on the CC13x2/CC26x2.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include <stdint.h>
#include "rom_crypto.h"
////////////////////////////////////* ECC *////////////////////////////////////
#ifdef ECC_PRIME_NIST256_CURVE
//#define TEST_NIST256
//#define PARAM_P NIST256_p;
#define PARAM_P 0x100257d4;
//#define PARAM_R NIST256_r;
#define PARAM_R 0x100257f8;
//#define PARAM_A NIST256_a;
#define PARAM_A 0x1002581c;
//#define PARAM_B NIST256_b;
#define PARAM_B 0x10025840;
//#define PARAM_GX NIST256_Gx;
#define PARAM_GX 0x10025864;
//#define PARAM_GY NIST256_Gy;
#define PARAM_GY 0x10025888;
#endif
//*****************************************************************************
// ECC_initialize
//*****************************************************************************
void
ECC_initialize(uint32_t *pWorkzone)
{
// Initialize curve parameters
//data_p = (uint32_t *)PARAM_P;
*((uint32_t **)0x20000138) = (uint32_t *)PARAM_P;
//data_r = (uint32_t *)PARAM_R;
*((uint32_t **)0x2000013c) = (uint32_t *)PARAM_R;
//data_a = (uint32_t *)PARAM_A;
*((uint32_t **)0x20000140) = (uint32_t *)PARAM_A;
//data_b = (uint32_t *)PARAM_B;
*((uint32_t **)0x20000144) = (uint32_t *)PARAM_B;
//data_Gx = (uint32_t *)PARAM_GX;
*((uint32_t **)0x2000012c) = (uint32_t *)PARAM_GX;
//data_Gy = (uint32_t *)PARAM_GY;
*((uint32_t **)0x20000130) = (uint32_t *)PARAM_GY;
// Initialize window size
//win = (uint8_t) ECC_WINDOW_SIZE;
*((uint8_t *)0x20000148) = (uint8_t) ECC_WINDOW_SIZE;
// Initialize work zone
//workzone = (uint32_t *) pWorkzone;
*((uint32_t **)0x20000134) = (uint32_t *) pWorkzone;
}
typedef uint8_t(*ecc_keygen_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *);
ecc_keygen_t ecc_generatekey = (ecc_keygen_t)(0x1001f94d);
typedef uint8_t(*ecdsa_sign_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *);
ecdsa_sign_t ecc_ecdsa_sign = (ecdsa_sign_t)(0x10010381);
typedef uint8_t(*ecdsa_verify_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *);
ecdsa_verify_t ecc_ecdsa_verify = (ecdsa_verify_t)(0x1000c805);
typedef uint8_t(*ecdh_computeSharedSecret_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *);
ecdh_computeSharedSecret_t ecdh_computeSharedSecret = (ecdh_computeSharedSecret_t)(0x10023485);
//*****************************************************************************
// ECC_generateKey
//*****************************************************************************
uint8_t
ECC_generateKey(uint32_t *randString, uint32_t *privateKey,
uint32_t *publicKey_x, uint32_t *publicKey_y)
{
return (uint8_t)ecc_generatekey((uint32_t*)randString, (uint32_t*)privateKey,
(uint32_t*)publicKey_x, (uint32_t*)publicKey_y);
}
//*****************************************************************************
// ECC_ECDSA_sign
//*****************************************************************************
uint8_t
ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString,
uint32_t *sign1, uint32_t *sign2)
{
return (uint8_t)ecc_ecdsa_sign((uint32_t*)secretKey, (uint32_t*)text, (uint32_t*)randString,
(uint32_t*)sign1, (uint32_t*)sign2);
}
//*****************************************************************************
// ECC_ECDSA_verify
//*****************************************************************************
uint8_t
ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y,
uint32_t *text, uint32_t *sign1, uint32_t *sign2)
{
return (uint8_t)ecc_ecdsa_verify((uint32_t*)publicKey_x, (uint32_t*)publicKey_y, (uint32_t*)text,
(uint32_t*)sign1, (uint32_t*)sign2);
}
//*****************************************************************************
// ECC_ECDH_computeSharedSecret
//*****************************************************************************
uint8_t
ECC_ECDH_computeSharedSecret(uint32_t *privateKey, uint32_t *publicKey_x,
uint32_t *publicKey_y, uint32_t *sharedSecret_x,
uint32_t *sharedSecret_y)
{
return (uint8_t)ecdh_computeSharedSecret((uint32_t*)privateKey, (uint32_t*)publicKey_x,
(uint32_t*)publicKey_y, (uint32_t*)sharedSecret_x,
(uint32_t*)sharedSecret_y);
}
third_party/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h
Vendored
+212
View File
@@ -0,0 +1,212 @@
/******************************************************************************
* Filename: rom_crypto.h
* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018)
* Revision: 52624
*
* Description: This header file is the API to the crypto functions
* built into ROM on the CC13xx/CC26xx.
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
//*****************************************************************************
//
//! \addtogroup peripheral_group
//! @{
//! \addtogroup rom_crypto_api
//! @{
//
//*****************************************************************************
#ifndef ROM_CRYPTO_H
#define ROM_CRYPTO_H
#ifdef __cplusplus
extern "C"
{
#endif
////////////////////////////////////* ECC */////////////////////////////////////
/* Window size, valid values are 2,3,4,5.
* Higher the value, faster the computation at the expense of memory usage.
*
* Recommended workzone size (in 4-byte words)
* Window size: 3, Workzone size: 275
*
*/
#define ECC_WINDOW_SIZE 3
/*
* ECC Supported Curves, define one:
* ECC_PRIME_NIST256_CURVE
*/
#define ECC_PRIME_NIST256_CURVE
/*
* ECC Return Status Flags.
*/
// Scalar multiplication status
#define ECC_MODULUS_EVEN 0xDC
#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2
#define ECC_MODULUS_LENGTH_ZERO 0x08
#define ECC_MODULUS_MSW_IS_ZERO 0x30
#define ECC_SCALAR_TOO_LONG 0x35
#define ECC_SCALAR_LENGTH_ZERO 0x53
#define ECC_ORDER_TOO_LONG 0xC6
#define ECC_ORDER_LENGTH_ZERO 0x6C
#define ECC_X_COORD_TOO_LONG 0x3C
#define ECC_X_COORD_LENGTH_ZERO 0xC3
#define ECC_Y_COORD_TOO_LONG 0x65
#define ECC_Y_COORD_LENGTH_ZERO 0x56
#define ECC_A_COEF_TOO_LONG 0x5C
#define ECC_A_COEF_LENGTH_ZERO 0xC5
#define ECC_BAD_WINDOW_SIZE 0x66
#define ECC_SCALAR_MUL_OK 0x99
// ECDSA and ECDH status
#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28
#define ECC_ORDER_EVEN 0x82
#define ECC_ORDER_MSW_IS_ZERO 0x23
#define ECC_ECC_KEY_TOO_LONG 0x25
#define ECC_ECC_KEY_LENGTH_ZERO 0x52
#define ECC_DIGEST_TOO_LONG 0x27
#define ECC_DIGEST_LENGTH_ZERO 0x72
#define ECC_ECDSA_SIGN_OK 0x32
#define ECC_ECDSA_INVALID_SIGNATURE 0x5A
#define ECC_ECDSA_VALID_SIGNATURE 0xA5
#define ECC_SIG_P1_TOO_LONG 0x11
#define ECC_SIG_P1_LENGTH_ZERO 0x12
#define ECC_SIG_P2_TOO_LONG 0x22
#define ECC_SIG_P2_LENGTH_ZERO 0x21
#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK
#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK
#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK
//*****************************************************************************
/*!
* \brief Pass pointer to ECC memory allocation to ECC engine.
*
* This function can be called again to point the ECC workzone at
* a different memory buffer.
*
* \param pWorkzone Pointer to memory allocated for computations, input.
* See description at beginning of ECC section for
* memory requirements.
*
* \return None
*/
//*****************************************************************************
extern void ECC_initialize(uint32_t *pWorkzone);
//*****************************************************************************
/*!
* \brief Generate a key.
*
* This is used for both ECDH and ECDSA.
*
* \param randString Pointer to random string, input.
* \param privateKey Pointer to the private key, output.
* \param publicKey_x Pointer to public key X-coordinate, output.
* \param publicKey_y Pointer to public key Y-coordinate, output.
*
* \return Status
*/
//*****************************************************************************
extern uint8_t ECC_generateKey(uint32_t *randString, uint32_t *privateKey,
uint32_t *publicKey_x, uint32_t *publicKey_y);
//*****************************************************************************
/*!
* \brief Sign data.
*
* \param secretKey Pointer to the secret key, input.
* \param text Pointer to the message, input.
* \param randString Pointer to random string, input.
* \param sign1 Pointer to signature part 1, output.
* \param sign2 Pointer to signature part 2, output.
*
* \return Status
*/
//*****************************************************************************
extern uint8_t ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString,
uint32_t *sign1, uint32_t *sign2);
//*****************************************************************************
/*!
* \brief Verify signature.
*
* \param publicKey_x Pointer to public key X-coordinate, input.
* \param publicKey_y Pointer to public key Y-coordinate, input.
* \param text Pointer to message data, input.
* \param sign1 Pointer to signature part 1, input.
* \param sign2 Pointer to signature part 2, input.
*
* \return Status
*/
//*****************************************************************************
extern uint8_t ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y,
uint32_t *text, uint32_t *sign1, uint32_t *sign2);
//*****************************************************************************
/*!
* \brief Compute the shared secret.
*
* \param privateKey Pointer to private key, input.
* \param publicKey_x Pointer to public key X-coordinate, input.
* \param publicKey_y Pointer to public key Y-coordinate, input.
* \param sharedSecret_x Pointer to shared secret X-coordinate, output.
* \param sharedSecret_y Pointer to shared secret Y-coordinate, output.
*
* \return Status
*/
//*****************************************************************************
extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t *privateKey,
uint32_t *publicKey_x,
uint32_t *publicKey_y,
uint32_t *sharedSecret_x,
uint32_t *sharedSecret_y);
#ifdef __cplusplus
}
#endif
#endif /* ROM_CRYPTO_H */
//*****************************************************************************
//
//! Close the Doxygen group.
//! @}
//! @}
//
//*****************************************************************************
third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.c
Vendored
+36 -162
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: setup.c
* Revised: 2018-04-05 13:46:03 +0200 (Thu, 05 Apr 2018)
* Revision: 51853
* Revised: 2018-11-06 15:08:57 +0100 (Tue, 06 Nov 2018)
* Revision: 53239
*
* Description: Setup file for CC13xx/CC26xx devices.
*
@@ -53,6 +53,7 @@
#include "../inc/hw_aon_pmctl.h"
#include "../inc/hw_aon_rtc.h"
#include "../inc/hw_ddi_0_osc.h"
#include "../inc/hw_ddi.h"
#include "../inc/hw_ccfg.h"
#include "../inc/hw_fcfg1.h"
#include "../inc/hw_flash.h"
@@ -121,9 +122,9 @@ SetupTrimDevice(void)
ui32Fcfg1Revision = 0;
}
// This driverlib version and setup file is for the CC13x2, CC26x2 chips.
// This driverlib version and setup file is for the CC13x2, CC26x2 PG2.0 or later chips.
// Halt if violated
ThisLibraryIsFor_CC13x2_CC26x2_HaltIfViolated();
ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated();
// Enable standby in flash bank
HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
@@ -227,58 +228,6 @@ TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void )
// Currently no specific trim for Powerdown
}
// Special shadow register trim propagation on first batch of devices
static void
Step_RCOSCHF_CTRIM( uint32_t toCode )
{
uint32_t currentRcoscHfCtlReg ;
uint32_t currentTrim ;
currentRcoscHfCtlReg = HWREGH( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_RCOSCHFCTL );
currentTrim = ((( currentRcoscHfCtlReg & DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M ) >>
DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S ) ^ 0xC0 );
while ( toCode != currentTrim ) {
HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
if ( toCode > currentTrim ) currentTrim++;
else currentTrim--;
HWREGH( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_RCOSCHFCTL ) =
( currentRcoscHfCtlReg & ~DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M ) |
(( currentTrim ^ 0xC0 ) << DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S );
}
}
static void
Step_VBG( int32_t targetSigned )
{
// VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG)
uint32_t refSysCtl3Reg ;
int32_t currentSigned ;
do {
refSysCtl3Reg = HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 );
currentSigned =
(((int32_t)( refSysCtl3Reg << ( 32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S )))
>> ( 32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W ));
HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
if ( targetSigned != currentSigned ) {
if ( targetSigned > currentSigned ) currentSigned++;
else currentSigned--;
HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) =
( refSysCtl3Reg & ~( ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN | ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M )) |
((((uint32_t)currentSigned) << ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S ) & ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M );
HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit set by doing a read modify write
}
} while ( targetSigned != currentSigned );
}
//*****************************************************************************
//
//! \brief Trims to be applied when coming from SHUTDOWN (also called when
@@ -304,7 +253,16 @@ TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
}
// TBD-Agama - Temporarily removed for Agama
// TBD - Temporarily removed for CC13x2 / CC26x2
// Force DCDC to use RCOSC before starting up XOSC.
// Clock loss detector does not use XOSC until SCLK_HF actually switches
// and thus DCDC is not protected from clock loss on XOSC in that time frame.
// The force must be released when the switch to XOSC has happened. This is done
// in OSCHfSourceSwitch().
HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16);
// Dummy read to ensure that the write has propagated
HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
// read the MODE_CONF register in CCFG
ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
@@ -314,6 +272,14 @@ TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
// -Configure DCDC.
SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg );
// Addition to the CC1352 boost mode for HWREV >= 2.0
// The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) &&
(( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) )
{
HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) = ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ;
}
// Second part of trim done after cold reset and wakeup from shutdown:
// -Configure XOSC.
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
@@ -322,106 +288,6 @@ TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
#endif
// Special shadow register trim propagation on first batch of devices
{
uint32_t ui32EfuseData ;
uint32_t orgResetCtl ;
// Get VTRIM_COARSE and VTRIM_DIG from EFUSE shadow register OSC_BIAS_LDO_TRIM
ui32EfuseData = HWREG( FCFG1_BASE + FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM );
Step_RCOSCHF_CTRIM(( ui32EfuseData &
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M ) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S ) ;
// Write to register SOCLDO_0_1 (addr offset 3) bits[7:4] (VTRIM_COARSE) and
// bits[3:0] (VTRIM_DIG) in ADI_2_REFSYS. Direct write can be used since
// all register bit fields are trimmed.
HWREGB(ADI2_BASE + ADI_O_DIR + ADI_2_REFSYS_O_SOCLDOCTL1) =
((((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S) <<
ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S) |
(((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S) <<
ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S));
// Write to register CTLSOCREFSYS0 (addr offset 0) bits[4:0] (TRIMIREF) in
// ADI_2_REFSYS. Avoid using masked write access since bit field spans
// nibble boundary. Direct write can be used since this is the only defined
// bit field in this register.
HWREGB(ADI2_BASE + ADI_O_DIR + ADI_2_REFSYS_O_REFSYSCTL0) =
(((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S) <<
ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S);
// Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in
// ADI_3_REFSYS
HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL2 << 1)) =
(ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M << 8) |
(((ui32EfuseData & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S) <<
ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S);
// Get TRIMBOD_EXTMODE or TRIMBOD_INTMODE from EFUSE shadow register in FCFG1
ui32EfuseData = HWREG( FCFG1_BASE + FCFG1_O_SHDW_ANA_TRIM );
orgResetCtl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M );
HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) =
( orgResetCtl & ~( AON_PMCTL_RESETCTL_CLK_LOSS_EN |
AON_PMCTL_RESETCTL_VDD_LOSS_EN |
AON_PMCTL_RESETCTL_VDDR_LOSS_EN |
AON_PMCTL_RESETCTL_VDDS_LOSS_EN ));
HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for xxx_LOSS_EN setting to propagate
// The VDDS_BOD trim and the VDDR trim is already stepped up to max/HH if "CC1352 boost mode" is requested.
// See function SetupAfterColdResetWakeupFromShutDownCfg1() in setup_rom.c for details.
if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) != 0 ) ||
(( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) == 0 ) )
{
if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
AON_PMCTL_PWRCTL_EXT_REG_MODE)
{
// Apply VDDS BOD trim value
// Write to register CTLSOCREFSYS1 (addr offset 3) bit[7:3] (TRIMBOD)
// in ADI_3_REFSYS
HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL1 << 1)) =
(ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8) |
(((ui32EfuseData & FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M) >>
FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S) <<
ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S);
}
else
{
// Apply VDDS BOD trim value
// Write to register CTLSOCREFSYS1 (addr offset 3) bit[7:3] (TRIMBOD)
// in ADI_3_REFSYS
HWREGH(ADI3_BASE + ADI_O_MASK8B + (ADI_3_REFSYS_O_REFSYSCTL1 << 1)) =
(ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8) |
(((ui32EfuseData & FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M) >>
FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S) <<
ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S);
}
// Load the new VDDS_BOD setting
HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) &= ~ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit clear by doing a read modify write
HWREGB( ADI3_BASE + ADI_3_REFSYS_O_REFSYSCTL3 ) |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; // Bit set by doing a read modify write
SetupStepVddrTrimTo(( ui32EfuseData &
FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M ) >>
FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S ) ;
}
// VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG)
Step_VBG(((int32_t)( ui32EfuseData << ( 32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S )))
>> ( 32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W ));
// Wait two more LF edges before restoring xxx_LOSS_EN settings
HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = orgResetCtl;
HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for xxx_LOSS_EN setting to propagate
}
{
uint32_t trimReg ;
uint32_t ui32TrimValue ;
@@ -432,11 +298,19 @@ TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ;
HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) &
ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ;
//--- Set fixed LPM_BIAS values --- LPM_BIAS_BACKUP_EN = 1 and LPM_BIAS_WIDTH_TRIM = 3
HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3
(( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8]
( 3 << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0]
// Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration
if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) {
HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
} else {
HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
}
// Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration
{
uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S );
HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3
(( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8]
( widthTrim << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0]
}
}
// Third part of trim done after cold reset and wakeup from shutdown:
third_party/ti/devices/cc13x2_cc26x2/driverlib/setup.h
Vendored
+19 -6
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: setup.h
* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016)
* Revision: 47152
* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018)
* Revision: 52993
*
* Description: Prototypes and defines for the setup API.
*
@@ -83,11 +83,24 @@ extern "C"
//*****************************************************************************
//
//! \brief Performs the necessary trim of the device which is not done in boot code.
//! \brief Performs the necessary trim of the device which is not done in ROM boot code.
//!
//! This function should only execute coming from ROM boot. The current
//! implementation does not take soft reset into account. However, it does no
//! damage to execute it again. It only consumes time.
//! This function should only execute coming from ROM boot.
//!
//! The following is handled by this function:
//! - Checks if the driverlib variant used by the application is supported by the
//! device. Execution is halted in case of unsupported driverlib variant.
//! - Configures VIMS cache mode based on setting in CCFG.
//! - Configures functionalities like DCDC and XOSC dependent on startup modes like
//! cold reset, wakeup from shutdown and wakeup from from powerdown.
//! - Configures VIMS power domain control.
//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep.
//!
//! \note The current implementation does not take soft reset into account. However,
//! it does no damage to execute it again. It only consumes time.
//!
//! \note This function is called by the compiler specific device startup codes
//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices.
//!
//! \return None
//
third_party/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h
Vendored
+41 -18
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: setup_rom.h
* Revised: 2017-09-04 19:00:53 +0200 (Mon, 04 Sep 2017)
* Revision: 49686
* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018)
* Revision: 52993
*
* Description: Prototypes and defines for the setup API.
*
@@ -102,9 +102,19 @@ extern "C"
//*****************************************************************************
//
//! \brief First part of configuration required when waking up from shutdown.
//! \brief First part of configuration required after cold reset and when waking up from shutdown.
//!
//! \param ccfg_ModeConfReg
//! Configures the following based on settings in CCFG (Customer Configuration area:
//! - Boost mode for CC13xx devices
//! - Minimal VDDR voltage threshold used during sleep mode
//! - DCDC functionality:
//! - Selects if DCDC or GLDO regulator will be used for VDDR in active mode
//! - Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode
//!
//! In addition the battery monitor low limit for internal regulator mode is set
//! to a hard coded value.
//!
//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register
//!
//! \return None
//
@@ -113,10 +123,14 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg
//*****************************************************************************
//
//! \brief Second part of configuration required when waking up from shutdown.
//! \brief Second part of configuration required after cold reset and when waking up from shutdown.
//!
//! \param ui32Fcfg1Revision
//! \param ccfg_ModeConfReg
//! Configures and trims functionalites required for use of XOSC_HF.
//! The configurations and trimmings are based on settings in FCFG1 (Factory
//! Configuration area) and partly on \c ccfg_ModeConfReg.
//!
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register
//!
//! \return None
//
@@ -125,9 +139,18 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revisio
//*****************************************************************************
//
//! \brief Third part of configuration required when waking up from shutdown.
//! \brief Third part of configuration required after cold reset and when waking up from shutdown.
//!
//! \param ccfg_ModeConfReg
//! Configures the following:
//! - XOSC source selection based on \c ccfg_ModeConfReg. If HPOSC is selected on a
//! HPOSC device the oscillator is configured based on settings in FCFG1 (Factory
//! Configuration area).
//! - Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver.
//! - Duration of the XOSC_HF fast startup mode based on FCFG1 setting.
//! - SCLK_LF based on \c ccfg_ModeConfReg.
//! - Output voltage of ADC fixed reference based on FCFG1 setting.
//!
//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register
//!
//! \return None
//
@@ -138,7 +161,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg
//
//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting.
//!
//! \param ui32Fcfg1Revision
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//!
//! \return Returns the trim value from FCFG1.
//
@@ -149,7 +172,7 @@ extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision );
//
//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting.
//!
//! \param ui32Fcfg1Revision
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//!
//! \return Returns the trim value from FCFG1.
//
@@ -160,7 +183,7 @@ extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision );
//
//! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG.
//!
//! \param ui32Fcfg1Revision
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//!
//! \return Returns the trim value.
//
@@ -189,7 +212,7 @@ extern uint32_t SetupGetTrimForAmpcompTh2( void );
//
//! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG.
//!
//! \param ccfg_ModeConfReg
//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register
//!
//! \return Returns the trim value.
//
@@ -200,7 +223,7 @@ extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg );
//
//! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting.
//!
//! \param ui32Fcfg1Revision
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//!
//! \return Returns the trim value from FCFG1.
//
@@ -211,7 +234,7 @@ extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Rev
//
//! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG.
//!
//! \param ui32Fcfg1Revision
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//!
//! \return Returns the trim value.
//
@@ -222,7 +245,7 @@ extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision );
//
//! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM.
//!
//! \param ui32Fcfg1Revision
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//!
//! \return Returns the trim value from FCFG1.
//
@@ -243,7 +266,7 @@ extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void );
//
//! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG.
//!
//! \param ui32Fcfg1Revision
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//!
//! \return Returns the trim value.
//
@@ -274,7 +297,7 @@ extern uint32_t SetupGetTrimForXoscHfIbiastherm( void );
//! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet
//! spanning bits [5:0] in the returned value.
//!
//! \param ui32Fcfg1Revision
//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
//!
//! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet.
//
third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c
Vendored
+4 -9
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: sys_ctrl.c
* Revised: 2017-11-07 11:56:04 +0100 (Tue, 07 Nov 2017)
* Revision: 50203
* Revised: 2018-06-26 15:19:11 +0200 (Tue, 26 Jun 2018)
* Revision: 52220
*
* Description: Driver for the System Control.
*
@@ -199,13 +199,8 @@ void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode
// adaptive recharge mode and fixed parameter values
if(rechargeMode == SYSCTRL_PREFERRED_RECHARGE_MODE)
{
if (( HWREG( FCFG1_BASE + FCFG1_O_TFW_FT ) % 10000 ) >= 683 ) {
// Enable the Recharge Comparator
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR;
} else {
// Set conservative recharge mode
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = 0x80A4E708;
}
// Enable the Recharge Comparator
HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR;
}
else
{
third_party/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: sys_ctrl.h
* Revised: 2017-11-07 11:56:04 +0100 (Tue, 07 Nov 2017)
* Revision: 50203
* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018)
* Revision: 52634
*
* Description: Defines and prototypes for the System Controller.
*
third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_adi_2_refsys_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h
Vendored
+19 -3
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_adi_3_refsys_h
* Revised: 2017-02-18 14:22:30 +0100 (Sat, 18 Feb 2017)
* Revision: 48483
* Revised: 2018-09-27 10:33:21 +0200 (Thu, 27 Sep 2018)
* Revision: 52772
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
@@ -67,7 +67,7 @@
// DCDC Control 2
#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008
// DCDC Control 3
// Internal
#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009
// Internal
@@ -451,6 +451,22 @@
// Register: ADI_3_REFSYS_O_DCDCCTL3
//
//*****************************************************************************
// Field: [1:0] VDDR_BOOST_COMP
//
// Internal. Only to be used through TI provided API.
// ENUMs:
// BOOST_P1 Internal. Only to be used through TI provided API.
// BOOST Internal. Only to be used through TI provided API.
// BOOST_N1 Internal. Only to be used through TI provided API.
// DEFAULT Internal. Only to be used through TI provided API.
#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_W 2
#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_M 0x00000003
#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_S 0
#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_P1 0x00000003
#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002
#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_N1 0x00000001
#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_DEFAULT 0x00000000
//*****************************************************************************
//
// Register: ADI_3_REFSYS_O_DCDCCTL4
third_party/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h
Vendored
+31 -4
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_adi_4_aux_h
* Revised: 2017-05-04 11:51:48 +0200 (Thu, 04 May 2017)
* Revision: 48895
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
@@ -76,6 +76,9 @@
// ADC Reference 1
#define ADI_4_AUX_O_ADCREF1 0x0000000B
// Internal
#define ADI_4_AUX_O_LPMBIAS 0x0000000E
//*****************************************************************************
//
// Register: ADI_4_AUX_O_MUX0
@@ -272,6 +275,13 @@
#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040
#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6
// Field: [5:3] LPM_BIAS_WIDTH_TRIM
//
// Internal. Only to be used through TI provided API.
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_W 3
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3
// Field: [2] COMPB_EN
//
// COMPB enable
@@ -421,9 +431,14 @@
//*****************************************************************************
// Field: [6] REF_ON_IDLE
//
// Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0.
// Enable ADCREF in IDLE state.
//
// Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time)
// 0: Disabled in IDLE state
// 1: Enabled in IDLE state
//
// Keep ADCREF enabled when ADC0.SMPL_MODE = 0.
// Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than
// 0x6 (21.3us sampling time).
#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040
#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040
#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6
@@ -482,5 +497,17 @@
#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F
#define ADI_4_AUX_ADCREF1_VTRIM_S 0
//*****************************************************************************
//
// Register: ADI_4_AUX_O_LPMBIAS
//
//*****************************************************************************
// Field: [5:0] LPM_TRIM_IOUT
//
// Internal. Only to be used through TI provided API.
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_W 6
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0
#endif // __ADI_4_AUX__
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aon_batmon_h
* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017)
* Revision: 49005
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aon_event_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aon_ioc_h
* Revised: 2017-05-18 09:01:49 +0200 (Thu, 18 May 2017)
* Revision: 49008
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aon_pmctl_h
* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018)
* Revision: 51887
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aon_rtc_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_aiodio_h
* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017)
* Revision: 49005
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_anaif_h
* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017)
* Revision: 49733
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_evctl_h
* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018)
* Revision: 51887
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_mac_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_ram_h
* Revised: 2017-05-06 20:38:09 +0200 (Sat, 06 May 2017)
* Revision: 48921
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_sce_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_smph_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_spim_h
* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017)
* Revision: 49005
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h
Vendored
+2 -2
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@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_sysif_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h
Vendored
+2 -2
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@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_tdc_h
* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017)
* Revision: 49005
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h
Vendored
+2 -2
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@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_timer01_h
* Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017)
* Revision: 49040
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_aux_timer2_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h
Vendored
+3 -5
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_ccfg_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-10-19 08:48:09 +0200 (Fri, 19 Oct 2018)
* Revision: 52957
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
@@ -415,9 +415,7 @@
// Field: [19:18] XOSC_FREQ
//
// Reserved for future use. Software should not rely on the value of a
// reserved. Writing any other value than the reset/default value may result in
// undefined behavior.
// Selects high precision HF oscillator (activated when using the radio).
// ENUMs:
// 24M 24 MHz XOSC_HF
// 48M 48 MHz XOSC_HF
third_party/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_ccfg_simple_struct_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h
Vendored
+1 -1
View File
@@ -195,7 +195,7 @@ extern "C"
#define CC_GET_CHIP_FAMILY 0x26
#define CC_GET_CHIP_OPTION 0x3
#define CC_GET_CHIP_HWREV 0x10
#define CC_GET_CHIP_HWREV 0x20
#ifdef CC_CHIP_ID
/* Define chip package only if specified */
third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_cpu_dwt_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_cpu_fpb_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_cpu_itm_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_cpu_rom_table_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_cpu_scs_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_cpu_tiprop_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_cpu_tpiu_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_crypto_h
* Revised: 2017-05-04 11:51:48 +0200 (Thu, 04 May 2017)
* Revision: 48895
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_ddi_0_osc_h
* Revised: 2017-05-04 11:51:48 +0200 (Thu, 04 May 2017)
* Revision: 48895
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_event.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_event_h
* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017)
* Revision: 49005
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h
Vendored
+175 -320
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_fcfg1_h
* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018)
* Revision: 51887
* Revised: 2018-11-06 14:08:24 +0100 (Tue, 06 Nov 2018)
* Revision: 53237
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
@@ -49,6 +49,21 @@
// Internal
#define FCFG1_O_MISC_CONF_2 0x000000A4
// Internal
#define FCFG1_O_HPOSC_MEAS_5 0x000000B0
// Internal
#define FCFG1_O_HPOSC_MEAS_4 0x000000B4
// Internal
#define FCFG1_O_HPOSC_MEAS_3 0x000000B8
// Internal
#define FCFG1_O_HPOSC_MEAS_2 0x000000BC
// Internal
#define FCFG1_O_HPOSC_MEAS_1 0x000000C0
// Internal
#define FCFG1_O_CONFIG_CC26_FE 0x000000C4
@@ -226,40 +241,16 @@
// Internal
#define FCFG1_O_MISC_OTP_DATA_1 0x00000398
// Power Down Current Control 20C
#define FCFG1_O_PWD_CURR_20C 0x0000039C
// Power Down Current Control 35C
#define FCFG1_O_PWD_CURR_35C 0x000003A0
// Power Down Current Control 50C
#define FCFG1_O_PWD_CURR_50C 0x000003A4
// Power Down Current Control 65C
#define FCFG1_O_PWD_CURR_65C 0x000003A8
// Power Down Current Control 80C
#define FCFG1_O_PWD_CURR_80C 0x000003AC
// Power Down Current Control 95C
#define FCFG1_O_PWD_CURR_95C 0x000003B0
// Power Down Current Control 110C
#define FCFG1_O_PWD_CURR_110C 0x000003B4
// Power Down Current Control 125C
#define FCFG1_O_PWD_CURR_125C 0x000003B8
// Shadow of EFUSE:DIE_ID_0
// Shadow of EFUSE:DIE_ID_0 register
#define FCFG1_O_SHDW_DIE_ID_0 0x000003D0
// Shadow of EFUSE:DIE_ID_1
// Shadow of EFUSE:DIE_ID_1 register
#define FCFG1_O_SHDW_DIE_ID_1 0x000003D4
// Shadow of EFUSE:DIE_ID_2
// Shadow of EFUSE:DIE_ID_2 register
#define FCFG1_O_SHDW_DIE_ID_2 0x000003D8
// Shadow of EFUSE:DIE_ID_3
// Shadow of EFUSE:DIE_ID_3 register
#define FCFG1_O_SHDW_DIE_ID_3 0x000003DC
// Internal
@@ -316,6 +307,136 @@
#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF
#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0
//*****************************************************************************
//
// Register: FCFG1_O_HPOSC_MEAS_5
//
//*****************************************************************************
// Field: [31:16] HPOSC_D5
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16
#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000
#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16
// Field: [15:8] HPOSC_T5
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8
#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00
#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8
// Field: [7:0] HPOSC_DT5
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8
#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF
#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0
//*****************************************************************************
//
// Register: FCFG1_O_HPOSC_MEAS_4
//
//*****************************************************************************
// Field: [31:16] HPOSC_D4
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16
#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000
#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16
// Field: [15:8] HPOSC_T4
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8
#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00
#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8
// Field: [7:0] HPOSC_DT4
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8
#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF
#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0
//*****************************************************************************
//
// Register: FCFG1_O_HPOSC_MEAS_3
//
//*****************************************************************************
// Field: [31:16] HPOSC_D3
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16
#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000
#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16
// Field: [15:8] HPOSC_T3
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8
#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00
#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8
// Field: [7:0] HPOSC_DT3
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8
#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF
#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0
//*****************************************************************************
//
// Register: FCFG1_O_HPOSC_MEAS_2
//
//*****************************************************************************
// Field: [31:16] HPOSC_D2
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16
#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000
#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16
// Field: [15:8] HPOSC_T2
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8
#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00
#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8
// Field: [7:0] HPOSC_DT2
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8
#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF
#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0
//*****************************************************************************
//
// Register: FCFG1_O_HPOSC_MEAS_1
//
//*****************************************************************************
// Field: [31:16] HPOSC_D1
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16
#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000
#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16
// Field: [15:8] HPOSC_T1
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8
#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00
#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8
// Field: [7:0] HPOSC_DT1
//
// Internal. Only to be used through TI provided API.
#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8
#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF
#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0
//*****************************************************************************
//
// Register: FCFG1_O_CONFIG_CC26_FE
@@ -1360,11 +1481,7 @@
//*****************************************************************************
// Field: [31:28] PG_REV
//
// Field used to distinguish revisions of the device.
//
// 0: Silicon revision 1.0
// 1: Silicon revision 1.01
// 2: Silicon revision 1.1
// Field used to distinguish revisions of the device
#define FCFG1_USER_ID_PG_REV_W 4
#define FCFG1_USER_ID_PG_REV_M 0xF0000000
#define FCFG1_USER_ID_PG_REV_S 28
@@ -1879,10 +1996,6 @@
// Field: [31:28] PG_REV
//
// Field used to distinguish revisions of the device.
//
// 0: Silicon revision 1.0
// 1: Silicon revision 1.01
// 2: Silicon revision 1.1
#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4
#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000
#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28
@@ -1953,15 +2066,6 @@
#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000
#define FCFG1_MISC_OTP_DATA_PER_E_S 12
// Field: [7:0] TEST_PROGRAM_REV
//
// The revision of the test program used in the production process when FCFG1
// was programmed.
// Value migth change without warning.
#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8
#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF
#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0
//*****************************************************************************
//
// Register: FCFG1_O_IOCONF
@@ -2488,278 +2592,6 @@
#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F
#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0
//*****************************************************************************
//
// Register: FCFG1_O_PWD_CURR_20C
//
//*****************************************************************************
// Field: [31:24] DELTA_CACHE_REF
//
// Additional maximum current, in units of 1uA, with cache retention
#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8
#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000
#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24
// Field: [23:16] DELTA_RFMEM_RET
//
// Additional maximum current, in 1uA units, with RF memory retention
#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8
#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000
#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16
// Field: [15:8] DELTA_XOSC_LPM
//
// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power
// mode
#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8
#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00
#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8
// Field: [7:0] BASELINE
//
// Worst-case baseline maximum powerdown current, in units of 0.5uA
#define FCFG1_PWD_CURR_20C_BASELINE_W 8
#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF
#define FCFG1_PWD_CURR_20C_BASELINE_S 0
//*****************************************************************************
//
// Register: FCFG1_O_PWD_CURR_35C
//
//*****************************************************************************
// Field: [31:24] DELTA_CACHE_REF
//
// Additional maximum current, in units of 1uA, with cache retention
#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8
#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000
#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24
// Field: [23:16] DELTA_RFMEM_RET
//
// Additional maximum current, in 1uA units, with RF memory retention
#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8
#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000
#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16
// Field: [15:8] DELTA_XOSC_LPM
//
// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power
// mode
#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8
#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00
#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8
// Field: [7:0] BASELINE
//
// Worst-case baseline maximum powerdown current, in units of 0.5uA
#define FCFG1_PWD_CURR_35C_BASELINE_W 8
#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF
#define FCFG1_PWD_CURR_35C_BASELINE_S 0
//*****************************************************************************
//
// Register: FCFG1_O_PWD_CURR_50C
//
//*****************************************************************************
// Field: [31:24] DELTA_CACHE_REF
//
// Additional maximum current, in units of 1uA, with cache retention
#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8
#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000
#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24
// Field: [23:16] DELTA_RFMEM_RET
//
// Additional maximum current, in 1uA units, with RF memory retention
#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8
#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000
#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16
// Field: [15:8] DELTA_XOSC_LPM
//
// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power
// mode
#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8
#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00
#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8
// Field: [7:0] BASELINE
//
// Worst-case baseline maximum powerdown current, in units of 0.5uA
#define FCFG1_PWD_CURR_50C_BASELINE_W 8
#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF
#define FCFG1_PWD_CURR_50C_BASELINE_S 0
//*****************************************************************************
//
// Register: FCFG1_O_PWD_CURR_65C
//
//*****************************************************************************
// Field: [31:24] DELTA_CACHE_REF
//
// Additional maximum current, in units of 1uA, with cache retention
#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8
#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000
#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24
// Field: [23:16] DELTA_RFMEM_RET
//
// Additional maximum current, in 1uA units, with RF memory retention
#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8
#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000
#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16
// Field: [15:8] DELTA_XOSC_LPM
//
// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power
// mode
#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8
#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00
#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8
// Field: [7:0] BASELINE
//
// Worst-case baseline maximum powerdown current, in units of 0.5uA
#define FCFG1_PWD_CURR_65C_BASELINE_W 8
#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF
#define FCFG1_PWD_CURR_65C_BASELINE_S 0
//*****************************************************************************
//
// Register: FCFG1_O_PWD_CURR_80C
//
//*****************************************************************************
// Field: [31:24] DELTA_CACHE_REF
//
// Additional maximum current, in units of 1uA, with cache retention
#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8
#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000
#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24
// Field: [23:16] DELTA_RFMEM_RET
//
// Additional maximum current, in 1uA units, with RF memory retention
#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8
#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000
#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16
// Field: [15:8] DELTA_XOSC_LPM
//
// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power
// mode
#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8
#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00
#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8
// Field: [7:0] BASELINE
//
// Worst-case baseline maximum powerdown current, in units of 0.5uA
#define FCFG1_PWD_CURR_80C_BASELINE_W 8
#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF
#define FCFG1_PWD_CURR_80C_BASELINE_S 0
//*****************************************************************************
//
// Register: FCFG1_O_PWD_CURR_95C
//
//*****************************************************************************
// Field: [31:24] DELTA_CACHE_REF
//
// Additional maximum current, in units of 1uA, with cache retention
#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8
#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000
#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24
// Field: [23:16] DELTA_RFMEM_RET
//
// Additional maximum current, in 1uA units, with RF memory retention
#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8
#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000
#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16
// Field: [15:8] DELTA_XOSC_LPM
//
// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power
// mode
#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8
#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00
#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8
// Field: [7:0] BASELINE
//
// Worst-case baseline maximum powerdown current, in units of 0.5uA
#define FCFG1_PWD_CURR_95C_BASELINE_W 8
#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF
#define FCFG1_PWD_CURR_95C_BASELINE_S 0
//*****************************************************************************
//
// Register: FCFG1_O_PWD_CURR_110C
//
//*****************************************************************************
// Field: [31:24] DELTA_CACHE_REF
//
// Additional maximum current, in units of 1uA, with cache retention
#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8
#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000
#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24
// Field: [23:16] DELTA_RFMEM_RET
//
// Additional maximum current, in 1uA units, with RF memory retention
#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8
#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000
#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16
// Field: [15:8] DELTA_XOSC_LPM
//
// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power
// mode
#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8
#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00
#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8
// Field: [7:0] BASELINE
//
// Worst-case baseline maximum powerdown current, in units of 0.5uA
#define FCFG1_PWD_CURR_110C_BASELINE_W 8
#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF
#define FCFG1_PWD_CURR_110C_BASELINE_S 0
//*****************************************************************************
//
// Register: FCFG1_O_PWD_CURR_125C
//
//*****************************************************************************
// Field: [31:24] DELTA_CACHE_REF
//
// Additional maximum current, in units of 1uA, with cache retention
#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8
#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000
#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24
// Field: [23:16] DELTA_RFMEM_RET
//
// Additional maximum current, in 1uA units, with RF memory retention
#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8
#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000
#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16
// Field: [15:8] DELTA_XOSC_LPM
//
// Additional maximum current, in units of 1uA, with XOSC_HF on in low-power
// mode
#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8
#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00
#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8
// Field: [7:0] BASELINE
//
// Worst-case baseline maximum powerdown current, in units of 0.5uA
#define FCFG1_PWD_CURR_125C_BASELINE_W 8
#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF
#define FCFG1_PWD_CURR_125C_BASELINE_S 0
//*****************************************************************************
//
// Register: FCFG1_O_SHDW_DIE_ID_0
@@ -2860,6 +2692,29 @@
// Register: FCFG1_O_SHDW_ANA_TRIM
//
//*****************************************************************************
// Field: [30] ALT_VDDR_TRIM
//
// Internal. Only to be used through TI provided API.
#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000
#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30
#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000
#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30
// Field: [29] DET_LOGIC_DIS
//
// Internal. Only to be used through TI provided API.
#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000
#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29
#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000
#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29
// Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT
//
// Internal. Only to be used through TI provided API.
#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2
#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000
#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27
// Field: [26:25] BOD_BANDGAP_TRIM_CNF
//
// Internal. Only to be used through TI provided API.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_flash.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_flash_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_gpio_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_gpram_h
* Revised: 2017-05-06 20:38:09 +0200 (Sat, 06 May 2017)
* Revision: 48921
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_gpt_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_i2c_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_i2s_h
* Revised: 2017-11-02 10:21:28 +0100 (Thu, 02 Nov 2017)
* Revision: 50141
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_ints.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_ints_h
* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017)
* Revision: 49005
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_ioc_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_memmap_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_pka_h
* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017)
* Revision: 49733
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_pka_int_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_pka_ram_h
* Revised: 2017-05-06 20:38:09 +0200 (Sat, 06 May 2017)
* Revision: 48921
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_prcm_h
* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017)
* Revision: 49733
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_rfc_dbell_h
* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018)
* Revision: 51887
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_rfc_pwr_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_rfc_rat_h
* Revised: 2018-04-16 11:16:52 +0200 (Mon, 16 Apr 2018)
* Revision: 51887
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_rfc_ullram_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.
third_party/ti/devices/cc13x2_cc26x2/inc/hw_smph.h
Vendored
+2 -2
View File
@@ -1,7 +1,7 @@
/******************************************************************************
* Filename: hw_smph_h
* Revised: 2017-01-10 11:54:43 +0100 (Tue, 10 Jan 2017)
* Revision: 48190
* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
* Revision: 51990
*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
* All rights reserved.

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